At the moment the sun4i EMAC driver relies on hardcoded CONFIG_MACPWR Kconfig symbols to enable potential PHY regulators. As we want to get rid of those, we need to find the regulator by chasing up the DT.

The sun4i-emac binding puts the PHY regulator into the MDIO node, which is the parent of the PHY device. U-Boot does not have (and does not need) an MDIO driver, so we need to chase down the regulator through the EMAC node: we follow the "phy-handle" property to find the PHY node, then go up to its parent, where we find the "phy-supply" link to the regulator. Let U-Boot find the associated regulator device, and put that into the private device struct, so we can find and enable the regulator at probe time, later.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- drivers/net/sunxi_emac.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)

diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 4c90d4b4981..f1f0e5bbbb2 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -17,6 +17,7 @@ #include <net.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <power/regulator.h>

/* EMAC register */ struct emac_regs { @@ -165,6 +166,7 @@ struct emac_eth_dev { struct phy_device *phydev; int link_printed; uchar rx_buf[EMAC_RX_BUFSIZE]; + struct udevice *phy_reg; };

struct emac_rxhdr { @@ -572,6 +574,9 @@ static int sunxi_emac_eth_probe(struct udevice *dev) if (ret) return ret;

+ if (priv->phy_reg) + regulator_set_enable(priv->phy_reg, true); + return sunxi_emac_init_phy(priv, dev); }

@@ -585,9 +590,43 @@ static const struct eth_ops sunxi_emac_eth_ops = { static int sunxi_emac_eth_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + ofnode mdio_node; + int ret;

pdata->iobase = dev_read_addr(dev);

+ /* The PHY regulator is in the MDIO node, not the EMAC or PHY node. */ + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "failed to get PHY node\n"); + return ret; + } + + /* + * U-Boot does not have (and does not need) a device driver for the + * MDIO device, so just "pass through" that DT node to get to the + * regulator phandle. + * The PHY regulator is optional, though: ignore if we cannot find + * a phy-supply property. + */ + mdio_node = ofnode_get_parent(args.node); + ret= ofnode_parse_phandle_with_args(mdio_node, "phy-supply", NULL, 0, 0, + &args); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get PHY supply node\n"); + return ret; + } + if (!ret) { + ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR, args.node, + &priv->phy_reg); + if (ret) { + dev_err(dev, "failed to get PHY regulator node\n"); + return ret; + } + } + return 0; }

The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and use a DM driver there, we should use the DT instead of hardcoding this.

Add code to the sun8i_emac and sunxi_emac drivers to check the DT for that regulator and enable it, at probe time. Then drop the current code from board.c, which was doing that job before. This allows us to remove the MACPWR Kconfig definition and the respective values from the defconfigs.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/mach-sunxi/Kconfig | 7 ------- board/sunxi/board.c | 12 +----------- configs/Bananapi_M2_Ultra_defconfig | 1 - configs/Bananapi_defconfig | 1 - configs/Bananapro_defconfig | 1 - configs/Lamobo_R1_defconfig | 1 - configs/Mele_A1000_defconfig | 1 - configs/Orangepi_defconfig | 1 - configs/Orangepi_mini_defconfig | 1 - configs/bananapi_m1_plus_defconfig | 1 - configs/bananapi_m2_plus_h3_defconfig | 1 - configs/bananapi_m2_plus_h5_defconfig | 1 - configs/i12-tvbox_defconfig | 1 - configs/jesurun_q5_defconfig | 1 - configs/mixtile_loftq_defconfig | 1 - configs/nanopi_m1_plus_defconfig | 1 - configs/nanopi_neo_plus2_defconfig | 1 - configs/nanopi_r1s_h5_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_plus2e_defconfig | 1 - configs/orangepi_plus_defconfig | 1 - configs/orangepi_win_defconfig | 1 - configs/pine_h64_defconfig | 1 - configs/zeropi_defconfig | 1 - drivers/net/sun8i_emac.c | 9 +++++++-- 25 files changed, 8 insertions(+), 42 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index a7c5ae80a1e..dff9f5ea947 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -695,13 +695,6 @@ config OLD_SUNXI_KERNEL_COMPAT Set this to enable various workarounds for old kernels, this results in sub-optimal settings for newer kernels, only enable if needed.

-config MACPWR - string "MAC power pin" - default "" - help - Set the pin used to power the MAC. This takes a string in the format - understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - config MMC1_PINS_PH bool "Pins for mmc1 are on Port H" depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 7ac50c4ae8c..2db4a2d73ca 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -187,7 +187,7 @@ enum env_location env_get_location(enum env_operation op, int prio) /* add board specific code here */ int board_init(void) { - __maybe_unused int id_pfr1, ret, macpwr_pin; + __maybe_unused int id_pfr1, ret;

gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);

@@ -224,15 +224,6 @@ int board_init(void) if (ret) return ret;

- /* strcmp() would look better, but doesn't get optimised away. */ - if (CONFIG_MACPWR[0]) { - macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); - if (macpwr_pin >= 0) { - gpio_request(macpwr_pin, "macpwr"); - gpio_direction_output(macpwr_pin, 1); - } - } - #if CONFIG_IS_ENABLED(DM_I2C) /* * Temporary workaround for enabling I2C clocks until proper sunxi DM @@ -240,7 +231,6 @@ int board_init(void) */ i2c_init_board(); #endif - eth_init_board();

return 0; diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index a5fe76af568..2cc7bbbd8b7 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 -CONFIG_MACPWR="PA17" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH23" CONFIG_USB2_VBUS_PIN="PH23" diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 6c2a1f630e8..f4910ba13ac 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_MACPWR="PH23" CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 94fd74754ea..02be8971df9 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_MACPWR="PH23" CONFIG_USB1_VBUS_PIN="PH0" CONFIG_USB2_VBUS_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 9639cb6aad9..66f57ab3c85 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_MACPWR="PH23" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index f5b6d908cdc..9ac2e4839d9 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" CONFIG_SPL=y CONFIG_MACH_SUN4I=y -CONFIG_MACPWR="PH15" CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index c89a9a1f9dd..53edf525ec0 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_MACPWR="PH23" CONFIG_USB1_VBUS_PIN="PH26" CONFIG_USB2_VBUS_PIN="PH22" CONFIG_VIDEO_VGA=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index fe9ce808a1e..ccf32670170 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_MACPWR="PH23" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="PH26" CONFIG_USB2_VBUS_PIN="PH22" diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 0fbb619d623..a432a01f6b4 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_MACPWR="PH23" CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index 26ced59fb02..a8f9b5044b0 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index fb6c945919a..1634f626190 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus" CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 257dd89af45..37f0f53ae7d 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 0ff666b2ee5..c99be7cea4e 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 -CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 0e4cdc44670..2f92228eb7b 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=251 -CONFIG_MACPWR="PA21" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 76655d79ae0..078e98b644d 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 924ff38f17c..85ff31c6fe5 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig index 27cf172d72a..2a6f94afe40 100644 --- a/configs/nanopi_r1s_h5_defconfig +++ b/configs/nanopi_r1s_h5_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 777af8c60ea..fb6fbaf787a 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 -CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 138a6a72b8c..5e2cbc48ea2 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index ed585881d49..092ce77a6c4 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 -CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index df11ad8c8fd..3ddaf050a48 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" CONFIG_SPL=y CONFIG_MACH_SUN50I=y -CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 6dac6098d04..4712b8e4694 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y -CONFIG_MACPWR="PC16" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig index 11f3715e6dc..7901bffd159 100644 --- a/configs/zeropi_defconfig +++ b/configs/zeropi_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 -CONFIG_MACPWR="PD6" # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 04c3274fbe1..7b60a60ad52 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -29,6 +29,7 @@ #include <net.h> #include <reset.h> #include <wait_bit.h> +#include <power/regulator.h>

#define MDIO_CMD_MII_BUSY BIT(0) #define MDIO_CMD_MII_WRITE BIT(1) @@ -167,9 +168,8 @@ struct emac_eth_dev { struct clk ephy_clk; struct reset_ctl tx_rst; struct reset_ctl ephy_rst; -#if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; -#endif + struct udevice *phy_reg; };

@@ -720,6 +720,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev)

sun8i_emac_set_syscon(sun8i_pdata, priv);

+ if (priv->phy_reg) + regulator_set_enable(priv->phy_reg, true); + sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name);

@@ -829,6 +832,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)

priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;

+ device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg); + pdata->phy_interface = -1; priv->phyaddr = -1; priv->use_internal_phy = false;

So far we were open-coding the pincontroller's GPIO output/input access in each function using that.

Provide functions that wrap that nicely, and follow the existing pattern (set/get_{bank,}), so users don't need to know about the internals, and we can abstract the new D1 pinctrl more easily.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/gpio.h | 4 +++ arch/arm/mach-sunxi/pinmux.c | 28 +++++++++++++++ drivers/gpio/sunxi_gpio.c | 49 +++++--------------------- 3 files changed, 40 insertions(+), 41 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 6eaeece4e24..26b7294f9c7 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -221,6 +221,10 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); void sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); int sunxi_gpio_get_cfgpin(u32 pin); +void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set); +void sunxi_gpio_set_output(u32 pin, bool set); +int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin); +int sunxi_gpio_get_output(u32 pin); void sunxi_gpio_set_drv(u32 pin, u32 val); void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); void sunxi_gpio_set_pull(u32 pin, u32 val); diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index c95fcee9f6c..751cac8e099 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -45,6 +45,34 @@ int sunxi_gpio_get_cfgpin(u32 pin) return sunxi_gpio_get_cfgbank(pio, pin); }

+void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set) +{ + u32 mask = 1U << GPIO_NUM(pin); + + clrsetbits_le32(&pio->dat, set ? 0 : mask, set ? mask : 0); +} + +void sunxi_gpio_set_output(u32 pin, bool set) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + sunxi_gpio_set_output_bank(pio, pin, set); +} + +int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin) +{ + return !!(readl(&pio->dat) & (1U << GPIO_NUM(pin))); +} + +int sunxi_gpio_get_output(u32 pin) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + return sunxi_gpio_get_output_bank(pio, pin); +} + void sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index f0b42e4fdb7..6dbf0e368f9 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -19,37 +19,6 @@ #include <dt-bindings/gpio/gpio.h>

#if !CONFIG_IS_ENABLED(DM_GPIO) -static int sunxi_gpio_output(u32 pin, u32 val) -{ - u32 dat; - u32 bank = GPIO_BANK(pin); - u32 num = GPIO_NUM(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); - - dat = readl(&pio->dat); - if (val) - dat |= 0x1 << num; - else - dat &= ~(0x1 << num); - - writel(dat, &pio->dat); - - return 0; -} - -static int sunxi_gpio_input(u32 pin) -{ - u32 dat; - u32 bank = GPIO_BANK(pin); - u32 num = GPIO_NUM(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); - - dat = readl(&pio->dat); - dat >>= num; - - return dat & 0x1; -} - int gpio_request(unsigned gpio, const char *label) { return 0; @@ -70,18 +39,21 @@ int gpio_direction_input(unsigned gpio) int gpio_direction_output(unsigned gpio, int value) { sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); + sunxi_gpio_set_output(gpio, value);

- return sunxi_gpio_output(gpio, value); + return 0; }

int gpio_get_value(unsigned gpio) { - return sunxi_gpio_input(gpio); + return sunxi_gpio_get_output(gpio); }

int gpio_set_value(unsigned gpio, int value) { - return sunxi_gpio_output(gpio, value); + sunxi_gpio_set_output(gpio, value); + + return 0; }

int sunxi_name_to_gpio(const char *name) @@ -131,13 +103,8 @@ int sunxi_name_to_gpio(const char *name) static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) { struct sunxi_gpio_plat *plat = dev_get_plat(dev); - u32 num = GPIO_NUM(offset); - unsigned dat; - - dat = readl(&plat->regs->dat); - dat >>= num;

- return dat & 0x1; + return sunxi_gpio_get_output_bank(plat->regs, offset) & 0x1; }

static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) @@ -177,7 +144,7 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); u32 num = GPIO_NUM(offset);

- clrsetbits_le32(&plat->regs->dat, 1 << num, value << num); + sunxi_gpio_set_output_bank(plat->regs, num, value); sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); } else if (flags & GPIOD_IS_IN) { u32 pull = 0;

So far every Allwinner SoC used the same basic pincontroller/GPIO register frame, and just differed by the number of implemented banks and pins, plus some special functionality from time to time. However the D1 and successors use a slightly different pinctrl register layout. Use that opportunity to drop "struct sunxi_gpio", that described that MMIO frame in a C struct. That approach is somewhat frowned upon in the Linux world and rarely used there, though still popular with U-Boot.

Switching from a C struct to a "base address plus offset" approach allows to switch between the two models more dynamically, without reverting to preprocessor macros and #ifdef's.

Model the pinctrl MMIO register frame in the usual "base address + offset" way, and replace a hard-to-parse CPP macro with a more readable static function. All the users get converted over. There are no functional changes at this point, it just prepares the stages for the D1 and friends.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/gpio.h | 67 +++++++++++--------------- arch/arm/mach-sunxi/pinmux.c | 66 +++++++++++++------------ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 +++--- 3 files changed, 71 insertions(+), 76 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 26b7294f9c7..b12bdbd2739 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -28,13 +28,6 @@ #define SUNXI_GPIO_H 7 #define SUNXI_GPIO_I 8

-/* - * This defines the number of GPIO banks for the _main_ GPIO controller. - * You should fix up the padding in struct sunxi_gpio_reg below if you - * change this. - */ -#define SUNXI_GPIO_BANKS 9 - /* * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) * at a different register offset. @@ -52,46 +45,42 @@ #define SUNXI_GPIO_M 12 #define SUNXI_GPIO_N 13

-struct sunxi_gpio { - u32 cfg[4]; - u32 dat; - u32 drv[2]; - u32 pull[2]; -}; - -/* gpio interrupt control */ -struct sunxi_gpio_int { - u32 cfg[3]; - u32 ctl; - u32 sta; - u32 deb; /* interrupt debounce */ -}; - -struct sunxi_gpio_reg { - struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; - u8 res[0xbc]; - struct sunxi_gpio_int gpio_int; -}; - #define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348

-#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ - &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) - #define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f)

+#define GPIO_CFG_REG_OFFSET 0x00 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)

+#define GPIO_DAT_REG_OFFSET 0x10 + +#define GPIO_DRV_REG_OFFSET 0x14 #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)

+#define GPIO_PULL_REG_OFFSET 0x1c #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)

+#define SUNXI_PINCTRL_BANK_SIZE 0x24 + +static inline void* BANK_TO_GPIO(int bank) +{ + void *pio_base; + + if (bank < SUNXI_GPIO_L) { + pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE; + } else { + pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE; + bank -= SUNXI_GPIO_L; + } + + return pio_base + bank * SUNXI_PINCTRL_BANK_SIZE; +} + /* GPIO bank sizes */ #define SUNXI_GPIOS_PER_BANK 32

@@ -213,22 +202,22 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_AXP0_GPIO_COUNT 6

struct sunxi_gpio_plat { - struct sunxi_gpio *regs; + void *regs; char bank_name[3]; };

-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); +void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); void sunxi_gpio_set_cfgpin(u32 pin, u32 val); -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); int sunxi_gpio_get_cfgpin(u32 pin); -void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set); +void sunxi_gpio_set_output_bank(void *bank_base, int pin, bool set); void sunxi_gpio_set_output(u32 pin, bool set); -int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin); +int sunxi_gpio_get_output_bank(void *bank_base, int pin); int sunxi_gpio_get_output(u32 pin); void sunxi_gpio_set_drv(u32 pin, u32 val); -void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); void sunxi_gpio_set_pull(u32 pin, u32 val); -void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val); +void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); int sunxi_name_to_gpio(const char *name);

#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index 751cac8e099..17d1a7bdb97 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -9,29 +9,30 @@ #include <asm/io.h> #include <asm/arch/gpio.h>

-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) +void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val) { - u32 index = GPIO_CFG_INDEX(bank_offset); - u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 index = GPIO_CFG_INDEX(pin_offset); + u32 offset = GPIO_CFG_OFFSET(pin_offset);

- clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset); + clrsetbits_le32(bank_base + GPIO_CFG_REG_OFFSET + index * 4, + 0xfU << offset, val << offset); }

void sunxi_gpio_set_cfgpin(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *pio = BANK_TO_GPIO(bank);

- sunxi_gpio_set_cfgbank(pio, pin, val); + sunxi_gpio_set_cfgbank(pio, pin % 32, val); }

-int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset) { - u32 index = GPIO_CFG_INDEX(bank_offset); - u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 index = GPIO_CFG_INDEX(pin_offset); + u32 offset = GPIO_CFG_OFFSET(pin_offset); u32 cfg;

- cfg = readl(&pio->cfg[index]); + cfg = readl(bank_base + GPIO_CFG_REG_OFFSET + index * 4); cfg >>= offset;

return cfg & 0xf; @@ -40,35 +41,38 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) int sunxi_gpio_get_cfgpin(u32 pin) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *bank_base = BANK_TO_GPIO(bank);

- return sunxi_gpio_get_cfgbank(pio, pin); + return sunxi_gpio_get_cfgbank(bank_base, pin % 32); }

-void sunxi_gpio_set_output_bank(struct sunxi_gpio *pio, int pin, bool set) +void sunxi_gpio_set_output_bank(void *bank_base, int pin, bool set) { u32 mask = 1U << GPIO_NUM(pin);

- clrsetbits_le32(&pio->dat, set ? 0 : mask, set ? mask : 0); + clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET, + set ? 0 : mask, set ? mask : 0); }

void sunxi_gpio_set_output(u32 pin, bool set) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *pio = BANK_TO_GPIO(bank);

sunxi_gpio_set_output_bank(pio, pin, set); }

-int sunxi_gpio_get_output_bank(struct sunxi_gpio *pio, int pin) +int sunxi_gpio_get_output_bank(void *bank_base, int pin) { - return !!(readl(&pio->dat) & (1U << GPIO_NUM(pin))); + u32 mask = 1U << GPIO_NUM(pin); + + return !!(readl(bank_base + GPIO_DAT_REG_OFFSET) & mask); }

int sunxi_gpio_get_output(u32 pin) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *pio = BANK_TO_GPIO(bank);

return sunxi_gpio_get_output_bank(pio, pin); } @@ -76,31 +80,33 @@ int sunxi_gpio_get_output(u32 pin) void sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *bank_base = BANK_TO_GPIO(bank);

- sunxi_gpio_set_drv_bank(pio, pin, val); + sunxi_gpio_set_drv_bank(bank_base, pin % 32, val); }

-void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val) { - u32 index = GPIO_DRV_INDEX(bank_offset); - u32 offset = GPIO_DRV_OFFSET(bank_offset); + u32 index = GPIO_DRV_INDEX(pin_offset); + u32 offset = GPIO_DRV_OFFSET(pin_offset);

- clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset); + clrsetbits_le32(bank_base + GPIO_DRV_REG_OFFSET + index * 4, + 0x3U << offset, val << offset); }

void sunxi_gpio_set_pull(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + void *bank_base = BANK_TO_GPIO(bank);

- sunxi_gpio_set_pull_bank(pio, pin, val); + sunxi_gpio_set_pull_bank(bank_base, pin % 32, val); }

-void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) +void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val) { - u32 index = GPIO_PULL_INDEX(bank_offset); - u32 offset = GPIO_PULL_OFFSET(bank_offset); + u32 index = GPIO_PULL_INDEX(pin_offset); + u32 offset = GPIO_PULL_OFFSET(pin_offset);

- clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset); + clrsetbits_le32(bank_base + GPIO_PULL_REG_OFFSET + index * 4, + 0x3U << offset, val << offset); } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index e5102180902..946447e9136 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -35,7 +35,7 @@ struct sunxi_pinctrl_desc { };

struct sunxi_pinctrl_plat { - struct sunxi_gpio __iomem *base; + void __iomem *base; };

static int sunxi_pinctrl_get_pins_count(struct udevice *dev) @@ -86,8 +86,8 @@ static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector, sunxi_pinctrl_get_function_name(dev, func_selector), desc->functions[func_selector].mux);

- sunxi_gpio_set_cfgbank(plat->base + bank, pin, - desc->functions[func_selector].mux); + sunxi_gpio_set_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE, + pin, desc->functions[func_selector].mux);

return 0; } @@ -102,7 +102,7 @@ static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = { static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat, uint bank, uint pin, uint bias) { - struct sunxi_gpio *regs = &plat->base[bank]; + void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE;

sunxi_gpio_set_pull_bank(regs, pin, bias);

@@ -112,7 +112,7 @@ static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat, static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat, uint bank, uint pin, uint drive) { - struct sunxi_gpio *regs = &plat->base[bank]; + void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE;

if (drive < 10 || drive > 40) return -EINVAL; @@ -148,7 +148,7 @@ static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector, struct sunxi_pinctrl_plat *plat = dev_get_plat(dev); int bank = pin_selector / SUNXI_GPIOS_PER_BANK; int pin = pin_selector % SUNXI_GPIOS_PER_BANK; - int mux = sunxi_gpio_get_cfgbank(plat->base + bank, pin); + int mux = sunxi_gpio_get_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE, pin);

switch (mux) { case SUNXI_GPIO_INPUT: @@ -206,7 +206,7 @@ static int sunxi_pinctrl_bind(struct udevice *dev) if (!gpio_plat) return -ENOMEM;

- gpio_plat->regs = plat->base + i; + gpio_plat->regs = plat->base + i * SUNXI_PINCTRL_BANK_SIZE; gpio_plat->bank_name[0] = 'P'; gpio_plat->bank_name[1] = 'A' + desc->first_bank + i; gpio_plat->bank_name[2] = '\0';

On the Allwinner platform we were describing a quite comprehensive memory map in a per-SoC header unser arch/arm. In the old days that was used by every driver, but nowadays it should only be needed by SPL drivers (not using the DT). Many addresses in there were never used, and some are not needed anymore.

To avoid a dependency on CPU specific headers in an arch specific directory, move the definition of the pinctroller MMIO base address into the sunxi_gpio.h header, because the SPL routines for GPIO should be the only one needing this address. This is a first step towards getting rid of cpu_sun[x]i.h completely, and allows to remove the inclusion of that file from the sunxi_gpio.h header.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 -- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 2 -- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 -- include/sunxi_gpio.h | 12 +++++++++++- 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index f7ecc790dbf..d6fe51f24bc 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -91,7 +91,6 @@

#define SUNXI_CCM_BASE 0x01c20000 #define SUNXI_INTC_BASE 0x01c20400 -#define SUNXI_PIO_BASE 0x01c20800 #define SUNXI_TIMER_BASE 0x01c20c00 #ifndef CONFIG_SUNXI_GEN_SUN6I #define SUNXI_PWM_BASE 0x01c20e00 @@ -210,7 +209,6 @@ defined(CONFIG_MACH_SUN50I)

#define SUNXI_R_TWI_BASE 0x01f02400 #define SUNXI_R_UART_BASE 0x01f02800 -#define SUNXI_R_PIO_BASE 0x01f02c00 #define SUN6I_P2WI_BASE 0x01f03400 #define SUNXI_RSB_BASE 0x01f03400

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index d9cf8ae0428..9b6bf843601 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -22,7 +22,6 @@ #define SUNXI_SIDC_BASE 0x03006000 #define SUNXI_SID_BASE 0x03006200 #define SUNXI_TIMER_BASE 0x03009000 -#define SUNXI_PIO_BASE 0x0300B000 #define SUNXI_PSI_BASE 0x0300C000

#define SUNXI_GIC400_BASE 0x03020000 @@ -68,7 +67,6 @@ #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 #define SUNXI_R_WDOG_BASE 0x07020400 -#define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 9c2d11b5901..20025be2319 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -81,7 +81,6 @@ /* APB0 Module */ #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) #define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) -#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) @@ -102,7 +101,6 @@ /* RCPUS Module */ #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) #define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) -#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)

/* Misc. */ diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index b12bdbd2739..fe89ff89bfa 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -9,7 +9,17 @@ #define _SUNXI_GPIO_H

#include <linux/types.h> -#include <asm/arch/cpu.h> + +#if defined(CONFIG_MACH_SUN9I) +#define SUNXI_PIO_BASE 0x06000800 +#define SUNXI_R_PIO_BASE 0x08002c00 +#elif defined(CONFIG_SUN50I_GEN_H6) +#define SUNXI_PIO_BASE 0x0300b000 +#define SUNXI_R_PIO_BASE 0x07022000 +#else +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#endif

/* * sunxi has 9 banks of gpio, they are:

The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL. Just enable that when we program that PLL.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 1 + arch/arm/mach-sunxi/clock_sun50i_h6.c | 12 +++++++----- 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 37df4410eaa..9895c2c220e 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -228,6 +228,7 @@ struct sunxi_ccm_reg {

/* pll1 bit field */ #define CCM_PLL1_CTRL_EN BIT(31) +#define CCM_PLL1_LDO_EN BIT(30) #define CCM_PLL1_LOCK_EN BIT(29) #define CCM_PLL1_LOCK BIT(28) #define CCM_PLL1_OUT_EN BIT(27) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 7926394cf76..90110eab101 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -86,11 +86,13 @@ void clock_set_pll1(unsigned int clk) writel(val, &ccm->cpu_axi_cfg);

/* clk = 24*n/p, p is ignored if clock is >288MHz */ - writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 | -#ifdef CONFIG_MACH_SUN50I_H616 - CCM_PLL1_OUT_EN | -#endif - CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); + val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2; + val |= CCM_PLL1_CTRL_N(clk / 24000000); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + val |= CCM_PLL1_OUT_EN; + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN; + writel(val, &ccm->pll1_cfg); while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}

/* Switch CPU to PLL1 */

The Allwinner D1/R528/T113 SoCs have a very minimal separate "management" power plane, with almost no device attached to it (so no r_i2c or r_uart). This means we don't need to flip any clock gates in the PRCM block, which in fact those SoCs do not have.

Prepare the code for those SoCs by making the PRCM block optional in the H6 SPL clock code, which we otherwise share to this new family of SoCs. If the memory map (cpu.h) does not define the PRCM address, we simply skip any attempt to program gates there.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 607efe6a9c1..c3a4623d345 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -4,14 +4,20 @@ #include <asm/arch/clock.h> #include <asm/arch/prcm.h>

+#ifndef SUNXI_PRCM_BASE +#define SUNXI_PRCM_BASE 0 +#endif + #ifdef CONFIG_SPL_BUILD -void clock_init_safe(void) + +static void clock_init_safe_prcm(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct sunxi_prcm_reg *const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;

+ if (!prcm) + return; + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { /* this seems to enable PLLs on H616 */ setbits_le32(&prcm->sys_pwroff_gating, 0x10); @@ -27,6 +33,14 @@ void clock_init_safe(void) /* set PLL VDD LDO output to 1.14 V */ setbits_le32(&prcm->pll_ldo_cfg, 0x60000); } +} + +void clock_init_safe(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + clock_init_safe_prcm();

clock_set_pll1(408000000);

@@ -141,6 +155,8 @@ int clock_twi_onoff(int port, int state) value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);

if (port == 5) { + if (!prcm) + return -ENODEV; shift = 0; ptr = &prcm->twi_gate_reset; } else {

The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and cleaned up, to match previous DRAM routines for other SoCs, and also to be closer to U-Boot's coding style and support routines. The actual DRAM chip timing parameters are included in the main file, since they cover all DRAM types, and are protected by a new Kconfig CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only the relevant settings, at build time.

The relevant DRAM chips/board specific configuration parameters are delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- drivers/Makefile | 1 + drivers/ram/Makefile | 3 + drivers/ram/sunxi/Kconfig | 59 ++ drivers/ram/sunxi/Makefile | 4 + drivers/ram/sunxi/dram_sun20i_d1.c | 1432 ++++++++++++++++++++++++++++ drivers/ram/sunxi/dram_sun20i_d1.h | 73 ++ 6 files changed, 1572 insertions(+) create mode 100644 drivers/ram/sunxi/Makefile create mode 100644 drivers/ram/sunxi/dram_sun20i_d1.c create mode 100644 drivers/ram/sunxi/dram_sun20i_d1.h

diff --git a/drivers/Makefile b/drivers/Makefile index 3bc6d279d7c..bdb19ef9275 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/ +obj-$(CONFIG_DRAM_SUN8I_R528) += ram/ obj-$(CONFIG_SPL_DM_RESET) += reset/ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 6eb1a241359..b4750ea11c4 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -23,6 +23,9 @@ obj-$(CONFIG_RAM_SIFIVE) += sifive/ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ endif + +obj-$(CONFIG_DRAM_SUN8I_R528) += sunxi/ + obj-$(CONFIG_ARCH_OCTEON) += octeon/

obj-$(CONFIG_ARCH_RMOBILE) += renesas/ diff --git a/drivers/ram/sunxi/Kconfig b/drivers/ram/sunxi/Kconfig index 97e261de542..657f47a870f 100644 --- a/drivers/ram/sunxi/Kconfig +++ b/drivers/ram/sunxi/Kconfig @@ -11,3 +11,62 @@ config DRAM_SUN8I_R528 default y if MACH_SUN8I_R528 help Select this DRAM controller driver for the R528/T113s SoCs. + +if DRAM_SUN20I_D1 || DRAM_SUN8I_R528 + +config DRAM_SUNXI_ODT_EN + hex "DRAM ODT EN parameter" + default 0x1 + help + ODT EN value from vendor DRAM settings. + +config DRAM_SUNXI_TPR0 + hex "DRAM TPR0 parameter" + default 0x0 + help + TPR0 value from vendor DRAM settings. + +config DRAM_SUNXI_TPR11 + hex "DRAM TPR11 parameter" + default 0x0 + help + TPR11 value from vendor DRAM settings. + +config DRAM_SUNXI_TPR12 + hex "DRAM TPR12 parameter" + default 0x0 + help + TPR12 value from vendor DRAM settings. + +config DRAM_SUNXI_TPR13 + hex "DRAM TPR13 parameter" + default 0x0 + help + TPR13 value from vendor DRAM settings. It tells which features + should be configured. + +choice + prompt "DRAM chip type" + default SUNXI_DRAM_TYPE_DDR3 if DRAM_SUN8I_R528 || DRAM_SUN20I_D1 + +config SUNXI_DRAM_TYPE_DDR2 + bool "DDR2 chips" + +config SUNXI_DRAM_TYPE_DDR3 + bool "DDR3 chips" + +config SUNXI_DRAM_TYPE_LPDDR2 + bool "LPDDR2 chips" + +config SUNXI_DRAM_TYPE_LPDDR3 + bool "LPDDR3 chips" +endchoice + +config SUNXI_DRAM_TYPE + int + default 2 if SUNXI_DRAM_TYPE_DDR2 + default 3 if SUNXI_DRAM_TYPE_DDR3 + default 6 if SUNXI_DRAM_TYPE_LPDDR2 + default 7 if SUNXI_DRAM_TYPE_LPDDR3 + +endif diff --git a/drivers/ram/sunxi/Makefile b/drivers/ram/sunxi/Makefile new file mode 100644 index 00000000000..d6fb2cf0b65 --- /dev/null +++ b/drivers/ram/sunxi/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_DRAM_SUN20I_D1) += dram_sun20i_d1.o +obj-$(CONFIG_DRAM_SUN8I_R528) += dram_sun20i_d1.o diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c new file mode 100644 index 00000000000..c766fc24065 --- /dev/null +++ b/drivers/ram/sunxi/dram_sun20i_d1.c @@ -0,0 +1,1432 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Allwinner D1/D1s/R528/T113-sx DRAM initialisation + * + * As usual there is no documentation for the memory controller or PHY IP + * used here. The baseline of this code was lifted from awboot[1], which + * seems to be based on some form of de-compilation of some original Allwinner + * code bits (with a GPL2 license tag from the very beginning). + * This version here is a reworked version, to match the U-Boot coding style + * and style of the other Allwinner DRAM drivers. + * + * [1] https://github.com/szemzoa/awboot.git + */ + +#include <asm/io.h> +#include <common.h> +#ifdef CONFIG_RAM + #include <dm.h> + #include <ram.h> +#endif +#include <linux/delay.h> + +#include "dram_sun20i_d1.h" + +#ifndef SUNXI_SID_BASE +#define SUNXI_SID_BASE 0x3006200 +#endif + +#ifndef SUNXI_CCM_BASE +#define SUNXI_CCM_BASE 0x2001000 +#endif + +static void sid_read_ldoB_cal(const dram_para_t *para) +{ + uint32_t reg; + + reg = (readl(SUNXI_SID_BASE + 0x1c) & 0xff00) >> 8; + + if (reg == 0) + return; + + switch (para->dram_type) { + case SUNXI_DRAM_TYPE_DDR2: + break; + case SUNXI_DRAM_TYPE_DDR3: + if (reg > 0x20) + reg -= 0x16; + break; + default: + reg = 0; + break; + } + + clrsetbits_le32(0x3000150, 0xff00, reg << 8); +} + +static void dram_voltage_set(const dram_para_t *para) +{ + int vol; + + switch (para->dram_type) { + case SUNXI_DRAM_TYPE_DDR2: + vol = 47; + break; + case SUNXI_DRAM_TYPE_DDR3: + vol = 25; + break; + default: + vol = 0; + break; + } + + clrsetbits_le32(0x3000150, 0x20ff00, vol << 8); + + udelay(1); + + sid_read_ldoB_cal(para); +} + +static void dram_enable_all_master(void) +{ + writel(~0, 0x3102020); + writel(0xff, 0x3102024); + writel(0xffff, 0x3102028); + udelay(10); +} + +static void dram_disable_all_master(void) +{ + writel(1, 0x3102020); + writel(0, 0x3102024); + writel(0, 0x3102028); + udelay(10); +} + +static void eye_delay_compensation(const dram_para_t *para) +{ + uint32_t delay; + unsigned long ptr; + + // DATn0IOCR, n = 0...7 + delay = (para->dram_tpr11 & 0xf) << 9; + delay |= (para->dram_tpr12 & 0xf) << 1; + for (ptr = 0x3103310; ptr < 0x3103334; ptr += 4) + setbits_le32(ptr, delay); + + // DATn1IOCR, n = 0...7 + delay = (para->dram_tpr11 & 0xf0) << 5; + delay |= (para->dram_tpr12 & 0xf0) >> 3; + for (ptr = 0x3103390; ptr != 0x31033b4; ptr += 4) + setbits_le32(ptr, delay); + + // PGCR0: assert AC loopback FIFO reset + clrbits_le32(0x3103100, 0x04000000); + + // ?? + + delay = (para->dram_tpr11 & 0xf0000) >> 7; + delay |= (para->dram_tpr12 & 0xf0000) >> 15; + setbits_le32(0x3103334, delay); + setbits_le32(0x3103338, delay); + + delay = (para->dram_tpr11 & 0xf00000) >> 11; + delay |= (para->dram_tpr12 & 0xf00000) >> 19; + setbits_le32(0x31033b4, delay); + setbits_le32(0x31033b8, delay); + + setbits_le32(0x310333c, (para->dram_tpr11 & 0xf0000) << 9); + setbits_le32(0x31033bc, (para->dram_tpr11 & 0xf00000) << 5); + + // PGCR0: release AC loopback FIFO reset + setbits_le32(0x3103100, BIT(26)); + + udelay(1); + + delay = (para->dram_tpr10 & 0xf0) << 4; + for (ptr = 0x3103240; ptr != 0x310327c; ptr += 4) + setbits_le32(ptr, delay); + for (ptr = 0x3103228; ptr != 0x3103240; ptr += 4) + setbits_le32(ptr, delay); + + setbits_le32(0x3103218, (para->dram_tpr10 & 0x0f) << 8); + setbits_le32(0x310321c, (para->dram_tpr10 & 0x0f) << 8); + + setbits_le32(0x3103280, (para->dram_tpr10 & 0xf00) >> 4); +} + +/* + * Main purpose of the auto_set_timing routine seems to be to calculate all + * timing settings for the specific type of sdram used. Read together with + * an sdram datasheet for context on the various variables. + */ +static void mctl_set_timing_params(const dram_para_t *para, + const dram_config_t *config) +{ + /* DRAM_TPR0 */ + u8 tccd = 2; + u8 tfaw; + u8 trrd; + u8 trcd; + u8 trc; + + /* DRAM_TPR1 */ + u8 txp; + u8 twtr; + u8 trtp = 4; + u8 twr; + u8 trp; + u8 tras; + + /* DRAM_TPR2 */ + u16 trefi; + u16 trfc; + + u8 tcksrx; + u8 tckesr; + u8 trd2wr; + u8 twr2rd; + u8 trasmax; + u8 twtp; + u8 tcke; + u8 tmod; + u8 tmrd; + u8 tmrw; + + u8 tcl; + u8 tcwl; + u8 t_rdata_en; + u8 wr_latency; + + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; + + u32 tdinit0; + u32 tdinit1; + u32 tdinit2; + u32 tdinit3; + + switch (para->dram_type) { + case SUNXI_DRAM_TYPE_DDR2: + /* DRAM_TPR0 */ + tfaw = ns_to_t(50); + trrd = ns_to_t(10); + trcd = ns_to_t(20); + trc = ns_to_t(65); + + /* DRAM_TPR1 */ + txp = 2; + twtr = ns_to_t(8); + twr = ns_to_t(15); + trp = ns_to_t(15); + tras = ns_to_t(45); + + /* DRAM_TRP2 */ + trfc = ns_to_t(328); + trefi = ns_to_t(7800) / 32; + + trasmax = CONFIG_DRAM_CLK / 30; + if (CONFIG_DRAM_CLK < 409) { + t_rdata_en = 1; + tcl = 3; + mr0 = 0x06a3; + } else { + t_rdata_en = 2; + tcl = 4; + mr0 = 0x0e73; + } + tmrd = 2; + twtp = twr + 5; + tcksrx = 5; + tckesr = 4; + trd2wr = 4; + tcke = 3; + tmod = 12; + wr_latency = 1; + tmrw = 0; + twr2rd = twtr + 5; + tcwl = 0; + + mr1 = para->dram_mr1; + mr2 = 0; + mr3 = 0; + + tdinit0 = 200 * CONFIG_DRAM_CLK + 1; + tdinit1 = 100 * CONFIG_DRAM_CLK / 1000 + 1; + tdinit2 = 200 * CONFIG_DRAM_CLK + 1; + tdinit3 = 1 * CONFIG_DRAM_CLK + 1; + + break; + case SUNXI_DRAM_TYPE_DDR3: + trfc = ns_to_t(350); + trefi = ns_to_t(7800) / 32 + 1; // XXX + + twtr = ns_to_t(8) + 2; // + 2 ? XXX + /* Only used by trd2wr calculation, which gets discard below */ +// twr = max(ns_to_t(15), 2); + trrd = max(ns_to_t(10), 2); + txp = max(ns_to_t(10), 2); + + if (CONFIG_DRAM_CLK <= 800) { + tfaw = ns_to_t(50); + trcd = ns_to_t(15); + trp = ns_to_t(15); + trc = ns_to_t(53); + tras = ns_to_t(38); + + mr0 = 0x1c70; + mr2 = 0x18; + tcl = 6; + wr_latency = 2; + tcwl = 4; + t_rdata_en = 4; + } else { + tfaw = ns_to_t(35); + trcd = ns_to_t(14); + trp = ns_to_t(14); + trc = ns_to_t(48); + tras = ns_to_t(34); + + mr0 = 0x1e14; + mr2 = 0x20; + tcl = 7; + wr_latency = 3; + tcwl = 5; + t_rdata_en = 5; + } + + trasmax = CONFIG_DRAM_CLK / 30; + twtp = tcwl + 2 + twtr; // WL+BL/2+tWTR + /* Gets overwritten below */ +// trd2wr = tcwl + 2 + twr; // WL+BL/2+tWR + twr2rd = tcwl + twtr; // WL+tWTR + + tdinit0 = 500 * CONFIG_DRAM_CLK + 1; // 500 us + tdinit1 = 360 * CONFIG_DRAM_CLK / 1000 + 1; // 360 ns + tdinit2 = 200 * CONFIG_DRAM_CLK + 1; // 200 us + tdinit3 = 1 * CONFIG_DRAM_CLK + 1; // 1 us + + mr1 = para->dram_mr1; + mr3 = 0; + tcke = 3; + tcksrx = 5; + tckesr = 4; + if (((config->dram_tpr13 & 0xc) == 0x04) || CONFIG_DRAM_CLK < 912) + trd2wr = 5; + else + trd2wr = 6; + + tmod = 12; + tmrd = 4; + tmrw = 0; + + break; + case SUNXI_DRAM_TYPE_LPDDR2: + tfaw = max(ns_to_t(50), 4); + trrd = max(ns_to_t(10), 1); + trcd = max(ns_to_t(24), 2); + trc = ns_to_t(70); + txp = ns_to_t(8); + if (txp < 2) { + txp++; + twtr = 2; + } else { + twtr = txp; + } + twr = max(ns_to_t(15), 2); + trp = ns_to_t(17); + tras = ns_to_t(42); + trefi = ns_to_t(3900) / 32; + trfc = ns_to_t(210); + + trasmax = CONFIG_DRAM_CLK / 60; + mr3 = para->dram_mr3; + twtp = twr + 5; + mr2 = 6; + mr1 = 5; + tcksrx = 5; + tckesr = 5; + trd2wr = 10; + tcke = 2; + tmod = 5; + tmrd = 5; + tmrw = 3; + tcl = 4; + wr_latency = 1; + t_rdata_en = 1; + + tdinit0 = 200 * CONFIG_DRAM_CLK + 1; + tdinit1 = 100 * CONFIG_DRAM_CLK / 1000 + 1; + tdinit2 = 11 * CONFIG_DRAM_CLK + 1; + tdinit3 = 1 * CONFIG_DRAM_CLK + 1; + twr2rd = twtr + 5; + tcwl = 2; + mr1 = 195; + mr0 = 0; + + break; + case SUNXI_DRAM_TYPE_LPDDR3: + tfaw = max(ns_to_t(50), 4); + trrd = max(ns_to_t(10), 1); + trcd = max(ns_to_t(24), 2); + trc = ns_to_t(70); + twtr = max(ns_to_t(8), 2); + twr = max(ns_to_t(15), 2); + trp = ns_to_t(17); + tras = ns_to_t(42); + trefi = ns_to_t(3900) / 32; + trfc = ns_to_t(210); + txp = twtr; + + trasmax = CONFIG_DRAM_CLK / 60; + if (CONFIG_DRAM_CLK < 800) { + tcwl = 4; + wr_latency = 3; + t_rdata_en = 6; + mr2 = 12; + } else { + tcwl = 3; + tcke = 6; + wr_latency = 2; + t_rdata_en = 5; + mr2 = 10; + } + twtp = tcwl + 5; + tcl = 7; + mr3 = para->dram_mr3; + tcksrx = 5; + tckesr = 5; + trd2wr = 13; + tcke = 3; + tmod = 12; + tdinit0 = 400 * CONFIG_DRAM_CLK + 1; + tdinit1 = 500 * CONFIG_DRAM_CLK / 1000 + 1; + tdinit2 = 11 * CONFIG_DRAM_CLK + 1; + tdinit3 = 1 * CONFIG_DRAM_CLK + 1; + tmrd = 5; + tmrw = 5; + twr2rd = tcwl + twtr + 5; + mr1 = 195; + mr0 = 0; + + break; + default: + trfc = 128; + trp = 6; + trefi = 98; + txp = 10; + twr = 8; + twtr = 3; + tras = 14; + tfaw = 16; + trc = 20; + trcd = 6; + trrd = 3; + + twr2rd = 8; + tcksrx = 4; + tckesr = 3; + trd2wr = 4; + trasmax = 27; + twtp = 12; + tcke = 2; + tmod = 6; + tmrd = 2; + tmrw = 0; + tcwl = 3; + tcl = 3; + wr_latency = 1; + t_rdata_en = 1; + mr3 = 0; + mr2 = 0; + mr1 = 0; + mr0 = 0; + tdinit3 = 0; + tdinit2 = 0; + tdinit1 = 0; + tdinit0 = 0; + + break; + } + + /* Set mode registers */ + writel(mr0, 0x3103030); + writel(mr1, 0x3103034); + writel(mr2, 0x3103038); + writel(mr3, 0x310303c); + /* TODO: dram_odt_en is either 0x0 or 0x1, so right shift looks weird */ + writel((para->dram_odt_en >> 4) & 0x3, 0x310302c); + + /* Set dram timing DRAMTMG0 - DRAMTMG5 */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0), + 0x3103058); + writel((txp << 16) | (trtp << 8) | (trc << 0), + 0x310305c); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0), + 0x3103060); + writel((tmrw << 16) | (tmrd << 12) | (tmod << 0), + 0x3103064); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0), + 0x3103068); + writel((tcksrx << 24) | (tcksrx << 16) | (tckesr << 8) | (tcke << 0), + 0x310306c); + + /* Set dual rank timing */ + clrsetbits_le32(0x3103078, 0xf000ffff, + (CONFIG_DRAM_CLK < 800) ? 0xf0006610 : 0xf0007610); + + /* Set phy interface time PITMG0, PTR3, PTR4 */ + writel((0x2 << 24) | (t_rdata_en << 16) | BIT(8) | (wr_latency << 0), + 0x3103080); + writel(((tdinit0 << 0) | (tdinit1 << 20)), 0x3103050); + writel(((tdinit2 << 0) | (tdinit3 << 20)), 0x3103054); + + /* Set refresh timing and mode */ + writel((trefi << 16) | (trfc << 0), 0x3103090); + writel((trefi << 15) & 0x0fff0000, 0x3103094); +} + +// Purpose of this routine seems to be to initialize the PLL driving +// the MBUS and sdram. +// +static int ccu_set_pll_ddr_clk(int index, const dram_para_t *para, + const dram_config_t *config) +{ + unsigned int val, clk, n; + + if (config->dram_tpr13 & BIT(6)) + clk = para->dram_tpr9; + else + clk = para->dram_clk; + + // set VCO clock divider + n = (clk * 2) / 24; + + val = readl(SUNXI_CCM_BASE + 0x10); + val &= ~0x0007ff03; // clear dividers + val |= (n - 1) << 8; // set PLL division + val |= BIT(31) | BIT(30); // enable PLL and LDO + writel(val | BIT(29), SUNXI_CCM_BASE + 0x10); + + // wait for PLL to lock + while ((readl(SUNXI_CCM_BASE + 0x10) & BIT(28)) == 0) + ; + + udelay(20); + + // enable PLL output + setbits_le32(SUNXI_CCM_BASE + 0x0, BIT(27)); + + // turn clock gate on + val = readl(SUNXI_CCM_BASE + 0x800); + val &= ~0x03000303; // select DDR clk source, n=1, m=1 + val |= BIT(31); // turn clock on + writel(val, SUNXI_CCM_BASE + 0x800); + + return n * 24; +} + +/* Set up the PLL and clock gates for the DRAM controller and MBUS clocks. */ +static void mctl_sys_init(const dram_para_t *para, const dram_config_t *config) +{ + // assert MBUS reset + clrbits_le32(SUNXI_CCM_BASE + 0x540, BIT(30)); + + // turn off sdram clock gate, assert sdram reset + clrbits_le32(SUNXI_CCM_BASE + 0x80c, 0x10001); + clrsetbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(30), BIT(27)); + udelay(10); + + // set ddr pll clock + ccu_set_pll_ddr_clk(0, para, config); + udelay(100); + dram_disable_all_master(); + + // release sdram reset + setbits_le32(SUNXI_CCM_BASE + 0x80c, BIT(16)); + + // release MBUS reset + setbits_le32(SUNXI_CCM_BASE + 0x540, BIT(30)); + setbits_le32(SUNXI_CCM_BASE + 0x800, BIT(30)); + + udelay(5); + + // turn on sdram clock gate + setbits_le32(SUNXI_CCM_BASE + 0x80c, BIT(0)); + + // turn dram clock gate on, trigger sdr clock update + setbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(27)); + udelay(5); + + // mCTL clock enable + writel(0x8000, 0x310300c); + udelay(10); +} + +// The main purpose of this routine seems to be to copy an address configuration +// from the dram_para1 and dram_para2 fields to the PHY configuration registers +// (0x3102000, 0x3102004). +// +static void mctl_com_init(const dram_para_t *para, const dram_config_t *config) +{ + uint32_t val, width; + unsigned long ptr; + int i; + + // purpose ?? + clrsetbits_le32(0x3102008, 0x3f00, 0x2000); + + // set SDRAM type and word width + val = readl(0x3102000) & ~0x00fff000; + val |= (para->dram_type & 0x7) << 16; // DRAM type + val |= (~config->dram_para2 & 0x1) << 12; // DQ width + val |= BIT(22); // ?? + if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR2 || + para->dram_type == SUNXI_DRAM_TYPE_LPDDR3) { + val |= BIT(19); // type 6 and 7 must use 1T + } else { + if (config->dram_tpr13 & BIT(5)) + val |= BIT(19); + } + writel(val, 0x3102000); + + // init rank / bank / row for single/dual or two different ranks + if ((config->dram_para2 & BIT(8)) && + ((config->dram_para2 & 0xf000) != 0x1000)) + width = 32; + else + width = 16; + + ptr = 0x3102000; + for (i = 0; i < width; i += 16) { + val = readl(ptr) & 0xfffff000; + + val |= (config->dram_para2 >> 12) & 0x3; // rank + val |= ((config->dram_para1 >> (i + 12)) << 2) & 0x4; // bank - 2 + val |= (((config->dram_para1 >> (i + 4)) - 1) << 4) & 0xff; // row - 1 + + // convert from page size to column addr width - 3 + switch ((config->dram_para1 >> i) & 0xf) { + case 8: val |= 0xa00; break; + case 4: val |= 0x900; break; + case 2: val |= 0x800; break; + case 1: val |= 0x700; break; + default: val |= 0x600; break; + } + writel(val, ptr); + ptr += 4; + } + + // set ODTMAP based on number of ranks in use + val = (readl(0x3102000) & 0x1) ? 0x303 : 0x201; + writel(val, 0x3103120); + + // set mctl reg 3c4 to zero when using half DQ + if (config->dram_para2 & BIT(0)) + writel(0, 0x31033c4); + + // purpose ?? + if (para->dram_tpr4) { + setbits_le32(0x3102000, (para->dram_tpr4 & 0x3) << 25); + setbits_le32(0x3102004, (para->dram_tpr4 & 0x7fc) << 10); + } +} + +static const uint8_t ac_remapping_tables[][22] = { + [0] = { 0 }, + [1] = { 1, 9, 3, 7, 8, 18, 4, 13, 5, 6, 10, + 2, 14, 12, 0, 0, 21, 17, 20, 19, 11, 22 }, + [2] = { 4, 9, 3, 7, 8, 18, 1, 13, 2, 6, 10, + 5, 14, 12, 0, 0, 21, 17, 20, 19, 11, 22 }, + [3] = { 1, 7, 8, 12, 10, 18, 4, 13, 5, 6, 3, + 2, 9, 0, 0, 0, 21, 17, 20, 19, 11, 22 }, + [4] = { 4, 12, 10, 7, 8, 18, 1, 13, 2, 6, 3, + 5, 9, 0, 0, 0, 21, 17, 20, 19, 11, 22 }, + [5] = { 13, 2, 7, 9, 12, 19, 5, 1, 6, 3, 4, + 8, 10, 0, 0, 0, 21, 22, 18, 17, 11, 20 }, + [6] = { 3, 10, 7, 13, 9, 11, 1, 2, 4, 6, 8, + 5, 12, 0, 0, 0, 20, 1, 0, 21, 22, 17 }, + [7] = { 3, 2, 4, 7, 9, 1, 17, 12, 18, 14, 13, + 8, 15, 6, 10, 5, 19, 22, 16, 21, 20, 11 }, +}; + +/* + * This routine chooses one of several remapping tables for 22 lines. + * It is unclear which lines are being remapped. It seems to pick + * table cfg7 for the Nezha board. + */ +static void mctl_phy_ac_remapping(const dram_para_t *para, + const dram_config_t *config) +{ + const uint8_t *cfg; + uint32_t fuse, val; + + /* + * It is unclear whether the LPDDRx types don't need any remapping, + * or whether the original code just didn't provide tables. + */ + if (para->dram_type != SUNXI_DRAM_TYPE_DDR2 && + para->dram_type != SUNXI_DRAM_TYPE_DDR3) + return; + + fuse = (readl(SUNXI_SID_BASE + 0x28) & 0xf00) >> 8; + debug("DDR efuse: 0x%x\n", fuse); + + if (para->dram_type == SUNXI_DRAM_TYPE_DDR2) { + if (fuse == 15) + return; + cfg = ac_remapping_tables[6]; + } else { + if (config->dram_tpr13 & 0xc0000) { + cfg = ac_remapping_tables[7]; + } else { + switch (fuse) { + case 8: cfg = ac_remapping_tables[2]; break; + case 9: cfg = ac_remapping_tables[3]; break; + case 10: cfg = ac_remapping_tables[5]; break; + case 11: cfg = ac_remapping_tables[4]; break; + default: + case 12: cfg = ac_remapping_tables[1]; break; + case 13: + case 14: cfg = ac_remapping_tables[0]; break; + } + } + } + + val = (cfg[4] << 25) | (cfg[3] << 20) | (cfg[2] << 15) | + (cfg[1] << 10) | (cfg[0] << 5); + writel(val, 0x3102500); + + val = (cfg[10] << 25) | (cfg[9] << 20) | (cfg[8] << 15) | + (cfg[ 7] << 10) | (cfg[6] << 5) | cfg[5]; + writel(val, 0x3102504); + + val = (cfg[15] << 20) | (cfg[14] << 15) | (cfg[13] << 10) | + (cfg[12] << 5) | cfg[11]; + writel(val, 0x3102508); + + val = (cfg[21] << 25) | (cfg[20] << 20) | (cfg[19] << 15) | + (cfg[18] << 10) | (cfg[17] << 5) | cfg[16]; + writel(val, 0x310250c); + + val = (cfg[4] << 25) | (cfg[3] << 20) | (cfg[2] << 15) | + (cfg[1] << 10) | (cfg[0] << 5) | 1; + writel(val, 0x3102500); +} + +// Init the controller channel. The key part is placing commands in the main +// command register (PIR, 0x3103000) and checking command status (PGSR0, 0x3103010). +// +static unsigned int mctl_channel_init(unsigned int ch_index, + const dram_para_t *para, + const dram_config_t *config) +{ + unsigned int val, dqs_gating_mode; + + dqs_gating_mode = (config->dram_tpr13 & 0xc) >> 2; + + // set DDR clock to half of CPU clock + clrsetbits_le32(0x310200c, 0xfff, (para->dram_clk / 2) - 1); + + // MRCTRL0 nibble 3 undocumented + clrsetbits_le32(0x3103108, 0xf00, 0x300); + + if (para->dram_odt_en) + val = 0; + else + val = BIT(5); + + // DX0GCR0 + if (para->dram_clk > 672) + clrsetbits_le32(0x3103344, 0xf63e, val); + else + clrsetbits_le32(0x3103344, 0xf03e, val); + + // DX1GCR0 + if (para->dram_clk > 672) { + setbits_le32(0x3103344, 0x400); + clrsetbits_le32(0x31033c4, 0xf63e, val); + } else { + clrsetbits_le32(0x31033c4, 0xf03e, val); + } + + // 0x3103208 undocumented + setbits_le32(0x3103208, BIT(1)); + + eye_delay_compensation(para); + + // set PLL SSCG ? + val = readl(0x3103108); + if (dqs_gating_mode == 1) { + clrsetbits_le32(0x3103108, 0xc0, 0); + clrbits_le32(0x31030bc, 0x107); + } else if (dqs_gating_mode == 2) { + clrsetbits_le32(0x3103108, 0xc0, 0x80); + + clrsetbits_le32(0x31030bc, 0x107, + (((config->dram_tpr13 >> 16) & 0x1f) - 2) | 0x100); + clrsetbits_le32(0x310311c, BIT(31), BIT(27)); + } else { + clrbits_le32(0x3103108, 0x40); + udelay(10); + setbits_le32(0x3103108, 0xc0); + } + + if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR2 || + para->dram_type == SUNXI_DRAM_TYPE_LPDDR3) { + if (dqs_gating_mode == 1) + clrsetbits_le32(0x310311c, 0x080000c0, 0x80000000); + else + clrsetbits_le32(0x310311c, 0x77000000, 0x22000000); + } + + clrsetbits_le32(0x31030c0, 0x0fffffff, + (config->dram_para2 & BIT(12)) ? 0x03000001 : 0x01000007); + + if (readl(0x70005d4) & BIT(16)) { + clrbits_le32(0x7010250, 0x2); + udelay(10); + } + + // Set ZQ config + clrsetbits_le32(0x3103140, 0x3ffffff, + (para->dram_zq & 0x00ffffff) | BIT(25)); + + // Initialise DRAM controller + if (dqs_gating_mode == 1) { + //writel(0x52, 0x3103000); // prep PHY reset + PLL init + z-cal + writel(0x53, 0x3103000); // Go + + while ((readl(0x3103010) & 0x1) == 0) { + } // wait for IDONE + udelay(10); + + // 0x520 = prep DQS gating + DRAM init + d-cal + if (para->dram_type == SUNXI_DRAM_TYPE_DDR3) + writel(0x5a0, 0x3103000); // + DRAM reset + else + writel(0x520, 0x3103000); + } else { + if ((readl(0x70005d4) & (1 << 16)) == 0) { + // prep DRAM init + PHY reset + d-cal + PLL init + z-cal + if (para->dram_type == SUNXI_DRAM_TYPE_DDR3) + writel(0x1f2, 0x3103000); // + DRAM reset + else + writel(0x172, 0x3103000); + } else { + // prep PHY reset + d-cal + z-cal + writel(0x62, 0x3103000); + } + } + + setbits_le32(0x3103000, 0x1); // GO + + udelay(10); + while ((readl(0x3103010) & 0x1) == 0) { + } // wait for IDONE + + if (readl(0x70005d4) & BIT(16)) { + clrsetbits_le32(0x310310c, 0x06000000, 0x04000000); + udelay(10); + + setbits_le32(0x3103004, 0x1); + + while ((readl(0x3103018) & 0x7) != 0x3) { + } + + clrbits_le32(0x7010250, 0x1); + udelay(10); + + clrbits_le32(0x3103004, 0x1); + + while ((readl(0x3103018) & 0x7) != 0x1) { + } + + udelay(15); + + if (dqs_gating_mode == 1) { + clrbits_le32(0x3103108, 0xc0); + clrsetbits_le32(0x310310c, 0x06000000, 0x02000000); + udelay(1); + writel(0x401, 0x3103000); + + while ((readl(0x3103010) & 0x1) == 0) { + } + } + } + + // Check for training error + if (readl(0x3103010) & BIT(20)) { + printf("ZQ calibration error, check external 240 ohm resistor\n"); + return 0; + } + + // STATR = Zynq STAT? Wait for status 'normal'? + while ((readl(0x3103018) & 0x1) == 0) { + } + + setbits_le32(0x310308c, BIT(31)); + udelay(10); + clrbits_le32(0x310308c, BIT(31)); + udelay(10); + setbits_le32(0x3102014, BIT(31)); + udelay(10); + + clrbits_le32(0x310310c, 0x06000000); + + if (dqs_gating_mode == 1) + clrsetbits_le32(0x310311c, 0xc0, 0x40); + + return 1; +} + +static unsigned int calculate_rank_size(uint32_t regval) +{ + unsigned int bits; + + bits = (regval >> 8) & 0xf; /* page size - 3 */ + bits += (regval >> 4) & 0xf; /* row width - 1 */ + bits += (regval >> 2) & 0x3; /* bank count - 2 */ + bits -= 14; /* 1MB = 20 bits, minus above 6 = 14 */ + + return 1U << bits; +} + +/* + * The below routine reads the dram config registers and extracts + * the number of address bits in each rank available. It then calculates + * total memory size in MB. + */ +static unsigned int DRAMC_get_dram_size(void) +{ + uint32_t val; + unsigned int size; + + val = readl(0x3102000); /* MC_WORK_MODE0 */ + size = calculate_rank_size(val); + if ((val & 0x3) == 0) /* single rank? */ + return size; + + val = readl(0x3102004); /* MC_WORK_MODE1 */ + if ((val & 0x3) == 0) /* two identical ranks? */ + return size * 2; + + /* add sizes of both ranks */ + return size + calculate_rank_size(val); +} + +/* + * The below routine reads the command status register to extract + * DQ width and rank count. This follows the DQS training command in + * channel_init. If error bit 22 is reset, we have two ranks and full DQ. + * If there was an error, figure out whether it was half DQ, single rank, + * or both. Set bit 12 and 0 in dram_para2 with the results. + */ +static int dqs_gate_detect(dram_config_t *config) +{ + uint32_t dx0, dx1; + + if ((readl(0x3103010) & BIT(22)) == 0) { + config->dram_para2 = (config->dram_para2 & ~0xf) | BIT(12); + debug("dual rank and full DQ\n"); + + return 1; + } + + dx0 = (readl(0x3103348) & 0x3000000) >> 24; + if (dx0 == 0) { + config->dram_para2 = (config->dram_para2 & ~0xf) | 0x1001; + debug("dual rank and half DQ\n"); + + return 1; + } + + if (dx0 == 2) { + dx1 = (readl(0x31033c8) & 0x3000000) >> 24; + if (dx1 == 2) { + config->dram_para2 = config->dram_para2 & ~0xf00f; + debug("single rank and full DQ\n"); + } else { + config->dram_para2 = (config->dram_para2 & ~0xf00f) | BIT(0); + debug("single rank and half DQ\n"); + } + + return 1; + } + + if ((config->dram_tpr13 & BIT(29)) == 0) + return 0; + + debug("DX0 state: %d\n", dx0); + debug("DX1 state: %d\n", dx1); + + return 0; +} + +static int dramc_simple_wr_test(unsigned int mem_mb, int len) +{ + unsigned int offs = (mem_mb / 2) << 18; // half of memory size + unsigned int patt1 = 0x01234567; + unsigned int patt2 = 0xfedcba98; + unsigned int *addr, v1, v2, i; + + addr = (unsigned int *)CFG_SYS_SDRAM_BASE; + for (i = 0; i != len; i++, addr++) { + writel(patt1 + i, (unsigned long)addr); + writel(patt2 + i, (unsigned long)(addr + offs)); + } + + addr = (unsigned int *)CFG_SYS_SDRAM_BASE; + for (i = 0; i != len; i++) { + v1 = readl((unsigned long)(addr + i)); + v2 = patt1 + i; + if (v1 != v2) { + printf("DRAM: simple test FAIL\n"); + printf("%x != %x at address %p\n", v1, v2, addr + i); + return 1; + } + v1 = readl((unsigned long)(addr + offs + i)); + v2 = patt2 + i; + if (v1 != v2) { + printf("DRAM: simple test FAIL\n"); + printf("%x != %x at address %p\n", v1, v2, addr + offs + i); + return 1; + } + } + + debug("DRAM: simple test OK\n"); + return 0; +} + +// Set the Vref mode for the controller +// +static void mctl_vrefzq_init(const dram_para_t *para, const dram_config_t *config) +{ + if (config->dram_tpr13 & BIT(17)) + return; + + clrsetbits_le32(0x3103110, 0x7f7f7f7f, para->dram_tpr5); + + // IOCVR1 + if ((config->dram_tpr13 & BIT(16)) == 0) + clrsetbits_le32(0x3103114, 0x7f, para->dram_tpr6 & 0x7f); +} + +// Perform an init of the controller. This is actually done 3 times. The first +// time to establish the number of ranks and DQ width. The second time to +// establish the actual ram size. The third time is final one, with the final +// settings. +// +static int mctl_core_init(const dram_para_t *para, const dram_config_t *config) +{ + mctl_sys_init(para, config); + + mctl_vrefzq_init(para, config); + + mctl_com_init(para, config); + + mctl_phy_ac_remapping(para, config); + + mctl_set_timing_params(para, config); + + return mctl_channel_init(0, para, config); +} + +/* + * This routine sizes a DRAM device by cycling through address lines and + * figuring out if they are connected to a real address line, or if the + * address is a mirror. + * First the column and bank bit allocations are set to low values (2 and 9 + * address lines). Then a maximum allocation (16 lines) is set for rows and + * this is tested. + * Next the BA2 line is checked. This seems to be placed above the column, + * BA0-1 and row addresses. Finally, the column address is allocated 13 lines + * and these are tested. The results are placed in dram_para1 and dram_para2. + */ +static int auto_scan_dram_size(const dram_para_t *para, dram_config_t *config) +{ + unsigned int rval, i, j, rank, maxrank, offs; + unsigned int shft; + unsigned long ptr, mc_work_mode, chk; + + if (mctl_core_init(para, config) == 0) { + printf("DRAM initialisation error : 0\n"); + return 0; + } + + maxrank = (config->dram_para2 & 0xf000) ? 2 : 1; + mc_work_mode = 0x3102000; + offs = 0; + + /* write test pattern */ + for (i = 0, ptr = CFG_SYS_SDRAM_BASE; i < 64; i++, ptr += 4) + writel((i & 0x1) ? ptr : ~ptr, ptr); + + for (rank = 0; rank < maxrank;) { + /* set row mode */ + clrsetbits_le32(mc_work_mode, 0xf0c, 0x6f0); + udelay(1); + + // Scan per address line, until address wraps (i.e. see shadow) + for (i = 11; i < 17; i++) { + chk = CFG_SYS_SDRAM_BASE + (1U << (i + 11)); + ptr = CFG_SYS_SDRAM_BASE; + for (j = 0; j < 64; j++) { + if (readl(chk) != ((j & 1) ? ptr : ~ptr)) + break; + ptr += 4; + chk += 4; + } + if (j == 64) + break; + } + if (i > 16) + i = 16; + debug("rank %d row = %d\n", rank, i); + + /* Store rows in para 1 */ + shft = offs + 4; + rval = config->dram_para1; + rval &= ~(0xff << shft); + rval |= i << shft; + config->dram_para1 = rval; + + if (rank == 1) /* Set bank mode for rank0 */ + clrsetbits_le32(0x3102000, 0xffc, 0x6a4); + + /* Set bank mode for current rank */ + clrsetbits_le32(mc_work_mode, 0xffc, 0x6a4); + udelay(1); + + // Test if bit A23 is BA2 or mirror XXX A22? + chk = CFG_SYS_SDRAM_BASE + (1U << 22); + ptr = CFG_SYS_SDRAM_BASE; + for (i = 0, j = 0; i < 64; i++) { + if (readl(chk) != ((i & 1) ? ptr : ~ptr)) { + j = 1; + break; + } + ptr += 4; + chk += 4; + } + + debug("rank %d bank = %d\n", rank, (j + 1) << 2); /* 4 or 8 */ + + /* Store banks in para 1 */ + shft = 12 + offs; + rval = config->dram_para1; + rval &= ~(0xf << shft); + rval |= j << shft; + config->dram_para1 = rval; + + if (rank == 1) /* Set page mode for rank0 */ + clrsetbits_le32(0x3102000, 0xffc, 0xaa0); + + /* Set page mode for current rank */ + clrsetbits_le32(mc_work_mode, 0xffc, 0xaa0); + udelay(1); + + // Scan per address line, until address wraps (i.e. see shadow) + for (i = 9; i < 14; i++) { + chk = CFG_SYS_SDRAM_BASE + (1U << i); + ptr = CFG_SYS_SDRAM_BASE; + for (j = 0; j < 64; j++) { + if (readl(chk) != ((j & 1) ? ptr : ~ptr)) + break; + ptr += 4; + chk += 4; + } + if (j == 64) + break; + } + if (i > 13) + i = 13; + + unsigned int pgsize = (i == 9) ? 0 : (1 << (i - 10)); + debug("rank %d page size = %d KB\n", rank, pgsize); + + /* Store page size */ + shft = offs; + rval = config->dram_para1; + rval &= ~(0xf << shft); + rval |= pgsize << shft; + config->dram_para1 = rval; + + // Move to next rank + rank++; + if (rank != maxrank) { + if (rank == 1) { + /* MC_WORK_MODE */ + clrsetbits_le32(0x3202000, 0xffc, 0x6f0); + + /* MC_WORK_MODE2 */ + clrsetbits_le32(0x3202004, 0xffc, 0x6f0); + } + /* store rank1 config in upper half of para1 */ + offs += 16; + mc_work_mode += 4; /* move to MC_WORK_MODE2 */ + } + } + if (maxrank == 2) { + config->dram_para2 &= 0xfffff0ff; + /* note: rval is equal to para->dram_para1 here */ + if ((rval & 0xffff) == (rval >> 16)) { + debug("rank1 config same as rank0\n"); + } else { + config->dram_para2 |= BIT(8); + debug("rank1 config different from rank0\n"); + } + } + + return 1; +} + +/* + * This routine sets up parameters with dqs_gating_mode equal to 1 and two + * ranks enabled. It then configures the core and tests for 1 or 2 ranks and + * full or half DQ width. It then resets the parameters to the original values. + * dram_para2 is updated with the rank and width findings. + */ +static int auto_scan_dram_rank_width(const dram_para_t *para, + dram_config_t *config) +{ + unsigned int s1 = config->dram_tpr13; + unsigned int s2 = config->dram_para1; + + config->dram_para1 = 0x00b000b0; + config->dram_para2 = (config->dram_para2 & ~0xf) | BIT(12); + + /* set DQS probe mode */ + config->dram_tpr13 = (config->dram_tpr13 & ~0x8) | BIT(2) | BIT(0); + + mctl_core_init(para, config); + + if (readl(0x3103010) & BIT(20)) + return 0; + + if (dqs_gate_detect(config) == 0) + return 0; + + config->dram_tpr13 = s1; + config->dram_para1 = s2; + + return 1; +} + +/* + * This routine determines the SDRAM topology. It first establishes the number + * of ranks and the DQ width. Then it scans the SDRAM address lines to establish + * the size of each rank. It then updates dram_tpr13 to reflect that the sizes + * are now known: a re-init will not repeat the autoscan. + */ +static int auto_scan_dram_config(const dram_para_t *para, + dram_config_t *config) +{ + if (((config->dram_tpr13 & BIT(14)) == 0) && + (auto_scan_dram_rank_width(para, config) == 0)) { + printf("ERROR: auto scan dram rank & width failed\n"); + return 0; + } + + if (((config->dram_tpr13 & BIT(0)) == 0) && + (auto_scan_dram_size(para, config) == 0)) { + printf("ERROR: auto scan dram size failed\n"); + return 0; + } + + if ((config->dram_tpr13 & BIT(15)) == 0) + config->dram_tpr13 |= BIT(14) | BIT(13) | BIT(1) | BIT(0); + + return 1; +} + +static int init_DRAM(int type, const dram_para_t *para) +{ + dram_config_t config = { + .dram_para1 = 0x000010d2, + .dram_para2 = 0, + .dram_tpr13 = CONFIG_DRAM_SUNXI_TPR13, + }; + u32 rc, mem_size_mb; + + debug("DRAM BOOT DRIVE INFO: %s\n", "V0.24"); + debug("DRAM CLK = %d MHz\n", para->dram_clk); + debug("DRAM Type = %d (2:DDR2,3:DDR3)\n", para->dram_type); + if ((para->dram_odt_en & 0x1) == 0) + debug("DRAMC read ODT off\n"); + else + debug("DRAMC ZQ value: 0x%x\n", para->dram_zq); + + /* Test ZQ status */ + if (config.dram_tpr13 & BIT(16)) { + debug("DRAM only have internal ZQ\n"); + setbits_le32(0x3000160, BIT(8)); + writel(0, 0x3000168); + udelay(10); + } else { + clrbits_le32(0x3000160, 0x3); + writel(config.dram_tpr13 & BIT(16), 0x7010254); + udelay(10); + clrsetbits_le32(0x3000160, 0x108, BIT(1)); + udelay(10); + setbits_le32(0x3000160, BIT(0)); + udelay(20); + debug("ZQ value = 0x%x\n", readl(0x300016c)); + } + + dram_voltage_set(para); + + /* Set SDRAM controller auto config */ + if ((config.dram_tpr13 & BIT(0)) == 0) { + if (auto_scan_dram_config(para, &config) == 0) { + printf("auto_scan_dram_config() FAILED\n"); + return 0; + } + } + + /* report ODT */ + rc = para->dram_mr1; + if ((rc & 0x44) == 0) + debug("DRAM ODT off\n"); + else + debug("DRAM ODT value: 0x%x\n", rc); + + /* Init core, final run */ + if (mctl_core_init(para, &config) == 0) { + printf("DRAM initialisation error: 1\n"); + return 0; + } + + /* Get SDRAM size */ + /* TODO: who ever puts a negative number in the top half? */ + rc = config.dram_para2; + if (rc & BIT(31)) { + rc = (rc >> 16) & ~BIT(15); + } else { + rc = DRAMC_get_dram_size(); + debug("DRAM: size = %dMB\n", rc); + config.dram_para2 = (config.dram_para2 & 0xffffU) | rc << 16; + } + mem_size_mb = rc; + + /* Purpose ?? */ + if (config.dram_tpr13 & BIT(30)) { + rc = para->dram_tpr8; + if (rc == 0) + rc = 0x10000200; + writel(rc, 0x31030a0); + writel(0x40a, 0x310309c); + setbits_le32(0x3103004, BIT(0)); + debug("Enable Auto SR\n"); + } else { + clrbits_le32(0x31030a0, 0xffff); + clrbits_le32(0x3103004, 0x1); + } + + /* Purpose ?? */ + if (config.dram_tpr13 & BIT(9)) { + clrsetbits_le32(0x3103100, 0xf000, 0x5000); + } else { + if (para->dram_type != SUNXI_DRAM_TYPE_LPDDR2) + clrbits_le32(0x3103100, 0xf000); + } + + setbits_le32(0x3103140, BIT(31)); + + /* CHECK: is that really writing to a different register? */ + if (config.dram_tpr13 & BIT(8)) + writel(readl(0x3103140) | 0x300, 0x31030b8); + + if (config.dram_tpr13 & BIT(16)) + clrbits_le32(0x3103108, BIT(13)); + else + setbits_le32(0x3103108, BIT(13)); + + /* Purpose ?? */ + if (para->dram_type == SUNXI_DRAM_TYPE_LPDDR3) + clrsetbits_le32(0x310307c, 0xf0000, 0x1000); + + dram_enable_all_master(); + if (config.dram_tpr13 & BIT(28)) { + if ((readl(0x70005d4) & BIT(16)) || + dramc_simple_wr_test(mem_size_mb, 4096)) + return 0; + } + + return mem_size_mb; +} + + static const dram_para_t para = { + .dram_clk = CONFIG_DRAM_CLK, + .dram_type = CONFIG_SUNXI_DRAM_TYPE, + .dram_zq = CONFIG_DRAM_ZQ, + .dram_odt_en = CONFIG_DRAM_SUNXI_ODT_EN, + .dram_mr0 = 0x1c70, + .dram_mr1 = 0x42, + .dram_mr2 = 0x18, + .dram_mr3 = 0, + .dram_tpr0 = 0x004a2195, + .dram_tpr1 = 0x02423190, + .dram_tpr2 = 0x0008b061, + .dram_tpr3 = 0xb4787896, // unused + .dram_tpr4 = 0, + .dram_tpr5 = 0x48484848, + .dram_tpr6 = 0x00000048, + .dram_tpr7 = 0x1620121e, // unused + .dram_tpr8 = 0, + .dram_tpr9 = 0, // clock? + .dram_tpr10 = 0, + .dram_tpr11 = CONFIG_DRAM_SUNXI_TPR11, + .dram_tpr12 = CONFIG_DRAM_SUNXI_TPR12, + }; + +unsigned long sunxi_dram_init(void) +{ + return init_DRAM(0, &para) * 1024UL * 1024; +}; + +#ifdef CONFIG_RAM /* using the driver model */ +struct sunxi_ram_priv { + size_t size; +}; + +static int sunxi_ram_probe(struct udevice *dev) +{ + struct sunxi_ram_priv *priv = dev_get_priv(dev); + unsigned long dram_size; + + debug("%s: %s: probing\n", __func__, dev->name); + + dram_size = sunxi_dram_init(); + if (!dram_size) { + printf("DRAM init failed: %d\n", ret); + return -ENODEV; + } + + priv->size = dram_size; + + return 0; +} + +static int sunxi_ram_get_info(struct udevice *dev, struct ram_info *info) +{ + struct sunxi_ram_priv *priv = dev_get_priv(dev); + + debug("%s: %s: getting info\n", __func__, dev->name); + + info->base = CFG_SYS_SDRAM_BASE; + info->size = priv->size; + + return 0; +} + +static struct ram_ops sunxi_ram_ops = { + .get_info = sunxi_ram_get_info, +}; + +static const struct udevice_id sunxi_ram_ids[] = { + { .compatible = "allwinner,sun20i-d1-mbus" }, + { } +}; + +U_BOOT_DRIVER(sunxi_ram) = { + .name = "sunxi_ram", + .id = UCLASS_RAM, + .of_match = sunxi_ram_ids, + .ops = &sunxi_ram_ops, + .probe = sunxi_ram_probe, + .priv_auto = sizeof(struct sunxi_ram_priv), +}; +#endif /* CONFIG_RAM (using driver model) */ diff --git a/drivers/ram/sunxi/dram_sun20i_d1.h b/drivers/ram/sunxi/dram_sun20i_d1.h new file mode 100644 index 00000000000..91383f6cf10 --- /dev/null +++ b/drivers/ram/sunxi/dram_sun20i_d1.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * D1/R528/T113 DRAM controller register and constant defines + * + * (C) Copyright 2022 Arm Ltd. + * Based on H6 and H616 header, which are: + * (C) Copyright 2017 Icenowy Zheng icenowy@aosc.io + * (C) Copyright 2020 Jernej Skrabec jernej.skrabec@siol.net + * + */ + +#ifndef _SUNXI_DRAM_SUN20I_D1_H +#define _SUNXI_DRAM_SUN20I_D1_H + +enum sunxi_dram_type { + SUNXI_DRAM_TYPE_DDR2 = 2, + SUNXI_DRAM_TYPE_DDR3 = 3, + SUNXI_DRAM_TYPE_LPDDR2 = 6, + SUNXI_DRAM_TYPE_LPDDR3 = 7, +}; + +/* + * This structure contains a mixture of fixed configuration settings, + * variables that are used at runtime to communicate settings between + * different stages and functions, and unused values. + * This is copied from Allwinner's boot0 data structure, which can be + * found at offset 0x38 in any boot0 binary. To allow matching up some + * board specific settings, this struct is kept compatible, even though + * we don't need all members in our code. + */ +typedef struct dram_para { + /* normal configuration */ + const u32 dram_clk; + const u32 dram_type; + const u32 dram_zq; + const u32 dram_odt_en; + + /* timing configuration */ + const u32 dram_mr0; + const u32 dram_mr1; + const u32 dram_mr2; + const u32 dram_mr3; + const u32 dram_tpr0; //DRAMTMG0 + const u32 dram_tpr1; //DRAMTMG1 + const u32 dram_tpr2; //DRAMTMG2 + const u32 dram_tpr3; //DRAMTMG3 + const u32 dram_tpr4; //DRAMTMG4 + const u32 dram_tpr5; //DRAMTMG5 + const u32 dram_tpr6; //DRAMTMG8 + const u32 dram_tpr7; + const u32 dram_tpr8; + const u32 dram_tpr9; + const u32 dram_tpr10; + const u32 dram_tpr11; + const u32 dram_tpr12; +} dram_para_t; + +typedef struct dram_config { + /* control configuration */ + u32 dram_para1; + u32 dram_para2; + /* contains a bitfield of DRAM setup settings */ + u32 dram_tpr13; +} dram_config_t; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +#endif /* _SUNXI_DRAM_SUN20I_D1_H */

This adds the remaining code bits to teach U-Boot about Allwinner's newest SoC generation. This was introduced with the RISC-V based Allwinner D1 SoC, which actually shares a die with the ARM cores versions called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols for the new SoC generation and pincontroller. It also adds the new symbols to the relavent code places, to set all the hardcoded bits directly.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 9 +++++++-- arch/arm/mach-sunxi/Kconfig | 11 +++++++++++ arch/arm/mach-sunxi/board.c | 8 ++++++++ arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 ++ arch/arm/mach-sunxi/cpu_info.c | 2 ++ common/spl/Kconfig | 1 + drivers/clk/sunxi/Kconfig | 1 + drivers/mmc/sunxi_mmc.c | 1 + drivers/pinctrl/sunxi/Kconfig | 1 + 9 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 8471e11aa02..a84a57e5b41 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -266,7 +266,7 @@ struct sunxi_ccm_reg { #define CCM_CPU_AXI_AXI_MASK 0x3 #define CCM_CPU_AXI_DEFAULT_FACTORS 0x301

-#ifdef CONFIG_MACH_SUN50I_H6 +#ifdef CONFIG_MACH_SUN50I_H6 /* H6 */ #define CCM_PLL6_DEFAULT 0xa0006300

/* psi_ahb1_ahb2 bit field */ @@ -277,7 +277,7 @@ struct sunxi_ccm_reg {

/* apb1 bit field */ #define CCM_APB1_DEFAULT 0x03000102 -#elif CONFIG_MACH_SUN50I_H616 +#elif CONFIG_MACH_SUN50I_H616 /* H616 */ #define CCM_PLL6_DEFAULT 0xa8003100

/* psi_ahb1_ahb2 bit field */ @@ -288,6 +288,11 @@ struct sunxi_ccm_reg {

/* apb1 bit field */ #define CCM_APB1_DEFAULT 0x03000102 +#elif CONFIG_MACH_SUN8I_R528 /* R528 */ +#define CCM_PLL6_DEFAULT 0xe8216300 +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 +//#define CCM_AHB3_DEFAULT 0x03000002 +#define CCM_APB1_DEFAULT 0x03000102 #endif

/* apb2 bit field */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index aa8834e2662..16b5a15477f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -352,6 +352,15 @@ config MACH_SUN8I_R40 select SUNXI_DRAM_DW_32BIT imply SPL_SYS_I2C_LEGACY

+config MACH_SUN8I_R528 + bool "sun8i (Allwinner R528)" + select CPU_V7A + select SUNXI_GEN_NCAT2 + select SUNXI_NEW_PINCTRL + select MMC_SUNXI_HAS_NEW_MODE + select SUPPORT_SPL + select DRAM_SUN8I_R528 + config MACH_SUN8I_V3S bool "sun8i (Allwinner V3/V3s/S3/S3L)" select CPU_V7A @@ -662,6 +671,7 @@ config SYS_CLK_FREQ default 1008000000 if MACH_SUN9I default 888000000 if MACH_SUN50I_H6 default 1008000000 if MACH_SUN50I_H616 + default 1008000000 if MACH_SUN8I_R528

config SYS_CONFIG_NAME default "suniv" if MACH_SUNIV @@ -670,6 +680,7 @@ config SYS_CONFIG_NAME default "sun6i" if MACH_SUN6I default "sun7i" if MACH_SUN7I default "sun8i" if MACH_SUN8I + default "sun8i" if MACH_SUN8I_R528 default "sun9i" if MACH_SUN9I default "sun50i" if MACH_SUN50I default "sun50i" if MACH_SUN50I_H6 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 51b8e708b00..8980ffb5097 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) + sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); + sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); + sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); @@ -163,6 +167,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); + sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index c3a4623d345..bf21a715420 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -52,7 +52,9 @@ void clock_init_safe(void) CCM_CPU_AXI_DEFAULT_FACTORS);

writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); +#ifdef CCM_AHB3_DEFAULT writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); +#endif writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);

/* diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 7eef178859b..7fecc3b88dd 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -93,6 +93,8 @@ int print_cpuinfo(void) printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_V3S printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_R528 + puts("CPU: Allwinner R528 (SUN8I)\n"); #elif defined CONFIG_MACH_SUN9I puts("CPU: Allwinner A80 (SUN9I)\n"); #elif defined CONFIG_MACH_SUN50I diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 9a0c16f9988..a9d4d2f7cd8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -357,6 +357,7 @@ config SPL_STACK default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x118000 if MACH_SUN50I_H6 default 0x58000 if MACH_SUN50I_H616 + default 0x40000 if MACH_SUN8I_R528 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I default 0x8000 if ARCH_SUNXI diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index f65e482ba4c..8bdc0944896 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -89,6 +89,7 @@ config CLK_SUN8I_H3

config CLK_SUN20I_D1 bool "Clock driver for Allwinner D1" + default MACH_SUN8I_R528 help This enables common clock driver support for platforms based on Allwinner D1 SoC. diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index a8e590561ce..0837e8bb307 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -708,6 +708,7 @@ static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun50i-h6-emmc" }, { .compatible = "allwinner,sun50i-a100-mmc" }, { .compatible = "allwinner,sun50i-a100-emmc" }, + { .compatible = "allwinner,sun20i-d1-mmc" }, { /* sentinel */ } };

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index c8f937d91e9..cbd61795986 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -126,6 +126,7 @@ config PINCTRL_SUN50I_H616_R

config PINCTRL_SUN20I_D1 bool "Support for the Allwinner D1/R528 PIO" + default MACH_SUN8I_R528 select PINCTRL_SUNXI

endif

At the moment we have each SoC's memory map defined in its own cpu.h, which is included in include/configs/sunxi_common.h. This will be a problem with the introduction of Allwinner RISC-V support.

Remove the inclusion of that header file from the common config header, instead move the required serial base addresses (for the SPL) into a separate header file. Then include the original cpu.h file only where we really need it, which is only under arch/arm now.

This disentangles the architecture specific header files from the generic code.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/cpu/armv7/sunxi/sram.c | 1 + arch/arm/cpu/armv8/fel_utils.S | 1 + arch/arm/include/asm/arch-sunxi/boot0.h | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 --------- .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 5 --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 7 ---- .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 4 --- arch/arm/include/asm/arch-sunxi/serial.h | 32 +++++++++++++++++++ arch/arm/mach-sunxi/gtbus_sun9i.c | 1 + arch/arm/mach-sunxi/timer.c | 1 + include/configs/sunxi-common.h | 2 +- 12 files changed, 40 insertions(+), 32 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/serial.h

diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c index 28564c2846a..28ff6a1b7c2 100644 --- a/arch/arm/cpu/armv7/sunxi/sram.c +++ b/arch/arm/cpu/armv7/sunxi/sram.c @@ -12,6 +12,7 @@ #include <common.h> #include <init.h> #include <asm/io.h> +#include <asm/arch/cpu.h>

void sunxi_sram_init(void) { diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index 2fe38a1a047..939869b9ffa 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -10,6 +10,7 @@ #include <config.h> #include <asm/system.h> #include <linux/linkage.h> +#include <asm/arch/cpu.h>

/* * We don't overwrite save_boot_params() here, to save the FEL state upon diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 30f5680757a..cad25c50bc6 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -3,6 +3,8 @@ * Configuration settings for the Allwinner A64 (sun50i) CPU */

+#include <asm/arch/cpu.h> + #if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) /* reserve space for BOOT0 header information */ b reset diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 3d34261b0e5..fcc8966cb0b 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -9,6 +9,7 @@ #define _SUNXI_CLOCK_H

#include <linux/types.h> +#include <asm/arch/cpu.h>

#define CLK_GATE_OPEN 0x1 #define CLK_GATE_CLOSE 0x0 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index d6fe51f24bc..3daee2f574a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -128,20 +128,6 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_CPUCFG_BASE 0x01c25c00 #endif

-#ifdef CONFIG_MACH_SUNIV -#define SUNXI_UART0_BASE 0x01c25000 -#define SUNXI_UART1_BASE 0x01c25400 -#define SUNXI_UART2_BASE 0x01c25800 -#else -#define SUNXI_UART0_BASE 0x01c28000 -#define SUNXI_UART1_BASE 0x01c28400 -#define SUNXI_UART2_BASE 0x01c28800 -#endif -#define SUNXI_UART3_BASE 0x01c28c00 -#define SUNXI_UART4_BASE 0x01c29000 -#define SUNXI_UART5_BASE 0x01c29400 -#define SUNXI_UART6_BASE 0x01c29800 -#define SUNXI_UART7_BASE 0x01c29c00 #define SUNXI_PS2_0_BASE 0x01c2a000 #define SUNXI_PS2_1_BASE 0x01c2a400

@@ -208,7 +194,6 @@ defined(CONFIG_MACH_SUN50I) #endif

#define SUNXI_R_TWI_BASE 0x01f02400 -#define SUNXI_R_UART_BASE 0x01f02800 #define SUN6I_P2WI_BASE 0x01f03400 #define SUNXI_RSB_BASE 0x01f03400

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 9b6bf843601..15ee092d358 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -42,10 +42,6 @@ #define SUNXI_DRAM_PHY0_BASE 0x04800000 #endif

-#define SUNXI_UART0_BASE 0x05000000 -#define SUNXI_UART1_BASE 0x05000400 -#define SUNXI_UART2_BASE 0x05000800 -#define SUNXI_UART3_BASE 0x05000C00 #define SUNXI_TWI0_BASE 0x05002000 #define SUNXI_TWI1_BASE 0x05002400 #define SUNXI_TWI2_BASE 0x05002800 @@ -67,7 +63,6 @@ #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 #define SUNXI_R_WDOG_BASE 0x07020400 -#define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400

#ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 20025be2319..2bf2675d5c1 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -86,12 +86,6 @@ #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)

/* APB1 Module */ -#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) -#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) -#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) -#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) -#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) -#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) #define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) @@ -100,7 +94,6 @@

/* RCPUS Module */ #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) -#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)

/* Misc. */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h index b13be2c4e82..961a3b37c9a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h @@ -10,10 +10,6 @@ #define SUNXI_CCM_BASE 0x02001000 #define SUNXI_TIMER_BASE 0x02050000

-#define SUNXI_UART0_BASE 0x02500000 -#define SUNXI_UART1_BASE 0x02500400 -#define SUNXI_UART2_BASE 0x02500800 -#define SUNXI_UART3_BASE 0x02500C00 #define SUNXI_TWI0_BASE 0x02502000 #define SUNXI_TWI1_BASE 0x02502400 #define SUNXI_TWI2_BASE 0x02502800 diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h new file mode 100644 index 00000000000..9386287b65e --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/serial.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardcoded UART base addresses for early SPL use + * + * Copyright (c) 2022 Arm Ltd. + */ + +#ifndef SUNXI_SERIAL_MEMMAP_H +#define SUNXI_SERIAL_MEMMAP_H + +#if defined(CONFIG_MACH_SUN9I) +#define SUNXI_UART0_BASE 0x07000000 +#define SUNXI_R_UART_BASE 0x08002800 +#elif defined(CONFIG_SUN50I_GEN_H6) +#define SUNXI_UART0_BASE 0x05000000 +#define SUNXI_R_UART_BASE 0x07080000 +#elif defined(CONFIG_MACH_SUNIV) +#define SUNXI_UART0_BASE 0x01c25000 +#define SUNXI_R_UART_BASE 0 +#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#define SUNXI_UART0_BASE 0x02500000 +#define SUNXI_R_UART_BASE 0 // 0x07080000 (?> +#else +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_R_UART_BASE 0x01f02800 +#endif + +#define SUNXI_UART1_BASE (SUNXI_UART0_BASE + 0x400) +#define SUNXI_UART2_BASE (SUNXI_UART0_BASE + 0x800) +#define SUNXI_UART3_BASE (SUNXI_UART0_BASE + 0xc00) + +#endif /* SUNXI_SERIAL_MEMMAP_H */ diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index cf011c4cfa7..5624621b500 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -8,6 +8,7 @@

#include <common.h> #include <asm/io.h> +#include <asm/arch/cpu.h> #include <asm/arch/gtbus_sun9i.h> #include <asm/arch/sys_proto.h>

diff --git a/arch/arm/mach-sunxi/timer.c b/arch/arm/mach-sunxi/timer.c index fc9d419a25e..9a6f6c06d8c 100644 --- a/arch/arm/mach-sunxi/timer.c +++ b/arch/arm/mach-sunxi/timer.c @@ -10,6 +10,7 @@ #include <time.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/arch/cpu.h> #include <asm/arch/timer.h> #include <linux/delay.h>

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d2d70f0fc23..b8ca77d031d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -12,7 +12,6 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H

-#include <asm/arch/cpu.h> #include <linux/stringify.h>

/* Serial & console */ @@ -24,6 +23,7 @@ #define CFG_SYS_NS16550_CLK 24000000 #endif #if !CONFIG_IS_ENABLED(DM_SERIAL) +#include <asm/arch/serial.h> # define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE

The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with two Arm Cortex-A7 cores. Since the D1 core .dtsi already describes all common peripherals, we just need a DT describing the ARM specific peripherals: the CPU cores, the Generic Timer, the GIC and the PMU. We include the core .dtsi directly from the riscv DT directory.

The ARM core version of the DT specifies the CPUX watchdog as "reserved", which means it won't be recognised by U-Boot. Override this in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog, so that the generic reset driver will work.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/dts/sun8i-t113s.dtsi | 59 ++++++++++++++++++++++++++++++++++ arch/arm/dts/sunxi-u-boot.dtsi | 7 ++++ 2 files changed, 66 insertions(+) create mode 100644 arch/arm/dts/sun8i-t113s.dtsi

diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi new file mode 100644 index 00000000000..ce008831307 --- /dev/null +++ b/arch/arm/dts/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <../../riscv/dts/sunxi-d1s-t113.dtsi> +#include <../../riscv/dts/sunxi-d1-t113.dtsi> + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index af419c7e590..a0c8abb7033 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -23,6 +23,13 @@ }; };

+/* Let U-Boot be the firmware layer that controls the watchdog. */ +#ifdef CONFIG_MACH_SUN8I_R528 +&wdt { + status = "okay"; +}; +#endif + &binman { u-boot-sunxi-with-spl { filename = "u-boot-sunxi-with-spl.bin";

This copies the T113s specific DTs from the Linux kernel tree (v6.4-rc1), and adds a defconfig to get the board booted.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/dts/Makefile | 2 + .../arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 +++++ arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 ++++++++++++++++++ configs/mangopi_mq_r_defconfig | 15 +++ 4 files changed, 178 insertions(+) create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts create mode 100644 arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi create mode 100644 configs/mangopi_mq_r_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 07b26df2750..5eb0e91225b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -722,6 +722,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-s3-pinecube.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-licheepi-zero.dtb +dtb-$(CONFIG_MACH_SUN8I_R528) += \ + sun8i-t113s-mangopi-mq-r-t113.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-bananapi-m2-plus.dtb \ sun50i-h5-emlid-neutis-n5-devboard.dtb \ diff --git a/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts new file mode 100644 index 00000000000..94e24b5926d --- /dev/null +++ b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#include <dt-bindings/interrupt-controller/irq.h> + +/dts-v1/; + +#include "sun8i-t113s.dtsi" +#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" + +/ { + model = "MangoPi MQ-R-T113"; + compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; + + aliases { + ethernet0 = &rtl8189ftv; + }; +}; + +&cpu0 { + cpu-supply = <&reg_vcc_core>; +}; + +&cpu1 { + cpu-supply = <&reg_vcc_core>; +}; + +&mmc1 { + rtl8189ftv: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi new file mode 100644 index 00000000000..e9bc749488b --- /dev/null +++ b/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. +/* + * Common peripherals and configurations for MangoPi MQ-R boards. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ + }; + }; + + /* board wide 5V supply directly from the USB-C socket */ + reg_vcc5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&reg_vcc5v>; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <&reg_vcc5v>; + }; + + /* XC6206 LDO on the board */ + reg_avdd2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&reg_3v3>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + vmmc-supply = <&reg_3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <&reg_3v3>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <&reg_3v3>; + vcc-pd-supply = <&reg_3v3>; + vcc-pe-supply = <&reg_avdd2v8>; + vcc-pf-supply = <&reg_3v3>; + vcc-pg-supply = <&reg_3v3>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pb_pins>; + status = "okay"; +}; + +/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <&reg_vcc5v>; + status = "okay"; +}; diff --git a/configs/mangopi_mq_r_defconfig b/configs/mangopi_mq_r_defconfig new file mode 100644 index 00000000000..66ae639326f --- /dev/null +++ b/configs/mangopi_mq_r_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mq-r-t113" +CONFIG_SPL=y +CONFIG_MACH_SUN8I_R528=y +CONFIG_DRAM_CLK=792 +CONFIG_DRAM_ZQ=8092667 +CONFIG_SUNXI_MINIMUM_DRAM_MB=128 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_DRAM_SUNXI_ODT_EN=0 +CONFIG_DRAM_SUNXI_TPR0=0x004a2195 +CONFIG_DRAM_SUNXI_TPR11=0x340000 +CONFIG_DRAM_SUNXI_TPR12=0x46 +CONFIG_DRAM_SUNXI_TPR13=0x34000100 +CONFIG_CONS_INDEX=4