For STM32 QSPI driver, "st,stm32-qspi" compatible string was first introduced in U-boot. But later in kernel side, "st,stm32f469-qspi" was used. To simplify, align U-boot QSPI compatible string with kernel one.

Signed-off-by: Patrice Chotard patrice.chotard@st.com ---

arch/arm/dts/stm32f469-disco-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 3da308e6a4..e071fd5d16 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -67,7 +67,7 @@ };

qspi: quadspi@A0001000 { - compatible = "st,stm32-qspi"; + compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;

Align doc/device-tree-bindings/spi/spi-stm32-qspi.txt with kernel v5.2-rc6

Signed-off-by: Patrice Chotard patrice.chotard@st.com

---

.../spi/spi-stm32-qspi.txt | 71 ++++++++++--------- 1 file changed, 38 insertions(+), 33 deletions(-)

diff --git a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt index cec3e1250c..adeeb63e84 100644 --- a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt +++ b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt @@ -1,39 +1,44 @@ -STM32 QSPI controller device tree bindings --------------------------------------------- +* STMicroelectronics Quad Serial Peripheral Interface(QSPI)

Required properties: -- compatible : should be "st,stm32-qspi". -- reg : 1. Physical base address and size of SPI registers map. - 2. Physical base address & size of mapped NOR Flash. -- spi-max-frequency : Max supported spi frequency. -- status : enable in requried dts. - -Connected flash properties --------------------------- -- spi-max-frequency : Max supported spi frequency. -- spi-tx-bus-width : Bus width (number of lines) for writing (1-4) -- spi-rx-bus-width : Bus width (number of lines) for reading (1-4) -- memory-map : Address and size for memory-mapping the flash +- compatible: should be "st,stm32f469-qspi" +- reg: the first contains the register location and length. + the second contains the memory mapping address and length +- reg-names: should contain the reg names "qspi" "qspi_mm" +- interrupts: should contain the interrupt for the device +- clocks: the phandle of the clock needed by the QSPI controller +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer + +Optional properties: +- resets: must contain the phandle to the reset controller. + +A spi flash (NOR/NAND) must be a child of spi node and could have some +properties. Also see jedec,spi-nor.txt. + +Required properties: +- reg: chip-Select number (QSPI controller may connect 2 flashes) +- spi-max-frequency: max frequency of spi bus + +Optional property: +- spi-rx-bus-width: see ./spi-bus.txt for the description

Example: - qspi: quadspi@A0001000 { - compatible = "st,stm32-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <92>; + +qspi: spi@a0001000 { + compatible = "st,stm32f469-qspi"; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <91>; + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - status = "okay"; - - qflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - memory-map = <0x90000000 0x1000000>; - reg = <0>; - }; + ... }; +};