[U-Boot] [PATCH v1 1/2] net: Add support for mv88e609x switches
The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports.
The main difference is the number of ports. Which affects the PORT_COUNT define and the size of the mask passed to mv88e61xx_port_set_vlan().
Other than that it's just a matter of adding the appropriate chip IDs.
Signed-off-by: Chris Packham judge.packham@gmail.com Cc: Joshua Scott joshua.scott@alliedtelesis.co.nz --- This is a re-work of Joshua's patch http://patchwork.ozlabs.org/patch/425556/
Thanks to the work from Kevin Smith the changes to support the 88E609x are quite trivial. I've tested this on a board with a 88E6097. It should also work for a 88E6096 based on the datasheet.
drivers/net/phy/mv88e61xx.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 74d5609..7385848 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -40,7 +40,7 @@
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
-#define PORT_COUNT 7 +#define PORT_COUNT 11 #define PORT_MASK ((1 << PORT_COUNT) - 1)
/* Device addresses */ @@ -167,6 +167,8 @@ #endif
/* ID register values for different switch models */ +#define PORT_SWITCH_ID_6096 0x0980 +#define PORT_SWITCH_ID_6097 0x0990 #define PORT_SWITCH_ID_6172 0x1720 #define PORT_SWITCH_ID_6176 0x1760 #define PORT_SWITCH_ID_6240 0x2400 @@ -580,7 +582,7 @@ static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) }
static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, - u8 mask) + u16 mask) { int val;
@@ -974,9 +976,21 @@ static struct phy_driver mv88e61xx_driver = { .shutdown = &genphy_shutdown, };
+static struct phy_driver mv88e609x_driver = { + .name = "Marvell MV88E609x", + .uid = 0x1410c89, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + int phy_mv88e61xx_init(void) { phy_register(&mv88e61xx_driver); + phy_register(&mv88e609x_driver);
return 0; }
On some boards these switches are wired directly into a SERDES interface on another Ethernet MAC. Add the ability to specify these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines a bit mask of these fixed ports.
Signed-off-by: Chris Packham judge.packham@gmail.com ---
drivers/net/phy/mv88e61xx.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 7385848..a2fd168 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -103,8 +103,16 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) +#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) +#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) +#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6) #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) +#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3) +#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2) +#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1) +#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
#define PORT_REG_CTRL_PSTATE_SHIFT 0 #define PORT_REG_CTRL_PSTATE_WIDTH 2 @@ -166,6 +174,14 @@ #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to #endif
+/* + * These are ports without PHYs that may be wired directly + * to other serdes interfaces + */ +#ifndef CONFIG_MV88E61XX_FIXED_PORTS +#define CONFIG_MV88E61XX_FIXED_PORTS 0 +#endif + /* ID register values for different switch models */ #define PORT_SWITCH_ID_6096 0x0980 #define PORT_SWITCH_ID_6097 0x0990 @@ -793,6 +809,27 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) return 0; }
+static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + + val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | + PORT_REG_PHYS_CTRL_FC_VALUE); + val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | + PORT_REG_PHYS_CTRL_PCS_AN_RST | + PORT_REG_PHYS_CTRL_FC_FORCE | + PORT_REG_PHYS_CTRL_DUPLEX_VALUE | + PORT_REG_PHYS_CTRL_DUPLEX_FORCE | + PORT_REG_PHYS_CTRL_SPD1000; + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +} + static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { int val; @@ -911,6 +948,12 @@ static int mv88e61xx_phy_config(struct phy_device *phydev)
/* Return success if any PHY succeeds */ ret = 0; + } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) { + res = mv88e61xx_fixed_port_setup(phydev, i); + if (res < 0) { + printf("Error configuring port %i\n", i); + continue; + } } }
On Fri, Aug 26, 2016 at 12:30 AM, Chris Packham judge.packham@gmail.com wrote:
On some boards these switches are wired directly into a SERDES interface on another Ethernet MAC. Add the ability to specify these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines a bit mask of these fixed ports.
Signed-off-by: Chris Packham judge.packham@gmail.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
On Fri, Aug 26, 2016 at 12:30 AM, Chris Packham judge.packham@gmail.com wrote:
The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports.
The main difference is the number of ports. Which affects the PORT_COUNT define and the size of the mask passed to mv88e61xx_port_set_vlan().
Other than that it's just a matter of adding the appropriate chip IDs.
Signed-off-by: Chris Packham judge.packham@gmail.com Cc: Joshua Scott joshua.scott@alliedtelesis.co.nz
Acked-by: Joe Hershberger joe.hershberger@ni.com
participants (3)
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Chris Packham -
Joe Hershberger -
Joe Hershberger