Add initial support for AM654 based EVM running on A53. Enable 4GB of DDR available on the EVM so that kernel DTB file can be updated accordingly.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com [Andreas: Added 4GB ddr support] Signed-off-by: Andreas Dannenberg dannenberg@ti.com --- arch/arm/mach-k3/Kconfig | 1 + board/ti/am65x/Kconfig | 30 ++++++++++++++++++++ board/ti/am65x/MAINTAINERS | 5 ++++ board/ti/am65x/Makefile | 8 ++++++ board/ti/am65x/evm.c | 56 +++++++++++++++++++++++++++++++++++++ include/configs/am65x_evm.h | 36 ++++++++++++++++++++++++ 6 files changed, 136 insertions(+) create mode 100644 board/ti/am65x/Kconfig create mode 100644 board/ti/am65x/MAINTAINERS create mode 100644 board/ti/am65x/Makefile create mode 100644 board/ti/am65x/evm.c create mode 100644 include/configs/am65x_evm.h

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 117e5b4e4a..df3ba32df6 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -47,4 +47,5 @@ config BOOT_PARAM_TABLE_INDEX Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media.

+source "board/ti/am65x/Kconfig" endif diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig new file mode 100644 index 0000000000..fb616e8fd5 --- /dev/null +++ b/board/ti/am65x/Kconfig @@ -0,0 +1,30 @@ +# +# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Lokesh Vutla lokeshvutla@ti.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +choice + prompt "K3 AM65 based boards" + optional + +config TARGET_AM654_A53_EVM + bool "TI K3 based AM654 EVM running on A53" + select ARM64 + select SOC_K3_AM6 + +endchoice + +if TARGET_AM654_A53_EVM + +config SYS_BOARD + default "am65x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am65x_evm" + +endif diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS new file mode 100644 index 0000000000..c5921b4a28 --- /dev/null +++ b/board/ti/am65x/MAINTAINERS @@ -0,0 +1,5 @@ +AM65x BOARD +M: Lokesh Vutla lokeshvutla@ti.com +S: Maintained +F: board/ti/am65x/ +F: include/configs/am65x_evm.h diff --git a/board/ti/am65x/Makefile b/board/ti/am65x/Makefile new file mode 100644 index 0000000000..94dddfcc4a --- /dev/null +++ b/board/ti/am65x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Lokesh Vutla lokeshvutla@ti.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := evm.o diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c new file mode 100644 index 0000000000..db2c90e948 --- /dev/null +++ b/board/ti/am65x/evm.c @@ -0,0 +1,56 @@ +/* + * Board specific initialization for AM654 EVM + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla lokeshvutla@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + + return 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + + return gd->ram_top; +} + +int dram_init_banksize(void) +{ + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR high region */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].size = 0x80000000; +#endif + + return 0; +} diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h new file mode 100644 index 0000000000..ee8a984cfc --- /dev/null +++ b/include/configs/am65x_evm.h @@ -0,0 +1,36 @@ +/* + * Configuration header file for K3 AM654 EVM + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla lokeshvutla@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM654_EVM_H +#define __CONFIG_AM654_EVM_H + +#include <linux/sizes.h> +#include <config_distro_bootcmd.h> + +#define CONFIG_ENV_SIZE (128 << 10) + +/* DDR Configuration */ +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +/* SPL Loader Configuration */ +#ifdef CONFIG_TARGET_AM654_A53_EVM +#define CONFIG_SPL_TEXT_BASE 0x80080000 +#endif + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SPL_MAX_SIZE CONFIG_MAX_DOWNLODABLE_IMAGE_SIZE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_NON_SECURE_MSRAM_SIZE - 4) + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_AM654_EVM_H */

Add README file that describes the building and booting procedure.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am65x/README | 134 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 board/ti/am65x/README

diff --git a/board/ti/am65x/README b/board/ti/am65x/README new file mode 100644 index 0000000000..1956142270 --- /dev/null +++ b/board/ti/am65x/README @@ -0,0 +1,134 @@ +Introduction: +------------- +The AM65x family of SoCs is the first device family from K3 Multicore +SoC architecture, targeted for broad market and industrial control with +aim to meet the complex processing needs of modern embedded products. + +The device is built over three domains, each containing specific processing +cores, voltage domains and peripherals: +1. Wake-up (WKUP) domain: + - Device Management and Security Controller (DMSC) +2. Microcontroller (MCU) domain: + - Dual Core ARM Cortex-R5F processor +3. MAIN domain: + - Quad core 64-bit ARM Cortex-A53 + +More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7 + +Boot Flow: +---------- +On AM65x family devices, ROM supports boot only via MCU(R5). This means that +bootloader has to run on R5 core. In order to meet this constraint, +keeping safety in picture and to have faster boot time, the software boot +architecture is designed as below: + ++------------------------------------------------------------------------+ +| DMSC | R5 | A53 | ++------------------------------------------------------------------------+ +| +--------+ | | | +| | Reset | | | | +| +--------+ | | | +| : | | | +| +--------+ | +-----------+ | | +| | *rom* |----------|-->| Reset rls | | | +| +--------+ | +-----------+ | | +| | | | : | | +| | rom | | : | | +| |services| | : | | +| | | | +-------------+ | | +| | | | | *R5 rom* | | | +| | | | +-------------+ | | +| | |<---------|---|Load and auth| | | +| | | | | tiboot3.bin | | | +| | | | +-------------+ | | +| | | | : | | +| | | | : | | +| | | | : | | +| | | | +-------------+ | | +| | Start | | | *R5 SPL* | | | +| | System | | +-------------+ | | +| |Firmware|<---------|---|Load and auth| | | +| +--------+ | | sysfw bin | | | +| : | +-------------+ | | +| +---------+ | | DDR | | | +| | *SYSFW* | | | config | | | +| +---------+ | +-------------+ | | +| | |<--------|---| Load | | | +| | | | | tispl.bin | | | +| | | | +-------------+ | | +| | |<--------|---| Start A53 | | | +| | | | | and Reset | | | +| | | | +-------------+ | | +| | | | | +-----------+ | +| | |---------|-----------------------|---->| Reset rls | | +| | | | | +-----------+ | +| | DMSC | | | : | +| |Services | | | +-----------+ | +| | |<--------|-----------------------|---->|*ATF/OPTEE*| | +| | | | | +-----------+ | +| | | | | : | +| | | | | +-----------+ | +| | |<--------|-----------------------|---->| *A53 SPL* | | +| | | | | +-----------+ | +| | | | | | Load | | +| | | | | | u-boot.img| | +| | | | | +-----------+ | +| | | | | : | +| | | | | +-----------+ | +| | |<--------|-----------------------|---->| *u-boot* | | +| | | | | +-----------+ | +| | | | | | prompt | | +| | | | | +-----------+ | +| +---------+ | | | +| | | | ++------------------------------------------------------------------------+ + +- Here DMSC acts as master and provides all the critical services. R5/A53 +requests DMSC to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + System Firmware repo is closed source and the binaries are delivered + to users with NDA. Please contact TI to get the System Firmware + Binary named ti-sci-firmware-am6x.bin that runs on AM65x SoC. + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. U-Boot: + Tree: http://git.denx.de/u-boot.git + Branch: master + +Build procedure: +---------------- +1. SYSFW: + ROM expects a signed binary that contains the X509 certificate. So +the binary ti-sci-firmware-am6x.bin cannot be uses as-is and needs to be signed. +Contact TI on the procedure to sign the system firmware binary. + +2. ATF: +$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + +3. OPTEE: +$ make PLATFORM=k3-am65x CFG_ARM64_core=y + +4. U-Boot: + +4.1. R5: + TBD. + +4.2. A53: +$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53 +$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53 + +Target Images +-------------- +Copy the below images to an SD card and boot: +- tiboot3.bin from step 4.1 +- tispl.bin, u-boot.img from 4.2

From: Andreas Dannenberg dannenberg@ti.com

Create a basic U-Boot environment that allows the automatic loading of a Linux Kernel located at /boot/Image and an associated device tree blob located at /boot/k3-am654-base-board.dtb from the secondary partition of an ext4-formatted SD card on the AM654x EVM. Furthermore the boot.scr and uEnv.txt detection and loading schemes are supported in a manner already known from other TI platforms.

Note that this is intended to be a starting point to enable initial board use and will most certainly get extended and refactored as different boot media become available.

Signed-off-by: Andreas Dannenberg dannenberg@ti.com --- include/configs/am65x_evm.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)

diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index ee8a984cfc..06b7624cd1 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -12,6 +12,7 @@

#include <linux/sizes.h> #include <config_distro_bootcmd.h> +#include <environment/ti/mmc.h>

#define CONFIG_ENV_SIZE (128 << 10)

@@ -30,6 +31,40 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_NON_SECURE_MSRAM_SIZE - 4)

+/* U-Boot general configuration */ +#define EXTRA_ENV_AM65X_BOARD_SETTINGS \ + "findfdt=" \ + "if test $board_name = am65x; then " \ + "setenv name_fdt k3-am654-base-board.dtb; " \ + "else if test $name_fdt = undefined; then " \ + "echo WARNING: Could not determine device tree to use;"\ + "fi; fi; " \ + "setenv fdtfile ${name_fdt}\0" \ + "loadaddr=0x80080000\0" \ + "fdtaddr=0x82000000\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM65X_BOARD_SETTINGS \ + EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC + /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h>

Add initial DT support for AM654 EVM that runs on A53.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- - Fetched from Linux next that are in queue for 4.19-rc1

arch/arm/dts/Makefile | 2 + arch/arm/dts/k3-am65-main.dtsi | 31 ++++++++ arch/arm/dts/k3-am65.dtsi | 87 ++++++++++++++++++++ arch/arm/dts/k3-am654-base-board.dts | 36 +++++++++ arch/arm/dts/k3-am654.dtsi | 115 +++++++++++++++++++++++++++ board/ti/am65x/evm.c | 12 +++ 6 files changed, 283 insertions(+) create mode 100644 arch/arm/dts/k3-am65-main.dtsi create mode 100644 arch/arm/dts/k3-am65.dtsi create mode 100644 arch/arm/dts/k3-am654-base-board.dts create mode 100644 arch/arm/dts/k3-am654.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa227262..150e1d4090 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -549,6 +549,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb

+dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb + targets += $(dtb-y)

# Add any required device tree compiler flags here diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi new file mode 100644 index 0000000000..2409344df4 --- /dev/null +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family Main Domain peripherals + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x01800000 0x10000>, /* GICD */ + <0x01880000 0x90000>; /* GICR */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: gic-its@18200000 { + compatible = "arm,gic-v3-its"; + reg = <0x01820000 0x10000>; + msi-controller; + #msi-cells = <1>; + }; + }; +}; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi new file mode 100644 index 0000000000..cede1fa098 --- /dev/null +++ b/arch/arm/dts/k3-am65.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Texas Instruments K3 AM654 SoC"; + compatible = "ti,am654"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: interconnect@100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ + <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ + <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ + <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ + <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ + /* MCUSS Range */ + <0x28380000 0x00 0x28380000 0x03880000>, + <0x40200000 0x00 0x40200000 0x00900100>, + <0x42040000 0x00 0x42040000 0x03ac2400>, + <0x45100000 0x00 0x45100000 0x00c24000>, + <0x46000000 0x00 0x46000000 0x00200000>, + <0x47000000 0x00 0x47000000 0x00068400>; + + cbass_mcu: interconnect@28380000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ + <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ + <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ + <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x46000000 0x46000000 0x00200000>, /* CPSW */ + <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ + + cbass_wakeup: interconnect@42040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* WKUP Basic peripherals */ + ranges = <0x42040000 0x42040000 0x03ac2400>; + }; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am65-main.dtsi" diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts new file mode 100644 index 0000000000..af6956fdc1 --- /dev/null +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am654.dtsi" + +/ { + compatible = "ti,am654-evm", "ti,am654"; + model = "Texas Instruments AM654 Base Board"; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + secure_ddr: secure_ddr@9e800000 { + reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; diff --git a/arch/arm/dts/k3-am654.dtsi b/arch/arm/dts/k3-am654.dtsi new file mode 100644 index 0000000000..2affa6f661 --- /dev/null +++ b/arch/arm/dts/k3-am654.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC family in Quad core configuration + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "k3-am65.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; +}; diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index db2c90e948..747cd58958 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -54,3 +54,15 @@ int dram_init_banksize(void)

return 0; } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ +#ifdef CONFIG_TARGET_AM654_A53_EVM + if (!strcmp(name, "k3-am654-base-board")) + return 0; +#endif + + return -1; +} +#endif

Add the minimum dt nodes required to boot. These nodes will get deleted as kernel gets these nodes added in the main dts files.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 203 +++++++++++++++++++ include/dt-bindings/pinctrl/k3-am65.h | 49 +++++ 2 files changed, 252 insertions(+) create mode 100644 arch/arm/dts/k3-am654-base-board-u-boot.dtsi create mode 100644 include/dt-bindings/pinctrl/k3-am65.h

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi new file mode 100644 index 0000000000..d4ecb3be10 --- /dev/null +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/pinctrl/k3-am65.h> + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial2 = &main_uart0; + }; +}; + +&cbass_main{ + u-boot,dm-spl; + secure_proxy: secure_proxy@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x32c00000 0x100000>, + <0x32400000 0x100000>, + <0x32800000 0x100000>; + interrupt-names = "rx_011"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + }; + + dmsc: dmsc { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* + * In case of rare platforms that does not use am6 as + * system master, use /delete-property/ + */ + ti,system-reboot-controller; + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy 11>, + <&secure_proxy 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <1>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + }; + }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x11c000 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinmux@11c2e8 { + compatible = "pinctrl-single"; + reg = <0x11c2e8 0x24>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x02800000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + sdhci0: sdhci@04F80000 { + compatible = "arasan,sdhci-5.1"; + reg = <0x4F80000 0x1000>, + <0x4F90000 0x400>; + clocks = <&k3_clks 47 1>; + power-domains = <&k3_pds 47>; + max-frequency = <25000000>; + }; + + sdhci1: sdhci@04FA0000 { + compatible = "arasan,sdhci-5.1"; + reg = <0x4FA0000 0x1000>, + <0x4FB0000 0x400>; + clocks = <&k3_clks 48 1>; + power-domains = <&k3_pds 48>; + max-frequency = <25000000>; + }; + +}; + +&secure_proxy { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; + main_uart0_pins_default: main_uart0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */ + >; + }; + + main_mmc0_pins_default: main_mmc0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */ + >; + }; + + main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */ + >; + }; + +}; + +&main_pmx1 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&sdhci0 { + u-boot,dm-spl; + status = "okay"; + non-removable; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; +}; + +&sdhci1 { + u-boot,dm-spl; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + sdhci-caps-mask = <0x7 0x0>; +}; diff --git a/include/dt-bindings/pinctrl/k3-am65.h b/include/dt-bindings/pinctrl/k3-am65.h new file mode 100644 index 0000000000..7bd5e894a5 --- /dev/null +++ b/include/dt-bindings/pinctrl/k3-am65.h @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This header provides constants for TI K3-AM65 pinctrl bindings. + * + * Copyright (C) 2018 Texas Instruments + */ +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H +#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H + +/* K3 mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 +#define MUX_MODE15 15 + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_200MHZ 0 +#define SLEWCTRL_150MHZ (1 << 19) +#define SLEWCTRL_100MHZ (2 << 19) +#define SLEWCTRL_50MHZ (3 << 19) +#define TX_DIS (1 << 21) +#define ISO_OVR (1 << 22) +#define ISO_BYPASS (1 << 23) +#define DS_EN (1 << 24) +#define DS_INPUT (1 << 25) +#define DS_FORCE_OUT_HIGH (1 << 26) +#define DS_PULL_UP_DOWN_EN 0 +#define DS_PULL_UP_DOWN_DIS (1 << 27) +#define DS_PULL_UP_SEL (1 << 28) +#define WAKEUP_ENABLE (1 << 29) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val) +#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val) + +#endif

Add initial defconfig support for AM65x that runs on A53.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Andreas Dannenberg dannenberg@ti.com --- board/ti/am65x/MAINTAINERS | 1 + configs/am65x_evm_a53_defconfig | 71 +++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 configs/am65x_evm_a53_defconfig

diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS index c5921b4a28..ca1ce58f72 100644 --- a/board/ti/am65x/MAINTAINERS +++ b/board/ti/am65x/MAINTAINERS @@ -3,3 +3,4 @@ M: Lokesh Vutla lokeshvutla@ti.com S: Maintained F: board/ti/am65x/ F: include/configs/am65x_evm.h +F: configs/am65x_evm_a53_defconfig diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig new file mode 100644 index 0000000000..5b08409249 --- /dev/null +++ b/configs/am65x_evm_a53_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SOC_K3_AM6=y +CONFIG_TARGET_AM654_A53_EVM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_INTERFACE="mmc" +CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_K3_ARASAN=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_K3=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y