This Makefile variable can be used in the architecture's main Makefile but at present it is not set up until later. Set it just before this Makefile is included.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

scripts/Makefile.spl | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 03a2f06..f490e29 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -35,6 +35,12 @@ else SPL_BIN := u-boot-spl endif

+ifdef CONFIG_SPL_BUILD +SPL_ := SPL_ +else +SPL_ := +endif + include $(srctree)/config.mk include $(srctree)/arch/$(ARCH)/Makefile

Add a new Kconfig option to allow CPU drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/spl/Kconfig | 10 ++++++++++ drivers/Makefile | 1 + 2 files changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index bb99f1f..ae46157 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -123,6 +123,16 @@ config SPL_SHA256_SUPPORT SHA256 variant is supported: SHA512 and others are not currently supported in U-Boot.

+config SPL_CPU_SUPPORT + bool "Support CPU drivers" + depends on SPL + help + Enable this to support CPU drivers in SPL. These drivers can set + up CPUs and provide information about them such as the model and + name. This can be useful in SPL since setting up the CPUs earlier + may improve boot performance. Enable this option to build the + drivers in drivers/cpu as part of an SPL build. + config SPL_CRYPTO_SUPPORT bool "Support crypto drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 761d0b3..de8d22a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM) += ram/

ifdef CONFIG_SPL_BUILD

+obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/

Add a new Kconfig option to allow PCI drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ae46157..305c75f 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -409,6 +409,15 @@ config SYS_OS_BASE

endif # SPL_OS_BOOT

+config SPL_PCI_SUPPORT + bool "Support PCI drivers" + depends on SPL + help + Enable support for PCI in SPL. For platforms that need PCI to boot, + or must perform some init using PCI in SPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of an SPL build. + config SPL_POST_MEM_SUPPORT bool "Support POST drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index de8d22a..eae48d0 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ +obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/

Add a new Kconfig option to allow RTC drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/spl/Kconfig | 10 ++++++++++ drivers/Makefile | 1 + 2 files changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 305c75f..f4dcc4e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -441,6 +441,16 @@ config SPL_POWER_SUPPORT in drivers/power, drivers/power/pmic and drivers/power/regulator as part of an SPL build.

+config SPL_RTC_SUPPORT + bool "Support RTC drivers" + depends on SPL + help + Enable RTC (Real-time Clock) support in SPL. This includes support + for reading and setting the time. Some RTC devices also have some + non-volatile (battery-backed) memory which is accessible if + needed. This enables the drivers in drivers/rtc as part of an SPL + build. + config SPL_SATA_SUPPORT bool "Support loading from SATA" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index eae48d0..e5b443e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ +obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/

Add a new Kconfig option to allow timer drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f4dcc4e..8b3bce9 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -494,6 +494,15 @@ config SPL_SPI_SUPPORT enable SPI drivers that are needed for other purposes also, such as a SPI PMIC.

+config SPL_TIMER_SUPPORT + bool "Support timer drivers" + depends on SPL + help + Enable support for timer drivers in SPL. These can be used to get + a timer value when in SPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + SPL build. + config SPL_USBETH_SUPPORT bool "Support USB Ethernet drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index e5b443e..4faa284 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ +obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/

Add an option for building Platorm Controller Hub drivers in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 8b3bce9..3849b04 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -418,6 +418,15 @@ config SPL_PCI_SUPPORT necessary driver support. This enables the drivers in drivers/pci as part of an SPL build.

+config SPL_PCH_SUPPORT + bool "Support PCH drivers" + depends on SPL + help + Enable support for PCH (Platform Controller Hub) devices in SPL. + These are used to set up GPIOs and the SPI peripheral early in + boot. This enables the drivers in drivers/pch as part of an SPL + build. + config SPL_POST_MEM_SUPPORT bool "Support POST drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 4faa284..cb8021c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ +obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/ obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/

When BSS does not immediate follow the SPL image we don't need padding before the device tree. Remove it in this case.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

scripts/Makefile.spl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index f490e29..1dd0d50 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -192,7 +192,8 @@ quiet_cmd_copy = COPY $@ cmd_copy = cp $< $@

ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy) -$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \ +$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ + $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(obj)/$(SPL_BIN).dtb FORCE $(call if_changed,cat)

We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Move table-related changes from a later patch - Rebase to mainline - Drop the write_smbios_table_wrapper() function

arch/x86/cpu/irq.c | 2 +- arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/mpspec.h | 2 +- arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/tables.h | 2 +- arch/x86/lib/acpi_table.c | 4 ++-- arch/x86/lib/mpspec.c | 2 +- arch/x86/lib/sfi.c | 6 +++--- arch/x86/lib/tables.c | 11 ++--------- arch/x86/lib/zimage.c | 2 +- drivers/misc/qfw.c | 4 ++-- include/smbios.h | 4 ++-- lib/smbios.c | 22 +++++++++++----------- 13 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 9364410..e3e928b 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -264,7 +264,7 @@ int irq_router_probe(struct udevice *dev) return irq_router_common_init(dev); }

-u32 write_pirq_routing_table(u32 addr) +ulong write_pirq_routing_table(ulong addr) { if (!pirq_routing_table) return addr; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index caff4d8..bbd80a1 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -316,4 +316,4 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); void acpi_create_gnvs(struct acpi_global_nvs *gnvs); -u32 write_acpi_tables(u32 start); +ulong write_acpi_tables(ulong start); diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index ad8eba9..146a4b0 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -456,6 +456,6 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); * @addr: start address to write MP table * @return: end address of MP table */ -u32 write_mp_table(u32 addr); +ulong write_mp_table(ulong addr);

#endif /* __ASM_MPSPEC_H */ diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h index d1f0f0c..d6c44c9 100644 --- a/arch/x86/include/asm/sfi.h +++ b/arch/x86/include/asm/sfi.h @@ -132,6 +132,6 @@ typedef int (*sfi_table_handler) (struct sfi_table_header *table); * @base: Address to write table to * @return address to use for the next table */ -u32 write_sfi_table(u32 base); +ulong write_sfi_table(ulong base);

#endif /*_LINUX_SFI_H */ diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index 81f98f2..d1b2388 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -65,6 +65,6 @@ void write_tables(void); * @start: start address to write PIRQ routing table * @return: end address of PIRQ routing table */ -u32 write_pirq_routing_table(u32 start); +ulong write_pirq_routing_table(ulong start);

#endif /* _X86_TABLES_H_ */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 7001e8b..355456d 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -327,7 +327,7 @@ static void enter_acpi_mode(int pm1_cnt) * QEMU's version of write_acpi_tables is defined in * arch/x86/cpu/qemu/acpi_table.c */ -u32 write_acpi_tables(u32 start) +ulong write_acpi_tables(ulong start) { u32 current; struct acpi_rsdp *rsdp; @@ -345,7 +345,7 @@ u32 write_acpi_tables(u32 start) /* Align ACPI tables to 16 byte */ current = ALIGN(current, 16);

- debug("ACPI: Writing ACPI tables at %x\n", start); + debug("ACPI: Writing ACPI tables at %lx\n", start);

/* We need at least an RSDP and an RSDT Table */ rsdp = (struct acpi_rsdp *)current; diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 6ab43f1..516d7b3 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -365,7 +365,7 @@ static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa) bus_isa, 0, MP_APIC_ALL, 1); }

-u32 write_mp_table(u32 addr) +ulong write_mp_table(ulong addr) { struct mp_config_table *mc; int ioapic_id, ioapic_ver; diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 3d36580..507e037 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -38,14 +38,14 @@ static void *get_entry_start(struct table_info *tab) tab->table[tab->count] = tab->entry_start; tab->entry_start += sizeof(struct sfi_table_header);

- return (void *)tab->entry_start; + return (void *)(uintptr_t)tab->entry_start; }

static void finish_table(struct table_info *tab, const char *sig, void *entry) { struct sfi_table_header *hdr;

- hdr = (struct sfi_table_header *)(tab->base + tab->ptr); + hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr); strcpy(hdr->sig, sig); hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start); hdr->rev = 1; @@ -131,7 +131,7 @@ static int sfi_write_xsdt(struct table_info *tab) return 0; }

-u32 write_sfi_table(u32 base) +ulong write_sfi_table(ulong base) { struct table_info table;

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 5966e58..4f5fe74 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -12,20 +12,13 @@ #include <asm/acpi_table.h> #include <asm/coreboot_tables.h>

-#ifdef CONFIG_GENERATE_SMBIOS_TABLE -static u32 write_smbios_table_wrapper(u32 addr) -{ - return write_smbios_table(addr); -} -#endif - /** * Function prototype to write a specific configuration table * * @addr: start address to write the table * @return: end address of the table */ -typedef u32 (*table_write)(u32 addr); +typedef ulong (*table_write)(ulong addr);

static table_write table_write_funcs[] = { #ifdef CONFIG_GENERATE_PIRQ_TABLE @@ -41,7 +34,7 @@ static table_write table_write_funcs[] = { write_acpi_tables, #endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE - write_smbios_table_wrapper, + write_smbios_table, #endif };

diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 1b33c77..b6b0f2b 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -165,7 +165,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, * A very old kernel MUST have its real-mode code * loaded at 0x90000 */ - if ((u32)setup_base != 0x90000) { + if ((ulong)setup_base != 0x90000) { /* Copy the real-mode kernel */ memmove((void *)0x90000, setup_base, setup_size);

diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index d43d1d3..a8af9e0 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -32,7 +32,7 @@ static LIST_HEAD(fw_list); * be ignored. * @return: 0 on success, or negative value on failure */ -static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr) +static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr) { uint32_t size, align; struct fw_file *file; @@ -147,7 +147,7 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry) }

/* This function loads and patches ACPI tables provided by QEMU */ -u32 write_acpi_tables(u32 addr) +ulong write_acpi_tables(ulong addr) { int i, ret = 0; struct fw_file *file; diff --git a/include/smbios.h b/include/smbios.h index d582d4f..c24d00e 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -225,7 +225,7 @@ static inline void fill_smbios_header(void *table, int type, * @handle: the structure's handle, a unique 16-bit number * @return: size of the structure */ -typedef int (*smbios_write_type)(uintptr_t *addr, int handle); +typedef int (*smbios_write_type)(ulong *addr, int handle);

/** * write_smbios_table() - Write SMBIOS table @@ -235,6 +235,6 @@ typedef int (*smbios_write_type)(uintptr_t *addr, int handle); * @addr: start address to write SMBIOS table * @return: end address of SMBIOS table */ -uintptr_t write_smbios_table(uintptr_t addr); +ulong write_smbios_table(ulong addr);

#endif /* _SMBIOS_H_ */ diff --git a/lib/smbios.c b/lib/smbios.c index ce1974d..22ca247 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -73,7 +73,7 @@ static int smbios_string_table_len(char *start) return len + 1; }

-static int smbios_write_type0(uintptr_t *current, int handle) +static int smbios_write_type0(ulong *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; int len = sizeof(struct smbios_type0); @@ -108,7 +108,7 @@ static int smbios_write_type0(uintptr_t *current, int handle) return len; }

-static int smbios_write_type1(uintptr_t *current, int handle) +static int smbios_write_type1(ulong *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; int len = sizeof(struct smbios_type1); @@ -129,7 +129,7 @@ static int smbios_write_type1(uintptr_t *current, int handle) return len; }

-static int smbios_write_type2(uintptr_t *current, int handle) +static int smbios_write_type2(ulong *current, int handle) { struct smbios_type2 *t = (struct smbios_type2 *)*current; int len = sizeof(struct smbios_type2); @@ -147,7 +147,7 @@ static int smbios_write_type2(uintptr_t *current, int handle) return len; }

-static int smbios_write_type3(uintptr_t *current, int handle) +static int smbios_write_type3(ulong *current, int handle) { struct smbios_type3 *t = (struct smbios_type3 *)*current; int len = sizeof(struct smbios_type3); @@ -199,7 +199,7 @@ static void smbios_write_type4_dm(struct smbios_type4 *t) t->processor_version = smbios_add_string(t->eos, name); }

-static int smbios_write_type4(uintptr_t *current, int handle) +static int smbios_write_type4(ulong *current, int handle) { struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -221,7 +221,7 @@ static int smbios_write_type4(uintptr_t *current, int handle) return len; }

-static int smbios_write_type32(uintptr_t *current, int handle) +static int smbios_write_type32(ulong *current, int handle) { struct smbios_type32 *t = (struct smbios_type32 *)*current; int len = sizeof(struct smbios_type32); @@ -234,7 +234,7 @@ static int smbios_write_type32(uintptr_t *current, int handle) return len; }

-static int smbios_write_type127(uintptr_t *current, int handle) +static int smbios_write_type127(ulong *current, int handle) { struct smbios_type127 *t = (struct smbios_type127 *)*current; int len = sizeof(struct smbios_type127); @@ -257,10 +257,10 @@ static smbios_write_type smbios_write_funcs[] = { smbios_write_type127 };

-uintptr_t write_smbios_table(uintptr_t addr) +ulong write_smbios_table(ulong addr) { struct smbios_entry *se; - u32 tables; + ulong tables; int len = 0; int max_struct_size = 0; int handle = 0; @@ -271,7 +271,7 @@ uintptr_t write_smbios_table(uintptr_t addr) /* 16 byte align the table address */ addr = ALIGN(addr, 16);

- se = (struct smbios_entry *)addr; + se = (struct smbios_entry *)(uintptr_t)addr; memset(se, 0, sizeof(struct smbios_entry));

addr += sizeof(struct smbios_entry); @@ -280,7 +280,7 @@ uintptr_t write_smbios_table(uintptr_t addr)

/* populate minimum required tables */ for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) { - int tmp = smbios_write_funcs[i](&addr, handle++); + int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++); max_struct_size = max(max_struct_size, tmp); len += tmp; }

At present this uses u32 to store an address. We should use unsigned long and avoid special types in function return values and parameters unless necessary. This makes the code more portable.

I believe Alex Graf has a patch to correct all of these, so this is just a WIP patch.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/mpspec.h | 8 ++++---- arch/x86/lib/mpspec.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index 146a4b0..30dbdca 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -224,9 +224,9 @@ struct mp_ext_compat_address_space { * @mc: configuration table header address * @return: configuration table end address */ -static inline u32 mp_next_mpc_entry(struct mp_config_table *mc) +static inline ulong mp_next_mpc_entry(struct mp_config_table *mc) { - return (u32)mc + mc->mpc_length; + return (ulong)mc + mc->mpc_length; }

/** @@ -254,9 +254,9 @@ static inline void mp_add_mpc_entry(struct mp_config_table *mc, uint length) * @mc: configuration table header address * @return: configuration table end address */ -static inline u32 mp_next_mpe_entry(struct mp_config_table *mc) +static inline ulong mp_next_mpe_entry(struct mp_config_table *mc) { - return (u32)mc + mc->mpc_length + mc->mpe_length; + return (ulong)mc + mc->mpc_length + mc->mpe_length; }

/** diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 516d7b3..17e977c 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -25,10 +25,10 @@ static bool isa_irq_occupied[16];

struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf) { - u32 mc; + ulong mc;

memcpy(mf->mpf_signature, MPF_SIGNATURE, 4); - mf->mpf_physptr = (u32)mf + sizeof(struct mp_floating_table); + mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table); mf->mpf_length = 1; mf->mpf_spec = MPSPEC_V14; mf->mpf_checksum = 0; @@ -41,7 +41,7 @@ struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf) mf->mpf_feature5 = 0; mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);

- mc = (u32)mf + sizeof(struct mp_floating_table); + mc = (ulong)mf + sizeof(struct mp_floating_table); return (struct mp_config_table *)mc; }

@@ -219,14 +219,14 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid,

u32 mptable_finalize(struct mp_config_table *mc) { - u32 end; + ulong end;

mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length); end = mp_next_mpe_entry(mc);

- debug("Write the MP table at: %x - %x\n", (u32)mc, end); + debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);

return end; } @@ -371,7 +371,7 @@ ulong write_mp_table(ulong addr) int ioapic_id, ioapic_ver; int bus_isa = 0xff; int ret; - u32 end; + ulong end;

/* 16 byte align the table address */ addr = ALIGN(addr, 16);

Add a link script and relocation code for building 64-bit EFI applications. This can be used for the EFI stub.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/elf_x86_64_efi.lds | 3 ++ arch/x86/lib/reloc_x86_64.c | 90 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 arch/x86/lib/reloc_x86_64.c

diff --git a/arch/x86/lib/elf_x86_64_efi.lds b/arch/x86/lib/elf_x86_64_efi.lds index 70c7c52..886ebef 100644 --- a/arch/x86/lib/elf_x86_64_efi.lds +++ b/arch/x86/lib/elf_x86_64_efi.lds @@ -54,6 +54,9 @@ SECTIONS *(SORT(.u_boot_list*)); . = ALIGN(8); *(.dtb*); + /* Keep U-Boot payload */ + . = ALIGN(8); + KEEP(*(.u_boot_bin.*)); }

. = ALIGN(4096); diff --git a/arch/x86/lib/reloc_x86_64.c b/arch/x86/lib/reloc_x86_64.c new file mode 100644 index 0000000..70a2b2a --- /dev/null +++ b/arch/x86/lib/reloc_x86_64.c @@ -0,0 +1,90 @@ +/* reloc_x86_64.c - position independent x86_64 ELF shared object relocator + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger davidm@hpl.hp.com. + Copyright (C) 2005 Intel Co. + Contributed by Fenghua Yu fenghua.yu@intel.com. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + +#include <common.h> +#include <efi.h> +#include <elf.h> +#include <asm/elf.h> + +efi_status_t _relocate(long ldbase, Elf64_Dyn *dyn, efi_handle_t image, + struct efi_system_table *systab) +{ + long relsz = 0, relent = 0; + struct elf64_rel *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_RELA: + rel = (struct elf64_rel *) + ((unsigned long)dyn[i].d_un.d_ptr + ldbase); + break; + case DT_RELASZ: + relsz = dyn[i].d_un.d_val; + break; + case DT_RELAENT: + relent = dyn[i].d_un.d_val; + break; + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF64_R_TYPE(rel->r_info)) { + case R_X86_64_NONE: + break; + case R_X86_64_RELATIVE: + addr = (unsigned long *)(ldbase + rel->r_offset); + *addr += ldbase; + break; + default: + break; + } + rel = (struct elf64_rel *)((char *)rel + relent); + relsz -= relent; + } + return EFI_SUCCESS; +}

Some files are missing this declaration. Add it to avoid build errors when we actually need the declaration.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: - Drop change to gma.c

arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++ arch/x86/cpu/ivybridge/lpc.c | 2 ++ arch/x86/cpu/ivybridge/model_206ax.c | 2 ++ arch/x86/cpu/ivybridge/northbridge.c | 2 ++ drivers/video/ivybridge_igd.c | 2 ++ 5 files changed, 10 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index e63ea6b..e3eff69 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -19,6 +19,8 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

+DECLARE_GLOBAL_DATA_PTR; + #define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 4af89b3..aef1206 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -20,6 +20,8 @@ #include <asm/pci.h> #include <asm/arch/pch.h>

+DECLARE_GLOBAL_DATA_PTR; + #define NMI_OFF 0

#define ENABLE_ACPI_MODE_IN_COREBOOT 0 diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 09b5342..d5f3219 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -22,6 +22,8 @@ #include <asm/turbo.h> #include <asm/arch/model_206ax.h>

+DECLARE_GLOBAL_DATA_PTR; + static void enable_vmx(void) { struct cpuid_result regs; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 491f289..94f31c4 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -19,6 +19,8 @@ #include <asm/arch/model_206ax.h> #include <asm/arch/sandybridge.h>

+DECLARE_GLOBAL_DATA_PTR; + int bridge_silicon_revision(struct udevice *dev) { struct cpuid_result result; diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c index 94db3dd..95d62a5 100644 --- a/drivers/video/ivybridge_igd.c +++ b/drivers/video/ivybridge_igd.c @@ -18,6 +18,8 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

+DECLARE_GLOBAL_DATA_PTR; + struct gt_powermeter { u16 reg; u32 value;

Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be built as a 64-bit application, with SPL doing the 16/32-bit init.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/Kconfig | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0884af2..5db8f13 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -5,6 +5,52 @@ config SYS_ARCH default "x86"

choice + prompt "Run U-Boot in 32/64-bit mode" + default X86_RUN_32BIT + help + U-Boot can be built as a 32-bit binary which runs in 32-bit mode + even on 64-bit machines. In this case SPL is not used, and U-Boot + runs directly from the reset vector (via 16-bit start-up). + + Alternatively it can be run as a 64-bit binary, thus requiring a + 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit + start-up) then jumps to U-Boot in 64-bit mode. + + For now, 32-bit mode is recommended, as 64-bit is still + experimental and is missing a lot of features. + +config X86_RUN_32BIT + bool "32-bit" + help + Build U-Boot as a 32-bit binary with no SPL. This is the currently + supported normal setup. U-Boot will stay in 32-bit mode even on + 64-bit machines. When booting a 64-bit kernel, U-Boot will switch + to 64-bit just before starting the kernel. Only the bottom 4GB of + memory can be accessed through normal means, although + arch_phys_memset() can be used for basic access to other memory. + +config X86_RUN_64BIT + bool "64-bit" + select X86_64 + select SUPPORT_SPL + select SPL + select SPL_SEPARATE_BSS + help + Build U-Boot as a 64-bit binary with a 32-bit SPL. This is + experimental and many features are missing. U-Boot SPL starts up, + runs through the 16-bit and 32-bit init, then switches to 64-bit + mode and jumps to U-Boot proper. + +endchoice + +config X86_64 + bool + +config SPL_X86_64 + bool + depends on SPL + +choice prompt "Mainboard vendor" default VENDOR_EMULATION

At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If this is enabled, then U-Boot is the 'first' boot loader and handles execution from the reset vector through to U-Boot's command prompt. If it is not enabled then U-Boot starts at the 32-bit entry and skips most of its init, assuming that the previous boot loader has done this already.

With the move to suport 64-bit operation, we have more cases to consider. The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper.

Add Kconfig options which control the location of the 16-bit and the 32-bit init. These are not intended to be user-setting except for experimentation. Their values should be determined by whether 64-bit U-Boot is used.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5db8f13..e57362e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -135,6 +135,45 @@ config X86_RESET_VECTOR bool default n

+# The following options control where the 16-bit and 32-bit init lies +# If SPL is enabled then it normally holds this init code, and U-Boot proper +# is normally a 64-bit build. +# +# The 16-bit init refers to the reset vector and the small amount of code to +# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, +# or missing altogether if U-Boot is started from EFI or coreboot. +# +# The 32-bit init refers to processor init, running binary blobs including +# FSP, setting up interrupts and anything else that needs to be done in +# 32-bit code. It is normally in the same place as 32-bit init. +config X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && !SPL + help + This is enabled when 16-bit init is in U-Boot proper + +config SPL_X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && SPL + help + This is enabled when 16-bit init is in SPL + +config X86_32BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && !SPL + help + This is enabled when 32-bit init is in U-Boot proper + +config SPL_X86_32BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && SPL + help + This is enabled when 32-bit init is in SPL + config RESET_SEG_START hex depends on X86_RESET_VECTOR

Use this new option to control the location of 16-bit init. This will allow us to place this in SPL if needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

Makefile | 7 ++++--- arch/x86/Makefile | 6 ++---- arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/u-boot.lds | 2 +- 4 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile index 4121b25..3cb340d 100644 --- a/Makefile +++ b/Makefile @@ -877,7 +877,7 @@ u-boot.hex u-boot.srec: u-boot FORCE $(call if_changed,objcopy)

OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ - $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec) + $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)

binary_size_check: u-boot-nodtb.bin FORCE @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ @@ -1065,8 +1065,9 @@ quiet_cmd_ldr = LD $@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \ $(filter-out FORCE,$^) -o $@

-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \ - $(if $(CONFIG_HAVE_REFCODE),refcode.bin) +u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \ + $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \ + $(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE $(call if_changed,binman)

OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec diff --git a/arch/x86/Makefile b/arch/x86/Makefile index d104a49..dd0e22f 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -5,10 +5,8 @@ ifeq ($(CONFIG_EFI_APP),) head-y := arch/x86/cpu/start.o endif -ifeq ($(CONFIG_SPL_BUILD),y) -head-y += arch/x86/cpu/start16.o -head-y += arch/x86/cpu/resetvec.o -endif +head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o +head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o

libs-y += arch/x86/cpu/ libs-y += arch/x86/lib/ diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index f5b8c9e..fd81310 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -9,7 +9,7 @@ #

extra-y = start.o -obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o +extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o

AFLAGS_REMOVE_call32.o := -mregparm=3 \ diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index cca536b..186718d 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -103,7 +103,7 @@ SECTIONS /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) }

-#ifdef CONFIG_X86_RESET_VECTOR +#ifdef CONFIG_X86_16BIT_INIT /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM

Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/intel_common/Makefile | 10 ++++++---- arch/x86/lib/init_helpers.c | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 804c539..1145e78 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -4,13 +4,15 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-$(CONFIG_HAVE_MRC) += car.o +ifdef CONFIG_HAVE_MRC +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o +endif obj-y += cpu.o obj-y += lpc.o -obj-$(CONFIG_HAVE_MRC) += me_status.o ifndef CONFIG_TARGET_EFI obj-y += microcode.o endif obj-y += pch.o -obj-$(CONFIG_HAVE_MRC) += report_platform.o -obj-$(CONFIG_HAVE_MRC) += mrc.o diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 2a186fc..420393b 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -19,7 +19,7 @@ __weak ulong board_get_usable_ram_top(ulong total_size)

int init_cache_f_r(void) { -#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP) +#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) int ret;

ret = mtrr_commit(false);

Update the Makefile so that some 32-bit init can be built into SPL rather than U-Boot proper.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/ivybridge/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 498e71a..d13d0d3 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,12 +7,12 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-y += cpu.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o obj-y += model_206ax.o obj-y += northbridge.o obj-y += sata.o -obj-y += sdram.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o endif obj-y += bd82x6x.o

Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are running from RAM and SPL has done the low-level init.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/Makefile | 5 +++++ arch/x86/cpu/Makefile | 4 ++++ arch/x86/cpu/start64.S | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 arch/x86/cpu/start64.S

diff --git a/arch/x86/Makefile b/arch/x86/Makefile index dd0e22f..4be1c35 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -3,8 +3,13 @@ #

ifeq ($(CONFIG_EFI_APP),) +ifdef CONFIG_$(SPL_)X86_64 +head-y := arch/x86/cpu/start64.o +else head-y := arch/x86/cpu/start.o endif +endif + head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index fd81310..97b26b0 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -8,7 +8,11 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifeq ($(CONFIG_$(SPL_)X86_64),y) +extra-y = start64.o +else extra-y = start.o +endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o

diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S new file mode 100644 index 0000000..9eadc35 --- /dev/null +++ b/arch/x86/cpu/start64.S @@ -0,0 +1,39 @@ +/* + * 64-bit x86 Startup Code + * + * (C) Copyright 216 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/global_data.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/processor-flags.h> +#include <generated/generic-asm-offsets.h> +#include <generated/asm-offsets.h> + +.section .text +.code64 +.globl _start +.type _start, @function +_start: + /* Set up memory using the existing stack */ + mov %rsp, %rdi + call board_init_f_alloc_reserve + mov %rax, %rsp + + call board_init_f_init_reserve + + callq board_init_f + callq board_init_f_r + + /* Should not return here */ + jmp . + + /* If the debug UART is being used, it is already set up by SPL */ + .globl board_debug_uart_init +board_debug_uart_init: + ret

Adjust the code so that 64-bit startup works. Since we don't need to do CAR changes in U-Boot proper anymore (they are done in SPL) we can simplify the flow and return normally from board_init_f().

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/board_f.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c index 4b74835..f19f998 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -767,7 +767,8 @@ static int setup_reloc(void) }

/* ARM calls relocate_code from its crt0.S */ -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ + !CONFIG_IS_ENABLED(X86_64)

static int jump_to_copy(void) { @@ -1045,7 +1046,8 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_XTENSA) clear_bss, #endif -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ + !CONFIG_IS_ENABLED(X86_64) jump_to_copy, #endif NULL, @@ -1079,7 +1081,7 @@ void board_init_f(ulong boot_flags) hang();

#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ - !defined(CONFIG_EFI_APP) + !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) /* NOTREACHED - jump_to_copy() does not return */ hang(); #endif @@ -1103,8 +1105,10 @@ void board_init_f(ulong boot_flags) * NOTE: At present only x86 uses this route, but it is intended that * all archs will move to this when generic relocation is implemented. */ -static init_fnc_t init_sequence_f_r[] = { +static const init_fnc_t init_sequence_f_r[] = { +#if !CONFIG_IS_ENABLED(X86_64) init_cache_f_r, +#endif

NULL, };

Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the time we get to board_init_r(). The old 'gd' variable is passed in as parameter to board_init_r(), presumably for this situation.

Assign it on 64-bit x86 so that gd points to the correct data.

Options to improve this: - Make gd a fixed register and remove the board_init_r() parameter - Make all archs use this board_init_r() parameter

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/board_r.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/common/board_r.c b/common/board_r.c index d959ad3..02800ca 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -974,6 +974,11 @@ init_fnc_t init_sequence_r[] = {

void board_init_r(gd_t *new_gd, ulong dest_addr) { + /* Set up the new global data pointer */ +#if CONFIG_IS_ENABLED(X86_64) + arch_setup_gd(new_gd); +#endif + #ifdef CONFIG_NEEDS_MANUAL_RELOC int i; #endif

The BSS region may overlap with relocations. If we clear BSS we will overwrite the start of the relocation area. This doesn't matter when running from SPI flash, since it is read-only. But when relocating 64-bit U-Boot from one place in RAM to another, relocation will fail because some of its relocations have been zeroed.

To fix this, put the ELF fixup call before the BSS clearing call.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/board_f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c index f19f998..c79ee4e 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1040,8 +1040,8 @@ static init_fnc_t init_sequence_f[] = { setup_reloc, #if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, - clear_bss, do_elf_reloc_fixups, + clear_bss, #endif #if defined(CONFIG_XTENSA) clear_bss,

Move the core relocation code into a separate function so that the checking code can be used for 64-bit relocation also.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/relocate.c | 57 ++++++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 0d683bf..21cd1db 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -47,38 +47,18 @@ int clear_bss(void) return 0; }

-/* - * This function has more error checking than you might expect. Please see - * the commit message for more informaiton. - */ -int do_elf_reloc_fixups(void) +static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size, + Elf32_Rel *re_src, Elf32_Rel *re_end) { - Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start); - Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end); - Elf32_Addr *offset_ptr_rom, *last_offset = NULL; Elf32_Addr *offset_ptr_ram; - unsigned int text_base = 0; - - /* The size of the region of u-boot that runs out of RAM. */ - uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; - - if (gd->flags & GD_FLG_SKIP_RELOC) - return 0; - if (re_src == re_end) - panic("No relocation data");

-#ifdef CONFIG_SYS_TEXT_BASE - text_base = CONFIG_SYS_TEXT_BASE; -#else - panic("No CONFIG_SYS_TEXT_BASE"); -#endif do { /* Get the location from the relocation entry */ - offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + offset_ptr_rom = (Elf32_Addr *)(uintptr_t)re_src->r_offset;

/* Check that the location of the relocation is in .text */ - if (offset_ptr_rom >= (Elf32_Addr *)text_base && + if (offset_ptr_rom >= (Elf32_Addr *)(uintptr_t)text_base && offset_ptr_rom > last_offset) {

/* Switch to the in-RAM version */ @@ -103,6 +83,35 @@ int do_elf_reloc_fixups(void) last_offset = offset_ptr_rom;

} while (++re_src < re_end); +} + +/* + * This function has more error checking than you might expect. Please see + * the commit message for more informaiton. + */ +int do_elf_reloc_fixups(void) +{ + void *re_src = (void *)(&__rel_dyn_start); + void *re_end = (void *)(&__rel_dyn_end); + uint text_base; + + /* The size of the region of u-boot that runs out of RAM. */ + uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; + if (re_src == re_end) { + printf("No relocation data %p %p", re_src, re_end); + while (1); + panic("No relocation data"); + } + +#ifdef CONFIG_SYS_TEXT_BASE + text_base = CONFIG_SYS_TEXT_BASE; +#else + panic("No CONFIG_SYS_TEXT_BASE"); +#endif + do_elf_reloc_fixups32(text_base, size, re_src, re_end);

return 0; }

Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed address and runs it. U-Boot then relocates itself to the top of RAM using this relocation function.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/relocate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 21cd1db..bac2fb6 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -47,6 +47,46 @@ int clear_bss(void) return 0; }

+#if CONFIG_IS_ENABLED(X86_64) +static void do_elf_reloc_fixups64(unsigned int text_base, uintptr_t size, + Elf64_Rela *re_src, Elf64_Rela *re_end) +{ + Elf64_Addr *offset_ptr_rom, *last_offset = NULL; + Elf64_Addr *offset_ptr_ram; + + do { + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf64_Addr *)(uintptr_t)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf64_Addr *)(uintptr_t)text_base && + offset_ptr_rom > last_offset) { + /* Switch to the in-RAM version */ + offset_ptr_ram = (Elf64_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); + + /* Check that the target points into .text */ + if (*offset_ptr_ram >= text_base && + *offset_ptr_ram <= text_base + size) { + *offset_ptr_ram = gd->reloc_off + + re_src->r_addend; + } else { + debug(" %p: %lx: rom reloc %lx, ram %p, value %lx, limit %" + PRIXPTR "\n", + re_src, (ulong)re_src->r_info, + (ulong)re_src->r_offset, offset_ptr_ram, + (ulong)*offset_ptr_ram, text_base + size); + } + } else { + debug(" %p: %lx: rom reloc %lx, last %p\n", re_src, + (ulong)re_src->r_info, (ulong)re_src->r_offset, + last_offset); + } + last_offset = offset_ptr_rom; + + } while (++re_src < re_end); +} +#else static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size, Elf32_Rel *re_src, Elf32_Rel *re_end) { @@ -84,6 +124,7 @@ static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,

} while (++re_src < re_end); } +#endif

/* * This function has more error checking than you might expect. Please see @@ -111,7 +152,11 @@ int do_elf_reloc_fixups(void) #else panic("No CONFIG_SYS_TEXT_BASE"); #endif +#if CONFIG_IS_ENABLED(X86_64) + do_elf_reloc_fixups64(text_base, size, re_src, re_end); +#else do_elf_reloc_fixups32(text_base, size, re_src, re_end); +#endif

return 0; }

Addresses should not be cast to size_t. Use uintptr_t instead.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/relocate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index bac2fb6..ad47c7e 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;

int copy_uboot_to_ram(void) { - size_t len = (size_t)&__data_end - (size_t)&__text_start; + size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;

if (gd->flags & GD_FLG_SKIP_RELOC) return 0; @@ -38,7 +38,7 @@ int copy_uboot_to_ram(void) int clear_bss(void) { ulong dst_addr = (ulong)&__bss_start + gd->reloc_off; - size_t len = (size_t)&__bss_end - (size_t)&__bss_start; + size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;

if (gd->flags & GD_FLG_SKIP_RELOC) return 0;

SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping to it. Call the existing init routines in order to accomplish this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/spl.h | 8 +++ arch/x86/lib/Makefile | 1 + arch/x86/lib/spl.c | 149 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+) create mode 100644 arch/x86/include/asm/spl.h create mode 100644 arch/x86/lib/spl.c

diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h new file mode 100644 index 0000000..a8bce98 --- /dev/null +++ b/arch/x86/include/asm/spl.h @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2014 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file is required for SPL to build, but is empty. + */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index ff402dc..db538ad 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -37,6 +37,7 @@ endif obj-y += tables.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ +obj-$(CONFIG_SPL_BUILD) += spl.o

extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c new file mode 100644 index 0000000..61d085f --- /dev/null +++ b/arch/x86/lib/spl.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <debug_uart.h> +#include <spl.h> +#include <asm/cpu.h> +#include <asm/init_helpers.h> +#include <asm/mtrr.h> +#include <asm/processor.h> +#include <asm-generic/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int x86_spl_init(void) +{ + /* + * TODO(sjg@chromium.org): We use this area of RAM for the stack + * and global_data in SPL. Once U-Boot starts up and releocates it + * is not needed. We could make this a CONFIG option or perhaps + * place it immediately below CONFIG_SYS_TEXT_BASE. + */ + char *ptr = (char *)0x110000; + int ret; + + debug("%s starting\n", __func__); + ret = spl_init(); + if (ret) { + debug("%s: spl_init() failed\n", __func__); + return ret; + } + preloader_console_init(); + + ret = arch_cpu_init(); + if (ret) { + debug("%s: arch_cpu_init() failed\n", __func__); + return ret; + } + ret = arch_cpu_init_dm(); + if (ret) { + debug("%s: arch_cpu_init_dm() failed\n", __func__); + return ret; + } + ret = print_cpuinfo(); + if (ret) { + debug("%s: print_cpuinfo() failed\n", __func__); + return ret; + } + ret = dram_init(); + if (ret) { + debug("%s: dram_init() failed\n", __func__); + return ret; + } + memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); + + /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ + ret = interrupt_init(); + if (ret) { + debug("%s: interrupt_init() failed\n", __func__); + return ret; + } + + gd->new_gd = (struct global_data *)ptr + 0x100; + memcpy(gd->new_gd, gd, sizeof(*gd)); + arch_setup_gd(gd->new_gd); + gd->start_addr_sp = (ulong)ptr; + + /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ + ret = mtrr_add_request(MTRR_TYPE_WRBACK, + (1ULL << 32) - CONFIG_XIP_ROM_SIZE, + CONFIG_XIP_ROM_SIZE); + if (ret) { + debug("%s: SPI cache setup failed\n", __func__); + return ret; + } + + return 0; +} + +void board_init_f(ulong flags) +{ + int ret; + + ret = x86_spl_init(); + if (ret) { + debug("Error %d\n", ret); + hang(); + } + + /* Uninit CAR and jump to board_init_f_r() */ + board_init_f_r_trampoline(gd->start_addr_sp); +} + +void board_init_f_r(void) +{ + init_cache_f_r(); + gd->flags &= ~GD_FLG_SERIAL_READY; + debug("cache status %d\n", dcache_status()); + board_init_r(gd, 0); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOARD; +} + +int spl_start_uboot(void) +{ + return 0; +} + +void spl_board_announce_boot_device(void) +{ + printf("SPI flash"); +} + +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + spl_image->size = CONFIG_SYS_MONITOR_LEN; + spl_image->entry_point = CONFIG_SYS_TEXT_BASE; + spl_image->load_addr = CONFIG_SYS_TEXT_BASE; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + + debug("Loading to %x\n", spl_image->load_addr); + + return 0; +} +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); + +int spl_spi_load_image(void) +{ + return -EPERM; +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + int ret; + + printf("Jumping to 64-bit U-Boot: Note many features are missing\n"); + ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); + debug("ret=%d\n", ret); + while (1); +}

Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it into its own directory and build it only in 32-bit mode.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/Makefile | 6 +- arch/x86/cpu/cpu.c | 504 ---------------------- arch/x86/cpu/i386/Makefile | 7 + arch/x86/cpu/i386/cpu.c | 534 ++++++++++++++++++++++++ arch/x86/cpu/{interrupts.c => i386/interrupt.c} | 4 - arch/x86/include/asm/mp.h | 3 + 6 files changed, 549 insertions(+), 509 deletions(-) create mode 100644 arch/x86/cpu/i386/Makefile create mode 100644 arch/x86/cpu/i386/cpu.c rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 97b26b0..41ad481 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -14,7 +14,7 @@ else extra-y = start.o endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o -obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o +obj-y += cpu.o cpu_x86.o call64.o setjmp.o

AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) @@ -37,3 +37,7 @@ obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SMP) += sipi_vector.o obj-y += turbo.o + +ifeq ($(CONFIG_$(SPL_)X86_64),) +obj-y += i386/ +endif diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 7c1d6de..8fa6953 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -43,55 +43,6 @@

DECLARE_GLOBAL_DATA_PTR;

-/* - * Constructor for a conventional segment GDT (or LDT) entry - * This is a macro so it can be used in initialisers - */ -#define GDT_ENTRY(flags, base, limit) \ - ((((base) & 0xff000000ULL) << (56-24)) | \ - (((flags) & 0x0000f0ffULL) << 40) | \ - (((limit) & 0x000f0000ULL) << (48-16)) | \ - (((base) & 0x00ffffffULL) << 16) | \ - (((limit) & 0x0000ffffULL))) - -struct gdt_ptr { - u16 len; - u32 ptr; -} __packed; - -struct cpu_device_id { - unsigned vendor; - unsigned device; -}; - -struct cpuinfo_x86 { - uint8_t x86; /* CPU family */ - uint8_t x86_vendor; /* CPU vendor */ - uint8_t x86_model; - uint8_t x86_mask; -}; - -/* - * List of cpu vendor strings along with their normalized - * id values. - */ -static const struct { - int vendor; - const char *name; -} x86_vendors[] = { - { X86_VENDOR_INTEL, "GenuineIntel", }, - { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, - { X86_VENDOR_UMC, "UMC UMC UMC ", }, - { X86_VENDOR_NEXGEN, "NexGenDriven", }, - { X86_VENDOR_CENTAUR, "CentaurHauls", }, - { X86_VENDOR_RISE, "RiseRiseRise", }, - { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, - { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, - { X86_VENDOR_NSC, "Geode by NSC", }, - { X86_VENDOR_SIS, "SiS SiS SiS ", }, -}; - static const char *const x86_vendor_name[] = { [X86_VENDOR_INTEL] = "Intel", [X86_VENDOR_CYRIX] = "Cyrix", @@ -105,100 +56,6 @@ static const char *const x86_vendor_name[] = { [X86_VENDOR_SIS] = "SiS", };

-static void load_ds(u32 segment) -{ - asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_es(u32 segment) -{ - asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_fs(u32 segment) -{ - asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_gs(u32 segment) -{ - asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_ss(u32 segment) -{ - asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_gdt(const u64 *boot_gdt, u16 num_entries) -{ - struct gdt_ptr gdt; - - gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; - gdt.ptr = (ulong)boot_gdt; - - asm volatile("lgdtl %0\n" : : "m" (gdt)); -} - -void arch_setup_gd(gd_t *new_gd) -{ - u64 *gdt_addr; - - gdt_addr = new_gd->arch.gdt; - - /* - * CS: code, read/execute, 4 GB, base 0 - * - * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS - */ - gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); - gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); - - /* DS: data, read/write, 4 GB, base 0 */ - gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); - - /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ - new_gd->arch.gd_addr = new_gd; - gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, - (ulong)&new_gd->arch.gd_addr, 0xfffff); - - /* 16-bit CS: code, read/execute, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); - - /* 16-bit DS: data, read/write, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); - - gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); - gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); - - load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); - load_ds(X86_GDT_ENTRY_32BIT_DS); - load_es(X86_GDT_ENTRY_32BIT_DS); - load_gs(X86_GDT_ENTRY_32BIT_DS); - load_ss(X86_GDT_ENTRY_32BIT_DS); - load_fs(X86_GDT_ENTRY_32BIT_FS); -} - -#ifdef CONFIG_HAVE_FSP -/* - * Setup FSP execution environment GDT - * - * Per Intel FSP external architecture specification, before calling any FSP - * APIs, we need make sure the system is in flat 32-bit mode and both the code - * and data selectors should have full 4GB access range. Here we reuse the one - * we used in arch/x86/cpu/start16.S, and reload the segement registers. - */ -void setup_fsp_gdt(void) -{ - load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); - load_ds(X86_GDT_ENTRY_32BIT_DS); - load_ss(X86_GDT_ENTRY_32BIT_DS); - load_es(X86_GDT_ENTRY_32BIT_DS); - load_fs(X86_GDT_ENTRY_32BIT_DS); - load_gs(X86_GDT_ENTRY_32BIT_DS); -} -#endif - int __weak x86_cleanup_before_linux(void) { #ifdef CONFIG_BOOTSTAGE_STASH @@ -209,241 +66,6 @@ int __weak x86_cleanup_before_linux(void) return 0; }

-/* - * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected - * by the fact that they preserve the flags across the division of 5/2. - * PII and PPro exhibit this behavior too, but they have cpuid available. - */ - -/* - * Perform the Cyrix 5/2 test. A Cyrix won't change - * the flags, while other 486 chips will. - */ -static inline int test_cyrix_52div(void) -{ - unsigned int test; - - __asm__ __volatile__( - "sahf\n\t" /* clear flags (%eax = 0x0005) */ - "div %b2\n\t" /* divide 5 by 2 */ - "lahf" /* store flags into %ah */ - : "=a" (test) - : "0" (5), "q" (2) - : "cc"); - - /* AH is 0x02 on Cyrix after the divide.. */ - return (unsigned char) (test >> 8) == 0x02; -} - -/* - * Detect a NexGen CPU running without BIOS hypercode new enough - * to have CPUID. (Thanks to Herbert Oppmann) - */ - -static int deep_magic_nexgen_probe(void) -{ - int ret; - - __asm__ __volatile__ ( - " movw $0x5555, %%ax\n" - " xorw %%dx,%%dx\n" - " movw $2, %%cx\n" - " divw %%cx\n" - " movl $0, %%eax\n" - " jnz 1f\n" - " movl $1, %%eax\n" - "1:\n" - : "=a" (ret) : : "cx", "dx"); - return ret; -} - -static bool has_cpuid(void) -{ - return flag_is_changeable_p(X86_EFLAGS_ID); -} - -static bool has_mtrr(void) -{ - return cpuid_edx(0x00000001) & (1 << 12) ? true : false; -} - -static int build_vendor_name(char *vendor_name) -{ - struct cpuid_result result; - result = cpuid(0x00000000); - unsigned int *name_as_ints = (unsigned int *)vendor_name; - - name_as_ints[0] = result.ebx; - name_as_ints[1] = result.edx; - name_as_ints[2] = result.ecx; - - return result.eax; -} - -static void identify_cpu(struct cpu_device_id *cpu) -{ - char vendor_name[16]; - int i; - - vendor_name[0] = '\0'; /* Unset */ - cpu->device = 0; /* fix gcc 4.4.4 warning */ - - /* Find the id and vendor_name */ - if (!has_cpuid()) { - /* Its a 486 if we can modify the AC flag */ - if (flag_is_changeable_p(X86_EFLAGS_AC)) - cpu->device = 0x00000400; /* 486 */ - else - cpu->device = 0x00000300; /* 386 */ - if ((cpu->device == 0x00000400) && test_cyrix_52div()) { - memcpy(vendor_name, "CyrixInstead", 13); - /* If we ever care we can enable cpuid here */ - } - /* Detect NexGen with old hypercode */ - else if (deep_magic_nexgen_probe()) - memcpy(vendor_name, "NexGenDriven", 13); - } - if (has_cpuid()) { - int cpuid_level; - - cpuid_level = build_vendor_name(vendor_name); - vendor_name[12] = '\0'; - - /* Intel-defined flags: level 0x00000001 */ - if (cpuid_level >= 0x00000001) { - cpu->device = cpuid_eax(0x00000001); - } else { - /* Have CPUID level 0 only unheard of */ - cpu->device = 0x00000400; - } - } - cpu->vendor = X86_VENDOR_UNKNOWN; - for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { - if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { - cpu->vendor = x86_vendors[i].vendor; - break; - } - } -} - -static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) -{ - c->x86 = (tfms >> 8) & 0xf; - c->x86_model = (tfms >> 4) & 0xf; - c->x86_mask = tfms & 0xf; - if (c->x86 == 0xf) - c->x86 += (tfms >> 20) & 0xff; - if (c->x86 >= 0x6) - c->x86_model += ((tfms >> 16) & 0xF) << 4; -} - -u32 cpu_get_family_model(void) -{ - return gd->arch.x86_device & 0x0fff0ff0; -} - -u32 cpu_get_stepping(void) -{ - return gd->arch.x86_mask; -} - -int x86_cpu_init_f(void) -{ - const u32 em_rst = ~X86_CR0_EM; - const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; - - if (ll_boot_init()) { - /* initialize FPU, reset EM, set MP and NE */ - asm ("fninit\n" \ - "movl %%cr0, %%eax\n" \ - "andl %0, %%eax\n" \ - "orl %1, %%eax\n" \ - "movl %%eax, %%cr0\n" \ - : : "i" (em_rst), "i" (mp_ne_set) : "eax"); - } - - /* identify CPU via cpuid and store the decoded info into gd->arch */ - if (has_cpuid()) { - struct cpu_device_id cpu; - struct cpuinfo_x86 c; - - identify_cpu(&cpu); - get_fms(&c, cpu.device); - gd->arch.x86 = c.x86; - gd->arch.x86_vendor = cpu.vendor; - gd->arch.x86_model = c.x86_model; - gd->arch.x86_mask = c.x86_mask; - gd->arch.x86_device = cpu.device; - - gd->arch.has_mtrr = has_mtrr(); - } - /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ - gd->pci_ram_top = 0x80000000U; - - /* Configure fixed range MTRRs for some legacy regions */ - if (gd->arch.has_mtrr) { - u64 mtrr_cap; - - mtrr_cap = native_read_msr(MTRR_CAP_MSR); - if (mtrr_cap & MTRR_CAP_FIX) { - /* Mark the VGA RAM area as uncacheable */ - native_write_msr(MTRR_FIX_16K_A0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), - MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); - - /* - * Mark the PCI ROM area as cacheable to improve ROM - * execution performance. - */ - native_write_msr(MTRR_FIX_4K_C0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_C8000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_D0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_D8000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - - /* Enable the fixed range MTRRs */ - msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); - } - } - -#ifdef CONFIG_I8254_TIMER - /* Set up the i8254 timer if required */ - i8254_init(); -#endif - - return 0; -} - -void x86_enable_caches(void) -{ - unsigned long cr0; - - cr0 = read_cr0(); - cr0 &= ~(X86_CR0_NW | X86_CR0_CD); - write_cr0(cr0); - wbinvd(); -} -void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); - -void x86_disable_caches(void) -{ - unsigned long cr0; - - cr0 = read_cr0(); - cr0 |= X86_CR0_NW | X86_CR0_CD; - wbinvd(); - write_cr0(cr0); - wbinvd(); -} -void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); - int x86_init_cache(void) { enable_caches(); @@ -483,11 +105,6 @@ void x86_full_reset(void) outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); }

-int dcache_status(void) -{ - return !(read_cr0() & X86_CR0_CD); -} - /* Define these functions to allow ehch-hcd to function */ void flush_dcache_range(unsigned long start, unsigned long stop) { @@ -520,57 +137,6 @@ int icache_status(void) return 1; }

-void cpu_enable_paging_pae(ulong cr3) -{ - __asm__ __volatile__( - /* Load the page table address */ - "movl %0, %%cr3\n" - /* Enable pae */ - "movl %%cr4, %%eax\n" - "orl $0x00000020, %%eax\n" - "movl %%eax, %%cr4\n" - /* Enable paging */ - "movl %%cr0, %%eax\n" - "orl $0x80000000, %%eax\n" - "movl %%eax, %%cr0\n" - : - : "r" (cr3) - : "eax"); -} - -void cpu_disable_paging_pae(void) -{ - /* Turn off paging */ - __asm__ __volatile__ ( - /* Disable paging */ - "movl %%cr0, %%eax\n" - "andl $0x7fffffff, %%eax\n" - "movl %%eax, %%cr0\n" - /* Disable pae */ - "movl %%cr4, %%eax\n" - "andl $0xffffffdf, %%eax\n" - "movl %%eax, %%cr4\n" - : - : - : "eax"); -} - -static bool can_detect_long_mode(void) -{ - return cpuid_eax(0x80000000) > 0x80000000UL; -} - -static bool has_long_mode(void) -{ - return cpuid_edx(0x80000001) & (1 << 29) ? true : false; -} - -int cpu_has_64bit(void) -{ - return has_cpuid() && can_detect_long_mode() && - has_long_mode(); -} - const char *cpu_vendor_name(int vendor) { const char *name; @@ -616,46 +182,6 @@ int default_print_cpuinfo(void) return 0; }

-#define PAGETABLE_SIZE (6 * 4096) - -/** - * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode - * - * @pgtable: Pointer to a 24iKB block of memory - */ -static void build_pagetable(uint32_t *pgtable) -{ - uint i; - - memset(pgtable, '\0', PAGETABLE_SIZE); - - /* Level 4 needs a single entry */ - pgtable[0] = (ulong)&pgtable[1024] + 7; - - /* Level 3 has one 64-bit entry for each GiB of memory */ - for (i = 0; i < 4; i++) - pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7; - - /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ - for (i = 0; i < 2048; i++) - pgtable[2048 + i * 2] = 0x183 + (i << 21UL); -} - -int cpu_jump_to_64bit(ulong setup_base, ulong target) -{ - uint32_t *pgtable; - - pgtable = memalign(4096, PAGETABLE_SIZE); - if (!pgtable) - return -ENOMEM; - - build_pagetable(pgtable); - cpu_call64((ulong)pgtable, setup_base, target); - free(pgtable); - - return -EFAULT; -} - void show_boot_progress(int val) { outb(val, POST_PORT); @@ -680,36 +206,6 @@ int last_stage_init(void) } #endif

-#ifdef CONFIG_SMP -static int enable_smis(struct udevice *cpu, void *unused) -{ - return 0; -} - -static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), - /* Wait for APs to finish initialization before proceeding */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), -}; - -static int x86_mp_init(void) -{ - struct mp_params mp_params; - - mp_params.parallel_microcode_load = 0, - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = 0; - - if (mp_init(&mp_params)) { - printf("Warning: MP init failure\n"); - return -EIO; - } - - return 0; -} -#endif - static int x86_init_cpus(void) { #ifdef CONFIG_SMP diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile new file mode 100644 index 0000000..d336495 --- /dev/null +++ b/arch/x86/cpu/i386/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Google, Inc +# Written by Simon Glass sjg@chromium.org +# + +obj-y += cpu.o +obj-y += interrupt.o diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c new file mode 100644 index 0000000..09a5b91 --- /dev/null +++ b/arch/x86/cpu/i386/cpu.c @@ -0,0 +1,534 @@ +/* + * (C) Copyright 2008-2011 + * Graeme Russ, graeme.russ@gmail.com + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Part of this file is adapted from coreboot + * src/arch/x86/lib/cpu.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/control_regs.h> +#include <asm/cpu.h> +#include <asm/mp.h> +#include <asm/msr.h> +#include <asm/mtrr.h> +#include <asm/processor-flags.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Constructor for a conventional segment GDT (or LDT) entry + * This is a macro so it can be used in initialisers + */ +#define GDT_ENTRY(flags, base, limit) \ + ((((base) & 0xff000000ULL) << (56-24)) | \ + (((flags) & 0x0000f0ffULL) << 40) | \ + (((limit) & 0x000f0000ULL) << (48-16)) | \ + (((base) & 0x00ffffffULL) << 16) | \ + (((limit) & 0x0000ffffULL))) + +struct gdt_ptr { + u16 len; + u32 ptr; +} __packed; + +struct cpu_device_id { + unsigned vendor; + unsigned device; +}; + +struct cpuinfo_x86 { + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; +}; + +/* + * List of cpu vendor strings along with their normalized + * id values. + */ +static const struct { + int vendor; + const char *name; +} x86_vendors[] = { + { X86_VENDOR_INTEL, "GenuineIntel", }, + { X86_VENDOR_CYRIX, "CyrixInstead", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_UMC, "UMC UMC UMC ", }, + { X86_VENDOR_NEXGEN, "NexGenDriven", }, + { X86_VENDOR_CENTAUR, "CentaurHauls", }, + { X86_VENDOR_RISE, "RiseRiseRise", }, + { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, + { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, + { X86_VENDOR_NSC, "Geode by NSC", }, + { X86_VENDOR_SIS, "SiS SiS SiS ", }, +}; + +static void load_ds(u32 segment) +{ + asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_es(u32 segment) +{ + asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_fs(u32 segment) +{ + asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_gs(u32 segment) +{ + asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_ss(u32 segment) +{ + asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_gdt(const u64 *boot_gdt, u16 num_entries) +{ + struct gdt_ptr gdt; + + gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; + gdt.ptr = (ulong)boot_gdt; + + asm volatile("lgdtl %0\n" : : "m" (gdt)); +} + +void arch_setup_gd(gd_t *new_gd) +{ + u64 *gdt_addr; + + gdt_addr = new_gd->arch.gdt; + + /* + * CS: code, read/execute, 4 GB, base 0 + * + * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS + */ + gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); + + /* DS: data, read/write, 4 GB, base 0 */ + gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); + + /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ + new_gd->arch.gd_addr = new_gd; + gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, + (ulong)&new_gd->arch.gd_addr, 0xfffff); + + /* 16-bit CS: code, read/execute, 64 kB, base 0 */ + gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); + + /* 16-bit DS: data, read/write, 64 kB, base 0 */ + gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); + + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); + + load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); + load_ds(X86_GDT_ENTRY_32BIT_DS); + load_es(X86_GDT_ENTRY_32BIT_DS); + load_gs(X86_GDT_ENTRY_32BIT_DS); + load_ss(X86_GDT_ENTRY_32BIT_DS); + load_fs(X86_GDT_ENTRY_32BIT_FS); +} + +#ifdef CONFIG_HAVE_FSP +/* + * Setup FSP execution environment GDT + * + * Per Intel FSP external architecture specification, before calling any FSP + * APIs, we need make sure the system is in flat 32-bit mode and both the code + * and data selectors should have full 4GB access range. Here we reuse the one + * we used in arch/x86/cpu/start16.S, and reload the segement registers. + */ +void setup_fsp_gdt(void) +{ + load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); + load_ds(X86_GDT_ENTRY_32BIT_DS); + load_ss(X86_GDT_ENTRY_32BIT_DS); + load_es(X86_GDT_ENTRY_32BIT_DS); + load_fs(X86_GDT_ENTRY_32BIT_DS); + load_gs(X86_GDT_ENTRY_32BIT_DS); +} +#endif + +/* + * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected + * by the fact that they preserve the flags across the division of 5/2. + * PII and PPro exhibit this behavior too, but they have cpuid available. + */ + +/* + * Perform the Cyrix 5/2 test. A Cyrix won't change + * the flags, while other 486 chips will. + */ +static inline int test_cyrix_52div(void) +{ + unsigned int test; + + __asm__ __volatile__( + "sahf\n\t" /* clear flags (%eax = 0x0005) */ + "div %b2\n\t" /* divide 5 by 2 */ + "lahf" /* store flags into %ah */ + : "=a" (test) + : "0" (5), "q" (2) + : "cc"); + + /* AH is 0x02 on Cyrix after the divide.. */ + return (unsigned char) (test >> 8) == 0x02; +} + +/* + * Detect a NexGen CPU running without BIOS hypercode new enough + * to have CPUID. (Thanks to Herbert Oppmann) + */ +static int deep_magic_nexgen_probe(void) +{ + int ret; + + __asm__ __volatile__ ( + " movw $0x5555, %%ax\n" + " xorw %%dx,%%dx\n" + " movw $2, %%cx\n" + " divw %%cx\n" + " movl $0, %%eax\n" + " jnz 1f\n" + " movl $1, %%eax\n" + "1:\n" + : "=a" (ret) : : "cx", "dx"); + return ret; +} + +static bool has_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +static bool has_mtrr(void) +{ + return cpuid_edx(0x00000001) & (1 << 12) ? true : false; +} + +static int build_vendor_name(char *vendor_name) +{ + struct cpuid_result result; + result = cpuid(0x00000000); + unsigned int *name_as_ints = (unsigned int *)vendor_name; + + name_as_ints[0] = result.ebx; + name_as_ints[1] = result.edx; + name_as_ints[2] = result.ecx; + + return result.eax; +} + +static void identify_cpu(struct cpu_device_id *cpu) +{ + char vendor_name[16]; + int i; + + vendor_name[0] = '\0'; /* Unset */ + cpu->device = 0; /* fix gcc 4.4.4 warning */ + + /* Find the id and vendor_name */ + if (!has_cpuid()) { + /* Its a 486 if we can modify the AC flag */ + if (flag_is_changeable_p(X86_EFLAGS_AC)) + cpu->device = 0x00000400; /* 486 */ + else + cpu->device = 0x00000300; /* 386 */ + if ((cpu->device == 0x00000400) && test_cyrix_52div()) { + memcpy(vendor_name, "CyrixInstead", 13); + /* If we ever care we can enable cpuid here */ + } + /* Detect NexGen with old hypercode */ + else if (deep_magic_nexgen_probe()) + memcpy(vendor_name, "NexGenDriven", 13); + } + if (has_cpuid()) { + int cpuid_level; + + cpuid_level = build_vendor_name(vendor_name); + vendor_name[12] = '\0'; + + /* Intel-defined flags: level 0x00000001 */ + if (cpuid_level >= 0x00000001) { + cpu->device = cpuid_eax(0x00000001); + } else { + /* Have CPUID level 0 only unheard of */ + cpu->device = 0x00000400; + } + } + cpu->vendor = X86_VENDOR_UNKNOWN; + for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { + if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { + cpu->vendor = x86_vendors[i].vendor; + break; + } + } +} + +static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +{ + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4; +} + +u32 cpu_get_family_model(void) +{ + return gd->arch.x86_device & 0x0fff0ff0; +} + +u32 cpu_get_stepping(void) +{ + return gd->arch.x86_mask; +} + +int x86_cpu_init_f(void) +{ + const u32 em_rst = ~X86_CR0_EM; + const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; + + if (ll_boot_init()) { + /* initialize FPU, reset EM, set MP and NE */ + asm ("fninit\n" \ + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax"); + } + + /* identify CPU via cpuid and store the decoded info into gd->arch */ + if (has_cpuid()) { + struct cpu_device_id cpu; + struct cpuinfo_x86 c; + + identify_cpu(&cpu); + get_fms(&c, cpu.device); + gd->arch.x86 = c.x86; + gd->arch.x86_vendor = cpu.vendor; + gd->arch.x86_model = c.x86_model; + gd->arch.x86_mask = c.x86_mask; + gd->arch.x86_device = cpu.device; + + gd->arch.has_mtrr = has_mtrr(); + } + /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ + gd->pci_ram_top = 0x80000000U; + + /* Configure fixed range MTRRs for some legacy regions */ + if (gd->arch.has_mtrr) { + u64 mtrr_cap; + + mtrr_cap = native_read_msr(MTRR_CAP_MSR); + if (mtrr_cap & MTRR_CAP_FIX) { + /* Mark the VGA RAM area as uncacheable */ + native_write_msr(MTRR_FIX_16K_A0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* + * Mark the PCI ROM area as cacheable to improve ROM + * execution performance. + */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_C8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + + /* Enable the fixed range MTRRs */ + msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); + } + } + +#ifdef CONFIG_I8254_TIMER + /* Set up the i8254 timer if required */ + i8254_init(); +#endif + + return 0; +} + +void x86_enable_caches(void) +{ + unsigned long cr0; + + cr0 = read_cr0(); + cr0 &= ~(X86_CR0_NW | X86_CR0_CD); + write_cr0(cr0); + wbinvd(); +} +void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); + +void x86_disable_caches(void) +{ + unsigned long cr0; + + cr0 = read_cr0(); + cr0 |= X86_CR0_NW | X86_CR0_CD; + wbinvd(); + write_cr0(cr0); + wbinvd(); +} +void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); + +int dcache_status(void) +{ + return !(read_cr0() & X86_CR0_CD); +} + +void cpu_enable_paging_pae(ulong cr3) +{ + __asm__ __volatile__( + /* Load the page table address */ + "movl %0, %%cr3\n" + /* Enable pae */ + "movl %%cr4, %%eax\n" + "orl $0x00000020, %%eax\n" + "movl %%eax, %%cr4\n" + /* Enable paging */ + "movl %%cr0, %%eax\n" + "orl $0x80000000, %%eax\n" + "movl %%eax, %%cr0\n" + : + : "r" (cr3) + : "eax"); +} + +void cpu_disable_paging_pae(void) +{ + /* Turn off paging */ + __asm__ __volatile__ ( + /* Disable paging */ + "movl %%cr0, %%eax\n" + "andl $0x7fffffff, %%eax\n" + "movl %%eax, %%cr0\n" + /* Disable pae */ + "movl %%cr4, %%eax\n" + "andl $0xffffffdf, %%eax\n" + "movl %%eax, %%cr4\n" + : + : + : "eax"); +} + +static bool can_detect_long_mode(void) +{ + return cpuid_eax(0x80000000) > 0x80000000UL; +} + +static bool has_long_mode(void) +{ + return cpuid_edx(0x80000001) & (1 << 29) ? true : false; +} + +int cpu_has_64bit(void) +{ + return has_cpuid() && can_detect_long_mode() && + has_long_mode(); +} + +#define PAGETABLE_SIZE (6 * 4096) + +/** + * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode + * + * @pgtable: Pointer to a 24iKB block of memory + */ +static void build_pagetable(uint32_t *pgtable) +{ + uint i; + + memset(pgtable, '\0', PAGETABLE_SIZE); + + /* Level 4 needs a single entry */ + pgtable[0] = (ulong)&pgtable[1024] + 7; + + /* Level 3 has one 64-bit entry for each GiB of memory */ + for (i = 0; i < 4; i++) + pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7; + + /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ + for (i = 0; i < 2048; i++) + pgtable[2048 + i * 2] = 0x183 + (i << 21UL); +} + +int cpu_jump_to_64bit(ulong setup_base, ulong target) +{ + uint32_t *pgtable; + + pgtable = memalign(4096, PAGETABLE_SIZE); + if (!pgtable) + return -ENOMEM; + + build_pagetable(pgtable); + cpu_call64((ulong)pgtable, setup_base, target); + free(pgtable); + + return -EFAULT; +} + +#ifdef CONFIG_SMP +static int enable_smis(struct udevice *cpu, void *unused) +{ + return 0; +} + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), + /* Wait for APs to finish initialization before proceeding */ + MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), +}; + +int x86_mp_init(void) +{ + struct mp_params mp_params; + + mp_params.parallel_microcode_load = 0, + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = 0; + + if (mp_init(&mp_params)) { + printf("Warning: MP init failure\n"); + return -EIO; + } + + return 0; +} +#endif diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/i386/interrupt.c similarity index 99% rename from arch/x86/cpu/interrupts.c rename to arch/x86/cpu/i386/interrupt.c index 5f6cdd3..8dfbb48 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -13,16 +13,12 @@

#include <common.h> #include <dm.h> -#include <asm/cache.h> #include <asm/control_regs.h> #include <asm/i8259.h> #include <asm/interrupt.h> #include <asm/io.h> #include <asm/lapic.h> -#include <asm/msr.h> #include <asm/processor-flags.h> -#include <asm/processor.h> -#include <asm/u-boot-x86.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 2e6c312..83b99dc 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -90,4 +90,7 @@ int mp_init(struct mp_params *params); /* Probes the CPU device */ int mp_init_cpu(struct udevice *cpu, void *unused);

+/* Set up additional CPUs */ +int x86_mp_init(void); + #endif /* _X86_MP_H_ */

There is not much needed at present, but set up a separate directory to put this code as it grows.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/Makefile | 4 +++- arch/x86/cpu/x86_64/Makefile | 6 ++++++ arch/x86/cpu/x86_64/cpu.c | 35 +++++++++++++++++++++++++++++++++++ arch/x86/cpu/x86_64/interrupts.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/x86_64/Makefile create mode 100644 arch/x86/cpu/x86_64/cpu.c create mode 100644 arch/x86/cpu/x86_64/interrupts.c

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 41ad481..7f89ff0 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -38,6 +38,8 @@ obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SMP) += sipi_vector.o obj-y += turbo.o

-ifeq ($(CONFIG_$(SPL_)X86_64),) +ifeq ($(CONFIG_$(SPL_)X86_64),y) +obj-y += x86_64/ +else obj-y += i386/ endif diff --git a/arch/x86/cpu/x86_64/Makefile b/arch/x86/cpu/x86_64/Makefile new file mode 100644 index 0000000..4b06386 --- /dev/null +++ b/arch/x86/cpu/x86_64/Makefile @@ -0,0 +1,6 @@ +# +# (C) Copyright 2016 Google, Inc +# Written by Simon Glass sjg@chromium.org +# + +obj-y += cpu.o interrupts.o diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c new file mode 100644 index 0000000..c1d3788 --- /dev/null +++ b/arch/x86/cpu/x86_64/cpu.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2016 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> + +int cpu_has_64bit(void) +{ + return true; +} + +void enable_caches(void) +{ + /* Not implemented */ +} + +void disable_caches(void) +{ + /* Not implemented */ +} + +int dcache_status(void) +{ + return true; +} + +int x86_mp_init(void) +{ + /* Not implemented */ + return 0; +} diff --git a/arch/x86/cpu/x86_64/interrupts.c b/arch/x86/cpu/x86_64/interrupts.c new file mode 100644 index 0000000..d814b6a --- /dev/null +++ b/arch/x86/cpu/x86_64/interrupts.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2016 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor-flags.h> + +void enable_interrupts(void) +{ + asm("sti\n"); +} + +int disable_interrupts(void) +{ + long flags; + + asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : ); + + return flags & X86_EFLAGS_IF; +} + +int interrupt_init(void) +{ + /* Nothing to do - this was already done in SPL */ + return 0; +} +

At present this is just an ordinary variable. We may consider making it a fixed register in the future.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/x86_64/cpu.c | 13 +++++++++++++ arch/x86/include/asm/global_data.h | 6 +++++- 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index c1d3788..da2ad11 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -8,6 +8,19 @@ #include <common.h> #include <debug_uart.h>

+DECLARE_GLOBAL_DATA_PTR; + +/* Global declaration of gd */ +struct global_data *global_data_ptr; + +void arch_setup_gd(gd_t *new_gd) +{ + global_data_ptr = new_gd; + + /* TODO(sjg@chromium.org): Why is this needed? */ + printch(' '); +} + int cpu_has_64bit(void) { return true; diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 7434f77..ce9e5cc 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -104,7 +104,7 @@ struct arch_global_data { #include <asm-generic/global_data.h>

#ifndef __ASSEMBLY__ -# ifdef CONFIG_EFI_APP +# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)

#define gd global_data_ptr

@@ -114,7 +114,11 @@ static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void) { gd_t *gd_ptr;

+#if CONFIG_IS_ENABLED(X86_64) + asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr)); +#else asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr)); +#endif

return gd_ptr; }

When SPL and U-Boot proper have different settings for this flag, we need to use the correct one. Fix this up in the interrupt code.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/i386/interrupt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index 8dfbb48..a058303 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -234,7 +234,7 @@ int disable_interrupts(void) { long flags;

-#ifdef CONFIG_X86_64 +#if CONFIG_IS_ENABLED(X86_64) asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : ); #else asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );

This needs a different image format from 32-bit x86, so add a new link script.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/config.mk | 6 ++++ arch/x86/cpu/u-boot-64.lds | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/x86/cpu/u-boot-64.lds

diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 1263221..4c99a35 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -15,3 +15,9 @@ LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE) LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" + +ifdef CONFIG_X86_64 +ifndef CONFIG_SPL_BUILD +LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds +endif +endif diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds new file mode 100644 index 0000000..718790c --- /dev/null +++ b/arch/x86/cpu/u-boot-64.lds @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") +OUTPUT_ARCH(i386:x86-64) +ENTRY(_start) + +SECTIONS +{ +#ifndef CONFIG_CMDLINE + /DISCARD/ : { *(.u_boot_list_2_cmd_*) } +#endif + + . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } + + . = ALIGN(4); + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = ALIGN(4); + .hash : { *(.hash*) } + + . = ALIGN(4); + .got : { *(.got*) } + + . = ALIGN(4); + __data_end = .; + __init_end = .; + + . = ALIGN(4); + .dynsym : { *(.dynsym*) } + + . = ALIGN(4); + __rel_dyn_start = .; + .rela.dyn : { + *(.rela*) + } + __rel_dyn_end = .; + . = ALIGN(4); + + .dynamic : { *(.dynamic) } + + . = ALIGN(4); + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + *(COM*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +}

If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/u-boot-spl.lds | 74 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/x86/cpu/u-boot-spl.lds

diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds new file mode 100644 index 0000000..8a38d58 --- /dev/null +++ b/arch/x86/cpu/u-boot-spl.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ +#ifndef CONFIG_CMDLINE + /DISCARD/ : { *(.u_boot_list_2_cmd_*) } +#endif + + . = CONFIG_SPL_TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } + + . = ALIGN(4); + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = ALIGN(4); + __data_end = .; + __init_end = .; + + _image_binary_end = .; + + . = 0x120000; + .bss (OVERLAY) : { + __bss_start = .; + *(.bss*) + *(COM*) + . = ALIGN(4); + __bss_end = .; + } + __bss_size = __bss_end - __bss_start; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + +#ifdef CONFIG_SPL_X86_16BIT_INIT + /* + * The following expressions place the 16-bit Real-Mode code and + * Reset Vector at the end of the Flash ROM + */ + . = START_16 - RESET_SEG_START; + .start16 : AT (START_16) { + KEEP(*(.start16)); + } + + . = RESET_VEC_LOC - RESET_SEG_START; + .resetvec : AT (RESET_VEC_LOC) { + KEEP(*(.resetvec)); + } +#endif + +}

When SPL is used we need to build the 16-bit start-up code. Add Makefile rules to handle this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

scripts/Makefile.spl | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 1dd0d50..f68a94b 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -180,6 +180,8 @@ ifeq ($(CONFIG_SYS_SOC),"at91") ALL-y += boot.bin endif

+ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin + ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin

@@ -264,11 +266,16 @@ endif quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@

-OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary +OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \ + $(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec)

$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE $(call if_changed,objcopy)

+OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j .start16 -j .resetvec +$(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE + $(call if_changed,objcopy) + LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)

Remove the very old x86 code and add support for 64-bit.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/byteorder.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h index 7dfeb8b..a2d1fd8 100644 --- a/arch/x86/include/asm/byteorder.h +++ b/arch/x86/include/asm/byteorder.h @@ -8,24 +8,25 @@

static __inline__ __u32 ___arch__swab32(__u32 x) { -#ifdef CONFIG_X86_BSWAP __asm__("bswap %0" : "=r" (x) : "0" (x)); -#else - __asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */ - "rorl $16,%0\n\t" /* swap words */ - "xchgb %b0,%h0" /* swap higher bytes */ - :"=q" (x) - : "0" (x)); -#endif + return x; }

+#define _constant_swab16(x) ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8))) + static __inline__ __u16 ___arch__swab16(__u16 x) { +#if CONFIG_IS_ENABLED(X86_64) + return _constant_swab16(x); +#else __asm__("xchgb %b0,%h0" /* swap bytes */ \ : "=q" (x) \ : "0" (x)); \ return x; +#endif }

#define __arch__swab32(x) ___arch__swab32(x)

This doesn't build at present and is not used in a 64-bit build. Disable it for now.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/cpu.h | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 540024a..b408515 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -159,6 +159,8 @@ static inline unsigned int cpuid_edx(unsigned int op) return edx; }

+#if !CONFIG_IS_ENABLED(X86_64) + /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -179,6 +181,7 @@ static inline int flag_is_changeable_p(uint32_t flag) : "ir" (flag)); return ((f1^f2) & flag) != 0; } +#endif

static inline void mfence(void) {

Adjust types as needed to support 64-bit compilation.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/posix_types.h | 5 +++++ arch/x86/include/asm/types.h | 5 +++++ 2 files changed, 10 insertions(+)

diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 5529f32..717f6cb 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h @@ -16,8 +16,13 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; +#if CONFIG_IS_ENABLED(X86_64) +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +#else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; +#endif typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index 880dcb4..a47e581 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -44,7 +44,12 @@ typedef __INT64_TYPE__ s64; typedef __UINT64_TYPE__ u64; #endif

+#if CONFIG_IS_ENABLED(X86_64) +#define BITS_PER_LONG 64 +#else #define BITS_PER_LONG 32 +#endif + /* Dma addresses are 32-bits wide. */

typedef u32 dma_addr_t;

Some files cannot be built with 64-bit and mostly don't make sense in that context. Disable them.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/Makefile | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index f0135a7..6889df3 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -20,11 +20,13 @@ endif

obj-y += cpu.o cpu_x86.o

+ifndef CONFIG_$(SPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) AFLAGS_call32.o := -fpic -fshort-wchar

extra-y += call32.o +endif

obj-y += intel_common/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ @@ -35,11 +37,16 @@ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ -obj-y += irq.o lapic.o ioapic.o +obj-y += lapic.o ioapic.o +ifndef CONFIG_$(SPL_)X86_64 +obj-y += irq.o obj-$(CONFIG_SMP) += mp_init.o +endif obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o +ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o +endif obj-y += turbo.o

ifeq ($(CONFIG_$(SPL_)X86_64),y)

These cannot be built in this mode, so drop them.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/Makefile | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index e2dce06..c4f6e79 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -48,7 +48,9 @@ OBJCOPYFLAGS := --prefix-symbols=__normal_ $(obj)/lib.a: $(NORMAL_LIBGCC) FORCE $(call if_changed,objcopy)

+ifeq ($(CONFIG_$(SPL_)X86_64),) obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o +endif

ifneq ($(CONFIG_EFI_STUB),)

@@ -68,5 +70,7 @@ extra-$(CONFIG_EFI_STUB_64BIT) += crt0_x86_64_efi.o reloc_x86_64_efi.o endif

ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO),) +ifeq ($(CONFIG_$(SPL_)X86_64),) extra-y += $(EFI_CRT0) $(EFI_RELOC) endif +endif

Booting into linux from 64-bit U-Boot is not yet supported. Avoid bringing in the bootm code until it is implemented.

Of course 32-bit U-Boot still supported booting into both 32- and 64-bit kernels.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/Makefile | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index c4f6e79..71ca112 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -10,7 +10,9 @@ obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o +endif obj-y += cmd_boot.o obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-$(CONFIG_EFI) += efi/ @@ -37,7 +39,9 @@ ifndef CONFIG_QEMU obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ZBOOT) += zimage.o +endif obj-$(CONFIG_HAVE_FSP) += fsp/ obj-$(CONFIG_SPL_BUILD) += spl.o

This is not currently supported, so drop the code.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/interrupts.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index dd08402..d3ae6d9 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -33,6 +33,8 @@ #include <common.h> #include <asm/interrupt.h>

+#if !CONFIG_IS_ENABLED(X86_64) + struct irq_action { interrupt_handler_t *handler; void *arg; @@ -118,10 +120,12 @@ void do_irq(int hw_irq) } } } +#endif

#if defined(CONFIG_CMD_IRQ) int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#if !CONFIG_IS_ENABLED(X86_64) int irq;

printf("Spurious IRQ: %u, last unknown IRQ: %d\n", @@ -139,6 +143,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) irq_handlers[irq].count); } } +#endif

return 0; }

Add a rough function to handle jumping from 32-bit SPL to 64-bit U-Boot. This still needs work to clean it up.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/call64.S | 3 +++ arch/x86/cpu/i386/cpu.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/cpu.h | 9 +++++++ 3 files changed, 77 insertions(+)

diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S index 08dc473..970c461 100644 --- a/arch/x86/cpu/call64.S +++ b/arch/x86/cpu/call64.S @@ -81,6 +81,9 @@ lret_target: jmp *%eax /* Jump to the 64-bit target */

.data + .align 16 + .globl gdt64 +gdt64: gdt: .word gdt_end - gdt - 1 .long gdt /* Fixed up by code above */ diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 09a5b91..ddbf367 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -503,6 +503,71 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target) return -EFAULT; }

+/* + * Jump from SPL to U-Boot + * + * This function is work-in-progress with many issues to resolve. + * + * It works by setting up several regions: + * ptr - a place to put the code that jumps into 64-bit mode + * gdt - a place to put the global descriptor table + * pgtable - a place to put the page tables + * + * The cpu_call64() code is copied from ROM and then manually patched so that + * it has the correct GDT address in RAM. U-Boot is copied from ROM into + * its pre-relocation address. Then we jump to the cpu_call64() code in RAM, + * which changes to 64-bit mode and starts U-Boot. + */ +int cpu_jump_to_64bit_uboot(ulong target) +{ + typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target); + void target64(void); + uint32_t *pgtable; + func_t func; + + /* TODO(sjg@chromium.org): Find a better place for this */ + pgtable = (uint32_t *)0x1000000; + if (!pgtable) + return -ENOMEM; + + build_pagetable(pgtable); + + /* TODO(sjg@chromium.org): Find a better place for this */ + char *ptr = (char *)0x3000000; + char *gdt = (char *)0x3100000; + + extern char gdt64[]; + + memcpy(ptr, cpu_call64, 0x1000); + memcpy(gdt, gdt64, 0x100); + + /* + * TODO(sjg@chromium.org): This manually inserts the pointers into + * the code. Tidy this up to avoid this. + */ + func = (func_t)ptr; + ulong ofs = (ulong)cpu_call64 - (ulong)ptr; + *(ulong *)(ptr + 7) = (ulong)gdt; + *(ulong *)(ptr + 0xc) = (ulong)gdt + 2; + *(ulong *)(ptr + 0x13) = (ulong)gdt; + *(ulong *)(ptr + 0x117 - 0xd4) -= ofs; + + /* + * Copy U-Boot from ROM + * TODO(sjg@chromium.org): Figure out a way to get the text base + * correctly here, and in the device-tree binman definition. + * + * Also consider using FIT so we get the correct image length and + * parameters. + */ + memcpy((char *)target, (char *)0xfff00000, 0x100000); + + /* Jump to U-Boot */ + func((ulong)pgtable, 0, (ulong)target); + + return -EFAULT; +} + #ifdef CONFIG_SMP static int enable_smis(struct udevice *cpu, void *unused) { diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index b408515..c651f2f 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -264,6 +264,15 @@ void cpu_call32(ulong code_seg32, ulong target, ulong table); int cpu_jump_to_64bit(ulong setup_base, ulong target);

/** + * cpu_jump_to_64bit_uboot() - special function to jump from SPL to U-Boot + * + * This handles calling from 32-bit SPL to 64-bit U-Boot. + * + * @target: Address of U-Boot in RAM + */ +int cpu_jump_to_64bit_uboot(ulong target); + +/** * cpu_get_family_model() - Get the family and model for the CPU * * @return the CPU ID masked with 0x0fff0ff0

To avoid using BSS in SPL before SDRAM is set up, move this field to global_data.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/irq.c | 12 +++++------- arch/x86/include/asm/global_data.h | 1 + 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index e3e928b..442d373 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -17,8 +17,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static struct irq_routing_table *pirq_routing_table; - bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) { struct irq_router *priv = dev_get_priv(dev); @@ -219,7 +217,7 @@ static int create_pirq_routing_table(struct udevice *dev) /* Fix up the table checksum */ rt->checksum = table_compute_checksum(rt, rt->size);

- pirq_routing_table = rt; + gd->arch.pirq_routing_table = rt;

return 0; } @@ -250,8 +248,8 @@ int irq_router_common_init(struct udevice *dev) return ret; } /* Route PIRQ */ - pirq_route_irqs(dev, pirq_routing_table->slots, - get_irq_slot_count(pirq_routing_table)); + pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots, + get_irq_slot_count(gd->arch.pirq_routing_table));

if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) irq_enable_sci(dev); @@ -266,10 +264,10 @@ int irq_router_probe(struct udevice *dev)

ulong write_pirq_routing_table(ulong addr) { - if (!pirq_routing_table) + if (!gd->arch.pirq_routing_table) return addr;

- return copy_pirq_routing_table(addr, pirq_routing_table); + return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); }

static const struct udevice_id irq_router_ids[] = { diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index ce9e5cc..e24cee7 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,7 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ + struct irq_routing_table *pirq_routing_table; #ifdef CONFIG_SEABIOS u32 high_table_ptr; u32 high_table_limit;

To avoid using BSS in SPL before SDRAM is set up, move this field to global_data.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/turbo.c | 8 ++++---- arch/x86/include/asm/global_data.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index 254d0de..bbd255e 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -12,6 +12,8 @@ #include <asm/processor.h> #include <asm/turbo.h>

+DECLARE_GLOBAL_DATA_PTR; + #if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED static inline int get_global_turbo_state(void) { @@ -22,16 +24,14 @@ static inline void set_global_turbo_state(int state) { } #else -static int g_turbo_state = TURBO_UNKNOWN; - static inline int get_global_turbo_state(void) { - return g_turbo_state; + return gd->arch.turbo_state; }

static inline void set_global_turbo_state(int state) { - g_turbo_state = state; + gd->arch.turbo_state = state; } #endif

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index e24cee7..0fadfc6 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,7 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ + int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; #ifdef CONFIG_SEABIOS u32 high_table_ptr;

Update config.mk settings to support both 32-bit and 64-bit U-Boot.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/config.mk | 30 ++++++++++++++++++++++++++++-- arch/x86/cpu/config.mk | 2 -- 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 03c71f7..13c2660 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -15,11 +15,25 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \

PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm + +ifdef CONFIG_SPL_BUILD +IS_32BIT := y +else +ifndef CONFIG_X86_64 +IS_32BIT := y +endif +endif + +ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 +else +PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common +endif

PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden

-PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions -m elf_i386 +PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions +PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)

LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 @@ -31,7 +45,9 @@ LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \ -j .rel -j .rela -j .reloc

+ifeq ($(IS_32BIT),y) CFLAGS_NON_EFI := -mregparm=3 +endif CFLAGS_EFI := -fpic -fshort-wchar

ifeq ($(CONFIG_EFI_STUB_64BIT),) @@ -62,8 +78,18 @@ else

PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI) PLATFORM_LDFLAGS += --emit-relocs -LDFLAGS_FINAL += --gc-sections -pie +LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie) + +endif

+ifdef CONFIG_X86_64 +ifndef CONFIG_SPL_BUILD +PLATFORM_CPPFLAGS += -D__x86_64__ +else +PLATFORM_CPPFLAGS += -D__I386__ +endif +else +PLATFORM_CPPFLAGS += -D__I386__ endif

ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO),) diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 4c99a35..b519f43 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -7,8 +7,6 @@

CROSS_COMPILE ?= i386-linux-

-PLATFORM_CPPFLAGS += -D__I386__ - # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START) LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE)

Add a new link config which uses 64-bit U-Boot. This is not fully functional but is it a start. Missing features:

- SDRAM sizing - Booting linux - EFI support - SCSI device init (and others)

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Drop patch 'video: Use ulong for video frame buffer address' - Add a new 64-bit link config instead of changing the existing one

board/google/Kconfig | 7 +++ board/google/chromebook_link/Kconfig | 2 +- board/google/chromebook_link/MAINTAINERS | 7 +++ configs/chromebook_link64_defconfig | 94 ++++++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+), 1 deletion(-) create mode 100644 configs/chromebook_link64_defconfig

diff --git a/board/google/Kconfig b/board/google/Kconfig index 7ba73a2..e56c026 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -22,6 +22,13 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.

+config TARGET_CHROMEBOOK_LINK64 + bool "Chromebook link 64-bit" + help + This is the Chromebook Pixel released in 2013. With this config + U-Boot is built as a 64-bit binary. This allows testing while this + feature is being completed. + config TARGET_CHROMEBOX_PANTHER bool "Chromebox panther (not available)" select n diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 5c57945..8999b58 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -1,4 +1,4 @@ -if TARGET_CHROMEBOOK_LINK +if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64

config SYS_BOARD default "chromebook_link" diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS index bc253a2..e7aef53 100644 --- a/board/google/chromebook_link/MAINTAINERS +++ b/board/google/chromebook_link/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/google/chromebook_link/ F: include/configs/chromebook_link.h F: configs/chromebook_link_defconfig + +CHROMEBOOK LINK 64-bit BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link64_defconfig diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig new file mode 100644 index 0000000..1380c5e --- /dev/null +++ b/configs/chromebook_link64_defconfig @@ -0,0 +1,94 @@ +CONFIG_X86=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_X86_RUN_64BIT=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_HAVE_MRC=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_CPU_SUPPORT=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_PCI_SUPPORT=y +CONFIG_SPL_PCH_SUPPORT=y +CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_TIMER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_INTEL=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IVYBRIDGE_IGD=y +CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_CFB_CONSOLE=y +CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_TPM=y +CONFIG_EFI_LOADER=y +CONFIG_CMD_BOOTEFI=y