[U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings
From: Jimmy Zhang jimmzhang@nvidia.com
The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly.
Signed-off-by: Jimmy Zhang jimmzhang@nvidia.com Reviewed-by: Tom Warren twarren@nvidia.com Signed-off-by: Thierry Reding treding@nvidia.com --- Changes in v2: - clean up table layout and comments
arch/arm/cpu/arm720t/tegra-common/cpu.c | 83 +++++++++++++++++++++++---------- 1 file changed, 59 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611..aa1e04f 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -49,33 +49,68 @@ int get_num_cpus(void) * Timing tables for each SOC for all four oscillator options. */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* T20: 1 GHz */ - /* n, m, p, cpcon */ - {{ 1000, 13, 0, 12}, /* OSC 13M */ - { 625, 12, 0, 8}, /* OSC 19.2M */ - { 1000, 12, 0, 12}, /* OSC 12M */ - { 1000, 26, 0, 12}, /* OSC 26M */ + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T25: 1.2 GHz */ - {{ 923, 10, 0, 12}, - { 750, 12, 0, 8}, - { 600, 6, 0, 12}, - { 600, 13, 0, 12}, + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T30: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 700, 6, 0, 8}, - { 700, 13, 0, 8}, + /* + * T30: 1.4 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ + { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, - - /* T114: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 696, 12, 0, 8}, - { 700, 13, 0, 8}, + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, };
PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it.
Signed-off-by: Thierry Reding treding@nvidia.com --- Changes in v2: - new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index aa1e04f..5ab2ebf 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { + int chip = tegra_get_chip(); u32 reg;
/* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */ - reg = (cpcon << PLL_CPCON_SHIFT); + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) + reg = (cpcon << PLL_CPCON_SHIFT);
/* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600)
Thierry,
-----Original Message----- From: Thierry Reding [mailto:thierry.reding@gmail.com] Sent: Monday, September 23, 2013 1:08 PM To: Tom Warren Cc: u-boot@lists.denx.de Subject: [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it.
Signed-off-by: Thierry Reding treding@nvidia.com
Changes in v2:
- new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index aa1e04f..5ab2ebf 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) {
int chip = tegra_get_chip(); u32 reg;
/* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@ int
pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
- reg = (cpcon << PLL_CPCON_SHIFT);
- if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
reg = (cpcon << PLL_CPCON_SHIFT);
If it's not a T20/T30, reg is still set to the PLLX_BASE setting from above. It'll then be written to PLLX_MISC w/bad bits below. You need to set a default, or read pllx_misc first.
/* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600) -- 1.8.4
-- Nvpublic
On Mon, Sep 30, 2013 at 02:25:57PM -0700, Tom Warren wrote:
Thierry,
-----Original Message----- From: Thierry Reding [mailto:thierry.reding@gmail.com] Sent: Monday, September 23, 2013 1:08 PM To: Tom Warren Cc: u-boot@lists.denx.de Subject: [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it.
Signed-off-by: Thierry Reding treding@nvidia.com
Changes in v2:
- new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index aa1e04f..5ab2ebf 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) {
int chip = tegra_get_chip(); u32 reg;
/* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@ int
pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
- reg = (cpcon << PLL_CPCON_SHIFT);
- if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
reg = (cpcon << PLL_CPCON_SHIFT);If it's not a T20/T30, reg is still set to the PLLX_BASE setting from above. It'll then be written to PLLX_MISC w/bad bits below. You need to set a default, or read pllx_misc first.
Ugh... you're right of course. Sent a v3 with reg = 0 in the else branch.
Thanks, Thierry
Thierry,
Your 3 patches (Avionics maintainer change, as well as the 2-part T114 MNP/CPCON changes) have been applied to u-boot-tegra/next, built, and tested on Dalmore.
New code (rebased against ARM/master) is available in both u-boot-tegra/next and /master, in anticipation of a pull request to u-boot-arm/master RSN.
Thanks,
Tom
On Tue, Oct 1, 2013 at 8:06 AM, Thierry Reding thierry.reding@gmail.comwrote:
On Mon, Sep 30, 2013 at 02:25:57PM -0700, Tom Warren wrote:
Thierry,
-----Original Message----- From: Thierry Reding [mailto:thierry.reding@gmail.com] Sent: Monday, September 23, 2013 1:08 PM To: Tom Warren Cc: u-boot@lists.denx.de Subject: [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it.
Signed-off-by: Thierry Reding treding@nvidia.com
Changes in v2:
- new patch
arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index aa1e04f..5ab2ebf 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) {
int chip = tegra_get_chip(); u32 reg;
/* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@
int
pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
- reg = (cpcon << PLL_CPCON_SHIFT);
- if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
reg = (cpcon << PLL_CPCON_SHIFT);If it's not a T20/T30, reg is still set to the PLLX_BASE setting from
above. It'll then be written to PLLX_MISC w/bad bits below.
You need to set a default, or read pllx_misc first.
Ugh... you're right of course. Sent a v3 with reg = 0 in the else branch.
Thanks, Thierry
On 09/23/2013 02:07 PM, Thierry Reding wrote:
From: Jimmy Zhang jimmzhang@nvidia.com
The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly.
The series, Acked-by: Stephen Warren swarren@nvidia.com
participants (4)
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Stephen Warren -
Thierry Reding -
Tom Warren -
Tom Warren