Hello Stefano,

On 06/01/2015 01:15 PM, Stefano Babic wrote:

Hi Bhuvanchandra,

On 18/05/2015 15:06, Bhuvanchandra DV wrote:

...

Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees. Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com

configs/colibri_vf_dtb_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfig

diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig new file mode 100644 index 0000000..28ff1e9 --- /dev/null +++ b/configs/colibri_vf_dtb_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"

This patch is broken because NAND setup is missing and the board colibri_vf_dtp is not built.

Indeed, it is fixed with:

diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig index 28ff1e9..88ecbdc 100644 --- a/configs/colibri_vf_dtb_defconfig +++ b/configs/colibri_vf_dtb_defconfig @@ -4,3 +4,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_I CONFIG_DM=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y

Please add these to your patch and resubmit, thanks !

Will add this and resubmit the patchset.

Best regards, Stefano Babic

Best regards, Bhuvan

Add GPIO driver support to Freescale VF610

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com --- arch/arm/imx-common/iomux-v3.c | 26 +++++ arch/arm/include/asm/arch-vf610/gpio.h | 29 +++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + arch/arm/include/asm/imx-common/iomux-v3.h | 6 + drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/vybrid_gpio.c | 169 +++++++++++++++++++++++++++++ 7 files changed, 243 insertions(+) create mode 100644 arch/arm/include/asm/arch-vf610/gpio.h create mode 100644 drivers/gpio/vybrid_gpio.c

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index e88e6e2..7fb23dd 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit, reg |= (value << start_bit); writel(reg, base + group * 4); } + +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction) +{ + u32 reg; + /* + * Only on Vybrid the input/output buffer enable flags + * are part of the shared mux/conf register. + */ + reg = readl(base + (gpio << 2)); + + if (direction) + reg |= 0x2; + else + reg &= ~0x2; + + writel(reg, base + (gpio << 2)); +} + +void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state) +{ + *gpio_state = readl(base + (gpio << 2)) & + ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE); +} +#endif diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h new file mode 100644 index 0000000..622b8f0 --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/gpio.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; +}; + +struct vybrid_gpio_platdata { + unsigned int chip; + u32 base; + const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 2021981..7df3b1e 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -81,6 +81,11 @@ #define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) #define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100)

/* AIPS 1 */ #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index e0a49be..2581019 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, */ void imx_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction); +void imx_iomux_gpio_get_function(unsigned int gpio, + u32 *gpio_state); +#endif

/* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0840a30..0c43777 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT are specified using the device tree. But you can also have a number of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. + +config VYBRID_GPIO + bool "Vybrid GPIO driver" + depends on DM + default n + help + Say yes here to support Vybrid vf610 GPIOs. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ba9efe8..5864850 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o +obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c new file mode 100644 index 0000000..6eaf0a9 --- /dev/null +++ b/drivers/gpio/vybrid_gpio.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct vybrid_gpios { + unsigned int chip; + struct vybrid_gpio_regs *reg; +}; + +static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN); + + return 0; +} + +static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + gpio_set_value(gpio, value); + imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT); + + return 0; +} + +static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + return ((readl(&gpios->reg->gpio_pdir) & (1 << gpio))) ? 1 : 0; +} + +static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + if (value) + writel((1 << gpio), &gpios->reg->gpio_psor); + else + writel((1 << gpio), &gpios->reg->gpio_pcor); + + return 0; +} + +static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + u32 g_state = 0; + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + + imx_iomux_gpio_get_function(gpio, &g_state); + + if (((g_state & (0x07 << PAD_MUX_MODE_SHIFT)) >> PAD_MUX_MODE_SHIFT) > 0) + return GPIOF_FUNC; + if (g_state & PAD_CTL_OBE_ENABLE) + return GPIOF_OUTPUT; + if (g_state & PAD_CTL_IBE_ENABLE) + return GPIOF_INPUT; + if (!(g_state & PAD_CTL_OBE_IBE_ENABLE)) + return GPIOF_UNUSED; + + return GPIOF_UNKNOWN; +} + +static const struct dm_gpio_ops gpio_vybrid_ops = { + .direction_input = vybrid_gpio_direction_input, + .direction_output = vybrid_gpio_direction_output, + .get_value = vybrid_gpio_get_value, + .set_value = vybrid_gpio_set_value, + .get_function = vybrid_gpio_get_function, +}; + +static int vybrid_gpio_probe(struct udevice *dev) +{ + struct vybrid_gpios *gpios = dev_get_priv(dev); + struct vybrid_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = plat->port_name; + uc_priv->gpio_count = VYBRID_GPIO_COUNT; + gpios->reg = (struct vybrid_gpio_regs *)plat->base; + gpios->chip = plat->chip; + + return 0; +} + +static int vybrid_gpio_bind(struct udevice *dev) +{ + struct vybrid_gpio_platdata *plat = dev->platdata; + fdt_addr_t base_addr; + + if (plat) + return 0; + + base_addr = dev_get_addr(dev); + if (base_addr == FDT_ADDR_T_NONE) + return -ENODEV; + + /* + * TODO: + * When every board is converted to driver model and DT is + * supported, this can be done by auto-alloc feature, but + * not using calloc to alloc memory for platdata. + */ + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + plat->base = base_addr; + plat->chip = dev->req_seq; + plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL); + dev->platdata = plat; + + return 0; +} + +#ifndef CONFIG_OF_CONTROL +static const struct vybrid_gpio_platdata vybrid_gpio[] = { + {0, GPIO0_BASE_ADDR, "GPIO0 "}, + {1, GPIO1_BASE_ADDR, "GPIO1 "}, + {2, GPIO2_BASE_ADDR, "GPIO2 "}, + {3, GPIO3_BASE_ADDR, "GPIO3 "}, + {4, GPIO4_BASE_ADDR, "GPIO4 "}, +}; + +U_BOOT_DEVICES(vybrid_gpio) = { + { "gpio_vybrid", &vybrid_gpio[0] }, + { "gpio_vybrid", &vybrid_gpio[1] }, + { "gpio_vybrid", &vybrid_gpio[2] }, + { "gpio_vybrid", &vybrid_gpio[3] }, + { "gpio_vybrid", &vybrid_gpio[4] }, +}; +#endif + +static const struct udevice_id vybrid_gpio_ids[] = { + { .compatible = "fsl,vf610-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_vybrid) = { + .name = "gpio_vybrid", + .id = UCLASS_GPIO, + .ops = &gpio_vybrid_ops, + .probe = vybrid_gpio_probe, + .priv_auto_alloc_size = sizeof(struct vybrid_gpios), + .of_match = vybrid_gpio_ids, + .bind = vybrid_gpio_bind, +};

On 2015-06-01 10:51, Bhuvanchandra DV wrote:

Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs.

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com

arch/arm/include/asm/arch-vf610/iomux-vf610.h | 49 ++++++++++++++++++++++ board/toradex/colibri_vf/colibri_vf.c | 60 +++++++++++++++++++++++++++ 2 files changed, 109 insertions(+)

diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 9226e69..e22e3f9 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -32,22 +32,56 @@ #define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)

+#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \

• 		PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE)
  

enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),

• VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),

• VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -57,6 +91,8 @@ enum { VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),

• VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), @@ -66,13 +102,21 @@ enum { VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),

• VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), @@ -83,9 +127,14 @@ enum { VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),

• VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),

• VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),

• VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),

• VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL),

• VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0,

VF610_GPIO_PAD_CTRL), VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 31ebb19..e354c6d 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -146,6 +146,62 @@ static void setup_iomux_nfc(void) } #endif

+#ifdef CONFIG_VYBRID_GPIO +static void setup_iomux_gpio(void) +{

• static const iomux_v3_cfg_t gpio_pads[] = {

• VF610_PAD_PTA17__GPIO_7,
  

• VF610_PAD_PTA20__GPIO_10,
  

• VF610_PAD_PTA21__GPIO_11,
  

• VF610_PAD_PTA30__GPIO_20,
  

• VF610_PAD_PTA31__GPIO_21,
  

• VF610_PAD_PTB0__GPIO_22,
  

• VF610_PAD_PTB1__GPIO_23,
  

• VF610_PAD_PTB6__GPIO_28,
  

• VF610_PAD_PTB7__GPIO_29,
  

• VF610_PAD_PTB8__GPIO_30,
  

• VF610_PAD_PTB9__GPIO_31,
  

• VF610_PAD_PTB12__GPIO_34,
  

• VF610_PAD_PTB13__GPIO_35,
  

• VF610_PAD_PTB16__GPIO_38,
  

• VF610_PAD_PTB17__GPIO_39,
  

• VF610_PAD_PTB18__GPIO_40,
  

• VF610_PAD_PTB21__GPIO_43,
  

• VF610_PAD_PTB22__GPIO_44,
  

• VF610_PAD_PTC0__GPIO_45,
  

• VF610_PAD_PTC1__GPIO_46,
  

• VF610_PAD_PTC2__GPIO_47,
  

• VF610_PAD_PTC3__GPIO_48,
  

• VF610_PAD_PTC4__GPIO_49,
  

• VF610_PAD_PTC5__GPIO_50,
  

• VF610_PAD_PTC6__GPIO_51,
  

• VF610_PAD_PTC7__GPIO_52,
  

• VF610_PAD_PTC8__GPIO_53,
  

• VF610_PAD_PTD31__GPIO_63,
  

• VF610_PAD_PTD30__GPIO_64,
  

• VF610_PAD_PTD29__GPIO_65,
  

• VF610_PAD_PTD28__GPIO_66,
  

• VF610_PAD_PTD27__GPIO_67,
  

• VF610_PAD_PTD26__GPIO_68,
  

• VF610_PAD_PTD25__GPIO_69,
  

• VF610_PAD_PTD24__GPIO_70,
  

• VF610_PAD_PTD9__GPIO_88,
  

• VF610_PAD_PTD10__GPIO_89,
  

• VF610_PAD_PTD11__GPIO_90,
  

• VF610_PAD_PTD12__GPIO_91,
  

• VF610_PAD_PTD13__GPIO_92,
  

• VF610_PAD_PTB23__GPIO_93,
  

• VF610_PAD_PTB26__GPIO_96,
  

• VF610_PAD_PTB28__GPIO_98,
  

• VF610_PAD_PTC29__GPIO_102,
  

• VF610_PAD_PTC30__GPIO_103,
  

• VF610_PAD_PTA7__GPIO_134,
  

• };
• imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));

+} +#endif

#ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -304,6 +360,10 @@ int board_early_init_f(void) setup_iomux_nfc(); #endif

+#ifdef CONFIG_VYBRID_GPIO

• setup_iomux_gpio();

+#endif

• return 0;

}

Acked-by: Stefan Agner stefan@agner.ch

-- Stefan

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com --- arch/arm/cpu/armv7/vf610/generic.c | 7 +++++++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 3 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 1bb9b8e..05c401d 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -198,6 +198,11 @@ static u32 get_i2c_clk(void) return get_ipg_clk(); }

+static u32 get_dspi_clk(void) +{ + return get_ipg_clk(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_fec_clk(); case MXC_I2C_CLK: return get_i2c_clk(); + case MXC_DSPI_CLK: + return get_dspi_clk(); default: break; } diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 535adad..e5a5c6d 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -17,6 +17,7 @@ enum mxc_clock { MXC_ESDHC_CLK, MXC_FEC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, };

void enable_ocotp_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index bc6db2a..fdb45e9 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,8 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -206,6 +208,8 @@ struct anadig_reg { #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)

Add device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules. Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot.

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com --- arch/arm/dts/Makefile | 3 ++ arch/arm/dts/vf-colibri.dtsi | 21 +++++++++ arch/arm/dts/vf.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/vf500-colibri.dts | 18 ++++++++ arch/arm/dts/vf610-colibri.dts | 18 ++++++++ 5 files changed, 160 insertions(+) create mode 100644 arch/arm/dts/vf-colibri.dtsi create mode 100644 arch/arm/dts/vf.dtsi create mode 100644 arch/arm/dts/vf500-colibri.dts create mode 100644 arch/arm/dts/vf610-colibri.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 267fd17..55039df 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -130,6 +130,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb

+dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ + vf610-colibri.dtb + targets += $(dtb-y)

DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi new file mode 100644 index 0000000..7a8e9bee --- /dev/null +++ b/arch/arm/dts/vf-colibri.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include "vf.dtsi" + +&dspi1 { + status = "okay"; + bus-num = <1>; + + spi_cmd: sspi@0 { + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi new file mode 100644 index 0000000..78706e1 --- /dev/null +++ b/arch/arm/dts/vf.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +/include/ "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + spi0 = &dspi0; + spi1 = &dspi1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips0: aips-bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dspi0: dspi0@4002c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + num-cs = <5>; + status = "disabled"; + }; + + dspi1: dspi1@4002d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002d000 0x1000>; + num-cs = <5>; + status = "disabled"; + }; + + qspi0: quadspi@40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>; + status = "disabled"; + }; + + gpio0: gpio@40049000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff000 0x40>; + #gpio-cells = <2>; + }; + + gpio1: gpio@4004a000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff040 0x40>; + #gpio-cells = <2>; + }; + + gpio2: gpio@4004b000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff080 0x40>; + #gpio-cells = <2>; + }; + + gpio3: gpio@4004c000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff0c0 0x40>; + #gpio-cells = <2>; + }; + + gpio4: gpio@4004d000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff100 0x40>; + #gpio-cells = <2>; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + }; +}; diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts new file mode 100644 index 0000000..e383306 --- /dev/null +++ b/arch/arm/dts/vf500-colibri.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50"; + compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500"; +}; diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts new file mode 100644 index 0000000..63bb3f4 --- /dev/null +++ b/arch/arm/dts/vf610-colibri.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61"; + compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610"; +};

On 2015-06-01 10:51, Bhuvanchandra DV wrote:

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com

include/configs/colibri_vf.h | 11 +++++++++++ 1 file changed, 11 insertions(+)

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 195102b..3e57417 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -272,4 +272,15 @@ #define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE

+/* Enable SPI support */ +#define CONFIG_DM_SPI +#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI

+#ifndef CONFIG_OF_CONTROL +#undef CONFIG_DM_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_FSL_DSPI +#endif

#endif /* __CONFIG_H */

Hm, any specific reason we need to define them unconditionally first? Couldn't we just inverse the logic and safe the undefs?

#ifdef CONFIG_OF_CONTROL #define CONFIG_DM_SPI #define CONFIG_CMD_SPI #define CONFIG_FSL_DSPI #endif

-- Stefan

Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees. Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com --- configs/colibri_vf_dtb_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfig

diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig new file mode 100644 index 0000000..d4c8c58 --- /dev/null +++ b/configs/colibri_vf_dtb_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"

On 06/01/2015 04:05 PM, Stefan Agner wrote:

On 2015-06-01 10:51, Bhuvanchandra DV wrote:

...

Most of the drivers available for Vybrid are not yet converted to OF model to use device tree model, only few drivers like SPI and GPIO drivers use device trees. Add separate defconfig for who needs to use device tree model. Later this can be integrated to single defconfig.

Signed-off-by: Bhuvanchandra DV bhuvanchandra.dv@toradex.com

configs/colibri_vf_dtb_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 configs/colibri_vf_dtb_defconfig

diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig new file mode 100644 index 0000000..d4c8c58 --- /dev/null +++ b/configs/colibri_vf_dtb_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"

One minor nit: Can you add this new file to the list of files in our boards maintainer file?

board/toradex/colibri_vf/MAINTAINERS

Sure, will add it.

But otherwise: Acked-by: Stefan Agner stefan@agner.ch

-- Stefan

Best regards, Bhuvan

From: Sanchayan Maity maitysanchayan@gmail.com

Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start".

Signed-off-by: Sanchayan Maity maitysanchayan@gmail.com --- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 1 + board/toradex/colibri_vf/colibri_vf.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+)

diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index b8b22b1..019307b 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -131,6 +131,7 @@ enum { VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 7173022..8618fd0 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -20,6 +20,7 @@ #include <netdev.h> #include <i2c.h> #include <g_dnl.h> +#include <asm/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)

+#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { + VF610_PAD_PTD4__GPIO_83, +}; + int dram_init(void) { static const struct ddr3_jedec_timings timings = { @@ -464,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)

return 0; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + switch (port) { + case 0: + /* USBC does not have PEN, also configured as USB client only */ + break; + case 1: + gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); + gpio_direction_output(USB_PEN_GPIO, 0); + break; + } + return 0; +} +#endif