On 12/22/2017 06:19 PM, Tom Rini wrote:

In order for these commands to not be included in SPL we need to guard compilation with CONFIG_SPL_BUILD checks. Reorganize some sections of code slightly in order to avoid new warnings and mark the command functions as static as they should have been before.

I'd expect the gc sections to collect those, is that no longer the case? Do these commands actually land in the SPL and does this patch make any size difference ?

Cc: Marek Vasut marex@denx.de Signed-off-by: Tom Rini trini@konsulko.com

---

arch/arm/mach-socfpga/clock_manager.c | 4 +++- arch/arm/mach-socfpga/misc_gen5.c | 13 ++++++++----- 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index cb6ae036961d..6b76221025af 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -59,7 +59,8 @@ int set_cpu_clk_info(void) return 0; }

-int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +#ifndef CONFIG_SPL_BUILD +static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cm_print_clock_quick_summary(); return 0; @@ -70,3 +71,4 @@ U_BOOT_CMD( "display clocks", "" ); +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 91ddb79f7310..a7dcaccbb793 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -30,14 +30,10 @@ static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_reset_manager *reset_manager_base =

• (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;

static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl =

• (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

/*

• DesignWare Ethernet initialization

@@ -292,6 +288,12 @@ int arch_early_init_r(void) return 0; }

+#ifndef CONFIG_SPL_BUILD +static struct socfpga_reset_manager *reset_manager_base =

• (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;

+static struct socfpga_sdr_ctrl *sdr_ctrl =

• (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

static void socfpga_sdram_apply_static_cfg(void) { const u32 applymask = 0x8; @@ -321,7 +323,7 @@ static void socfpga_sdram_apply_static_cfg(void) : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); }

-int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc != 2) return CMD_RET_USAGE; @@ -357,3 +359,4 @@ U_BOOT_CMD( "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" "" ); +#endif