[U-Boot] [PATCH] sh: sh7722: Fix multiple definition of PSDR in serial_sh

Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com --- drivers/serial/serial_sh.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index df21b37..54e94e5 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -87,6 +87,7 @@ struct uart_port { # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ #elif defined(CONFIG_CPU_SH7722) # define PADR 0xA4050120 +# undef PSDR # define PSDR 0xA405013e # define PWDR 0xA4050166 # define PSCR 0xA405011E

The serial of ap325rxa has it of two kinds, and the setting of the clock is different. Because there was a problem by function to judge serial kind, this revised it.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com --- drivers/serial/serial_sh.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 54e94e5..e19593c 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -675,14 +675,14 @@ static inline int sci_rxd_in(struct uart_port *port) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SH7723) ||\ defined(CONFIG_CPU_SH7724) -static inline int scbrr_calc(struct uart_port *port, int bps, int clk) +static inline int scbrr_calc(struct uart_port port, int bps, int clk) { - if (port->type == PORT_SCIF) + if (port.type == PORT_SCIF) return (clk+16*bps)/(32*bps)-1; else return ((clk*2)+16*bps)/(16*bps)-1; } -#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) +#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) #else /* Generic SH */
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Nobuhiro Iwamatsu