[U-Boot-Users] AMCC Luan BDI2000 Config File
Does anyone know where I can get a BDI2000 config file for AMCC's Luan eval board, and a BDI2000 reg file for the 440SP?
Thanks, Jeff jsteve17@yahoo.com
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Does anyone know where I can get a BDI2000 config file for AMCC's Luan eval board, and a BDI2000 reg file for the 440SP?
06/07/2005 01:03 PM 6,332 evb440sp.cfg 05/30/2005 03:39 PM 11,612 reg440sp.def
Here evb440sp.cfg (page down for reg440sp.def):
;bdiGDB configuration file for AMCC 440SP LUAN 2 Board ; ---------------------------------------------------- ; [INIT] ; Setup TLB WTLB 0xF0000095 0x1F00003F ;Boot Space 256MB (Flash,SRAM,EPLD) WTLB 0x00000094 0x0000003F ;SDRAM 256MB @ 0x00000000 WTLB 0x10000094 0x0100003F ;SDRAM 256MB @ 0x10000000 ; ; Setup caches WSPR 0x370 0x00000000 ;INV0 WSPR 0x371 0x00000000 ;INV1 WSPR 0x372 0x00000000 ;INV2 WSPR 0x373 0x00000000 ;INV3 WSPR 0x374 0x00000000 ;ITV0 WSPR 0x375 0x00000000 ;ITV1 WSPR 0x376 0x00000000 ;ITV2 WSPR 0x377 0x00000000 ;ITV3 WSPR 0x390 0x00000000 ;DNV0 WSPR 0x391 0x00000000 ;DNV1 WSPR 0x392 0x00000000 ;DNV2 WSPR 0x393 0x00000000 ;DNV3 WSPR 0x394 0x00000000 ;DTV0 WSPR 0x395 0x00000000 ;DTV1 WSPR 0x396 0x00000000 ;DTV2 WSPR 0x397 0x00000000 ;DTV3 WSPR 0x398 0x0001f800 ;DVLIM WSPR 0x399 0x0001f800 ;IVLIM ; ; Setup Peripheral Bus WDCR 0x12 0x00000010 ;Select EBC0_B0AP WDCR 0x13 0x03800000 ;B0AP: Flash and SRAM WDCR 0x12 0x00000000 ;Select EBC0_B0CR WDCR 0x13 0xFFE38000 ;B0CR: 2MB at 0xFFE00000, r/w, 8bit ; WDCR 0x12 0x00000011 ;Select EBC0_B1AP WDCR 0x13 0x02095a40 ;B1AP: EPLD and FRAM WDCR 0x12 0x00000001 ;Select EBC0_B1CR WDCR 0x13 0xf8018000 ;B1CR: 1MB at 0xF8000000, r/w, 8bit ; WDCR 0x12 0x00000012 ;Select EBC0_B2AP WDCR 0x13 0x03800000 ;B2AP: 4 MB Flash WDCR 0x12 0x00000002 ;Select EBC0_B2CR WDCR 0x13 0xff858000 ;B2CR: 4MB at 0xFF800000, r/w, 8bit ; ; Setup DDR2 Controller WDCR 0x10 0x00000021 ;Select MCIF0_MCOPT2 WDCR 0x11 0x84000000 ;MCOPT2: Clear DCEN BIT WDCR 0x10 0x00000020 ;Select MCIF0_MCOPT1 WDCR 0x11 0x2D122000 ;MCOPT1: ECC OFF,64 bits,4 banks,DDR2 WDCR 0x10 0x00000026 ;Select MCIF0_CODT WDCR 0x11 0x00800026 ;CODT: Die Termination On WDCR 0x10 0x00000081 ;Select MCIF0_WRDTR WDCR 0x11 0x82000800 ;WRDTR: Write DQS Adv 90 + Fractional DQS Delay WDCR 0x10 0x00000080 ;Select MCIF0_CLKTR WDCR 0x11 0x80000000 ;CLKTR: Adv Addr clock by 180 deg WDCR 0x10 0x00000040 ;Select MCIF0_MB0CF WDCR 0x11 0x00000201 ;MB0CF: Turn on CS0, N x 10 coll WDCR 0x10 0x00000044 ;Select MCIF0_MB1CF WDCR 0x11 0x00000201 ;MB1CF: Turn on CS0, N x 10 coll WDCR 0x10 0x00000030 ;Select MCIF0_RTR WDCR 0x11 0x08200000 ;RTR: Refresh every 7.8125uS WDCR 0x10 0x00000085 ;Select MCIF0_SDTR1 WDCR 0x11 0x80201000 ;SDTR1: Timing Register 1 WDCR 0x10 0x00000086 ;Select MCIF0_SDTR2 WDCR 0x11 0x42103242 ;SDTR2: Timing Register 2 WDCR 0x10 0x00000087 ;Select MCIF0_SDTR3 WDCR 0x11 0x0C100D14 ;SDTR3: Timing Register 3 WDCR 0x10 0x00000088 ;Select MCIF0_MMODE WDCR 0x11 0x00000642 ;MMODE: CAS = 4 cycles WDCR 0x10 0x00000089 ;Select MCIF0_MEMODE WDCR 0x11 0x00000400 ;MEMODE: Diff DQS disabled, ODT term disabled ; WDCR 0x10 0x00000050 ;Select MCIF0_INITPLR0 WDCR 0x11 0x81b80000 ;INITPLR0: NOP WDCR 0x10 0x00000051 ;Select MCIF0_INITPLR1 WDCR 0x11 0x82100400 ;INITPLR1: PRE WDCR 0x10 0x00000052 ;Select MCIF0_INITPLR2 WDCR 0x11 0x80820000 ;INITPLR2: EMR2 WDCR 0x10 0x00000053 ;Select MCIF0_INITPLR3 WDCR 0x11 0x80830000 ;INITPLR3: EMR3 WDCR 0x10 0x00000054 ;Select MCIF0_INITPLR4 WDCR 0x11 0x80810000 ;INITPLR4: EMR DLL ENABLE WDCR 0x10 0x00000055 ;Select MCIF0_INITPLR5 WDCR 0x11 0x80800542 ;INITPLR5: MR DLL RESET WDCR 0x10 0x00000056 ;Select MCIF0_INITPLR6 WDCR 0x11 0x82100400 ;INITPLR6: PRE WDCR 0x10 0x00000057 ;Select MCIF0_INITPLR7 WDCR 0x11 0x99080000 ;INITPLR7: Refresh WDCR 0x10 0x00000058 ;Select MCIF0_INITPLR8 WDCR 0x11 0x99080000 ;INITPLR8: Refresh WDCR 0x10 0x00000059 ;Select MCIF0_INITPLR9 WDCR 0x11 0x99080000 ;INITPLR9: Refresh WDCR 0x10 0x0000005A ;Select MCIF0_INITPLR10 WDCR 0x11 0x99080000 ;INITPLR10: Refresh WDCR 0x10 0x0000005B ;Select MCIF0_INITPLR11 WDCR 0x11 0x80800442 ;INITPLR11: MR WDCR 0x10 0x0000005C ;Select MCIF0_INITPLR12 WDCR 0x11 0x80810380 ;INITPLR12: EMR OCD Default WDCR 0x10 0x0000005D ;Select MCIF0_INITPLR13 WDCR 0x11 0x80810000 ;INITPLR12: EMR OCD Exit DELAY 10 ; WDCR 0x10 0x00000021 ;Select MCIF0_MCOPT2 WDCR 0x11 0x28000000 ;MCOPT2: Execute Preloaded Initialization Sequence, set DC_EN DELAY 100 ; WDCR 0x40 0x0000F800 ;MQ0_B0BAS: Base Address 0x00000000 / Size 256 MB WDCR 0x41 0x1000F800 ;MQ0_B1BAS: Base Address 0x10000000 / Size 256 MB ; WDCR 0x10 0x00000078 ;Select MCIF0_RDCC WDCR 0x11 0x00000000 ;RDCC: Auto Set Read Stage WDCR 0x10 0x00000070 ;Select MCIF0_RQDC WDCR 0x11 0x8000003A ;RQDC: Read DQS Delay Control Enabled + Fractional DQS Delay WDCR 0x10 0x00000074 ;Select MCIF0_RFDC WDCR 0x11 0x00000200 ;RFDC: 2 clock feedback delay ;
[TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 440 ;the used target CPU type SCANMISC 8 ;IR length is 8 bits for 440SP WAKEUP 50 ;wakeup time after reset BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses one or two hardware breakpoints
[HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mpc860\fibo.elf FORMAT ELF DUMP E:\temp\dump.bin PROMPT 440SP>
[FLASH] ; program large 4MB Flash (AM29LV033C) at 0xff800000 WORKSPACE 0xFFE00000 ;workspace in SRAM for fast programming algorithm CHIPTYPE AM29F ;Flash type CHIPSIZE 0x400000 ;The size of one flash chip in bytes BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE E:\temp\dump256k.bin FORMAT BIN 0xFF800000 ERASE 0xFF800000 ;erase sector 0 of flash (AM29LV033C) ERASE 0xFF810000 ;erase sector 1 of flash ERASE 0xFF820000 ;erase sector 2 of flash ERASE 0xFF830000 ;erase sector 3 of flash ERASE 0xFF840000 ;erase sector 4 of flash ERASE 0xFF850000 ;erase sector 5 of flash ERASE 0xFF860000 ;erase sector 6 of flash ERASE 0xFF870000 ;erase sector 7 of flash
[REGS] IDCR1 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA IDCR2 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA IDCR3 0x010 0x011 ;MCIF0_CFGADDR and MCIF0_CFGDATA IDCR4 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA FILE $reg440sp.def
And here's reg440sp.def:
;Register definition for PPC440SP ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IDCRx indirect accessed DCR's ; x = 1..4 ; the addr and data DCR is defined in the configuration file ; e.g. IDCR1 0x010 0x011 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; ; Special Purpose Registers ; xer SPR 0x001 lr SPR 0x008 ctr SPR 0x009 dec SPR 0x016 srr0 SPR 0x01a srr1 SPR 0x01b pid SPR 0x030 decar SPR 0x036 csrr0 SPR 0x03a csrr1 SPR 0x03b dear SPR 0x03d esr SPR 0x03e ivpr SPR 0x03f usprg0 SPR 0x100 sprg4r SPR 0x104 sprg5r SPR 0x105 sprg6r SPR 0x106 sprg7r SPR 0x107 tblr SPR 0x10c tbur SPR 0x10d sprg0 SPR 0x110 sprg1 SPR 0x111 sprg2 SPR 0x112 sprg3 SPR 0x113 sprg4w SPR 0x114 sprg5w SPR 0x115 sprg6w SPR 0x116 sprg7w SPR 0x117 tblw SPR 0x11c tbuw SPR 0x11d pir SPR 0x11e pvr SPR 0x11f dbsr SPR 0x130 dbcr0 SPR 0x134 dbcr1 SPR 0x135 dbcr2 SPR 0x136 iac1 SPR 0x138 iac2 SPR 0x139 iac3 SPR 0x13a iac4 SPR 0x13b dac1 SPR 0x13c dac2 SPR 0x13d dvc1 SPR 0x13e dvc2 SPR 0x13f tsr SPR 0x150 tcr SPR 0x154 ivor0 SPR 0x190 ivor1 SPR 0x191 ivor2 SPR 0x192 ivor3 SPR 0x193 ivor4 SPR 0x194 ivor5 SPR 0x195 ivor6 SPR 0x196 ivor7 SPR 0x197 ivor8 SPR 0x198 ivor9 SPR 0x199 ivor10 SPR 0x19a ivor11 SPR 0x19b ivor12 SPR 0x19c ivor13 SPR 0x19d ivor14 SPR 0x19e ivor15 SPR 0x19f mcsrr0 SPR 0x23a mcsrr1 SPR 0x23b mcsr SPR 0x23c inv0 SPR 0x370 inv1 SPR 0x371 inv2 SPR 0x372 inv3 SPR 0x373 itv0 SPR 0x374 itv1 SPR 0x375 itv2 SPR 0x376 itv3 SPR 0x377 ccr1 SPR 0x378 dnv0 SPR 0x390 dnv1 SPR 0x391 dnv2 SPR 0x392 dnv3 SPR 0x393 dtv0 SPR 0x394 dtv1 SPR 0x395 dtv2 SPR 0x396 dtv3 SPR 0x397 dvlim SPR 0x398 ivlim SPR 0x399 rstcfg SPR 0x39b dcdbtrl SPR 0x39c dcdbtrh SPR 0x39d icdbtrl SPR 0x39e icdbtrh SPR 0x39f mmucr SPR 0x3b2 ccr0 SPR 0x3b3 icdbdr SPR 0x3d3 dbdr SPR 0x3f3 ; ; Directly Accessed DCR's ; cpr0_cfgaddr DCR 0x00C ;Clocking Configuration Address Register cpr0_cfgdata DCR 0x00D ;Clocking Configuration Data Register sdr0_cfgaddr DCR 0x00E ;System DCR Configuration Address Register sdr0_cfgdata DCR 0x00F ;System DCR Configuration Data Register mcif0_cfgaddr DCR 0x010 ;Memory Controller Configuration Address mcif0_cfgdata DCR 0x011 ;Memory Controller Configuration Data ebc0_cfgaddr DCR 0x012 ;EBC0 Configuration Address ebc0_cfgdata DCR 0x013 ;EBC0 Configuration Data ; ; Internal SRAM Controller ; sram0_sb0cr DCR 0x020 sram0_sb1cr DCR 0x021 sram0_sb2cr DCR 0x022 sram0_sb3cr DCR 0x023 sram0_bear DCR 0x024 sram0_besr0 DCR 0x025 sram0_besr1 DCR 0x026 sram0_pmeg DCR 0x027 sram0_cid DCR 0x028 sram0_revid DCR 0x029 sram0_dpc DCR 0x0a0 ; ; Level 2 cache ; l2c0_cfg DCR 0x030 l2c0_cmd DCR 0x031 l2c0_addr DCR 0x032 l2c0_data DCR 0x033 l2c0_sr DCR 0x034 l2c0_revid DCR 0x035 l2c0_snp0 DCR 0x036 l2c0_snp1 DCR 0x037 ; ; Memory Queue ; mq0_b0bas DCR 0x0040 mq0_b1bas DCR 0x0041 mq0_bauh DCR 0x0043 mq0_cf1h DCR 0x0045 mq0_esh DCR 0x0047 mq0_eauh DCR 0x0048 mq0_ealh DCR 0x0049 mq0_baul DCR 0x004A mq0_cf1l DCR 0x004B mq0_esl DCR 0x004C mq0_eaul DCR 0x004D mq0_eall DCR 0x004E mq0_cfbhl DCR 0x004F ; ; I2O/DMA ; i2o0_llirq0l DCR 0x0060 i2o0_llirq0h DCR 0x0061 i2o0_llwr0m DCR 0x0062 i2o0_llirq1l DCR 0x0063 i2o0_llirq1h DCR 0x0064 i2o0_llwr1m DCR 0x0065 i2o0_ibal DCR 0x0066 i2o0_ibah DCR 0x0067 i2o0_dma0_st DCR 0x0068 i2o0_dma1_st DCR 0x0069 i2o0_istat DCR 0x006A i2o0_dma0_op DCR 0x006B i2o0_dma1_op DCR 0x006C i2o0_seat DCR 0x006D i2o0_sead DCR 0x006E i2o0_i2o_op DCR 0x006F i2o0_hwr0l DCR 0x0070 i2o0_hwr0h DCR 0x0071 i2o0_hwrom DCR 0x0072 i2o0_hwr1l DCR 0x0073 i2o0_hwr1h DCR 0x0074 i2o0_hwr1m DCR 0x0075 i2o0_miscc DCR 0x0076 ; ; PLB Crossbar Arbiter Registers ; plb_revid DCR 0x0080 plb0_acr DCR 0x0081 plb0_besrl DCR 0x0082 plb0_besrh DCR 0x0083 plb0_bearl DCR 0x0084 plb0_bearh DCR 0x0085 plb_ccr DCR 0x0088 plb1_acr DCR 0x0089 plb1_besrl DCR 0x008A plb1_besrh DCR 0x008B plb1_bearl DCR 0x008C plb1_bearh DCR 0x008D ; ; PLB to OPB bridge Registers ; pob0_besr0 DCR 0x0090 pob0_bearl DCR 0x0092 pob0_bearh DCR 0x0093 pob0_besr1 DCR 0x0094 pob0_confg DCR 0x0096 pob0_latency DCR 0x0098 pob0_revid DCR 0x009A ; ; Universal Interrupt Controllers ; uic0_sr DCR 0x0c0 uic0_er DCR 0x0c2 uic0_cr DCR 0x0c3 uic0_pr DCR 0x0c4 uic0_tr DCR 0x0c5 uic0_msr DCR 0x0c6 uic0_vr DCR 0x0c7 uic0_vcr DCR 0x0c8 uic1_sr DCR 0x0d0 uic1_er DCR 0x0d2 uic1_cr DCR 0x0d3 uic1_pr DCR 0x0d4 uic1_tr DCR 0x0d5 uic1_msr DCR 0x0d6 uic1_vr DCR 0x0d7 uic1_vcr DCR 0x0d8 ; ; Clocking and Power Management ; cpm0_er DCR 0x0e0 cpm0_fr DCR 0x0e1 cpm0_sr DCR 0x0e2 ; ; Memory Access Layer ; mal0_cfg DCR 0x0180 mal0_esr DCR 0x0181 mal0_ier DCR 0x0182 mal0_txcasr DCR 0x0184 mal0_txcarr DCR 0x0185 mal0_txeobisr DCR 0x0186 mal0_txdeir DCR 0x0187 mal0_txtattrr DCR 0x0188 mal0_txbaddr DCR 0x0189 mal0_rxcasr DCR 0x0190 mal0_rxcarr DCR 0x0191 mal0_rxeobisr DCR 0x0192 mal0_rxdeir DCR 0x0193 mal0_rxtattrr DCR 0x0194 mal0_rxbaddr DCR 0x0195 mal0_txctp0r DCR 0x01A0 mal0_rxctp0r DCR 0x01C0 mal0_rcbs0 DCR 0x01E0 ; ; ; Indirectly Accessed DCR's ; ; IDCR1 must be set to CPR0_CFGADDR and CPR0_CFGDATA ; IDCR2 must be set to SDR0_CFGADDR and SDR0_CFGDATA ; IDCR3 must be set to MCIF0_CFGADDR and MCIF0_CFGDATA ; IDCR4 must be set to EBC0_CFGADDR and EBC0_CFGDATA ; ; ; Clocking and PowerOn Reset DCR ; cpr0_clkupd IDCR1 0x0020 cpr0_pllc IDCR1 0x0040 cpr0_plld IDCR1 0x0060 cpr0_primad IDCR1 0x0080 cpr0_primbd IDCR1 0x00A0 cpr0_opbd IDCR1 0x00C0 cpr0_perd IDCR1 0x00E0 cpr0_mald IDCR1 0x0100 cpr0_icfg IDCR1 0x0140 ; ; ; System DCR ; sdr0_sdstp0 IDCR2 0x0020 sdr0_sdstp1 IDCR2 0x0021 sdr0_sdstp2 IDCR2 0x0022 sdr0_sdstp3 IDCR2 0x0023 sdr0_pinstp IDCR2 0x0040 sdr0_sdcs IDCR2 0x0060 sdr0_ecid0 IDCR2 0x0080 sdr0_ecid1 IDCR2 0x0081 sdr0_ecid2 IDCR2 0x0082 sdr0_jtag IDCR2 0x00C0 sdr0_ddrdl IDCR2 0x00E1 sdr0_uart0 IDCR2 0x0120 sdr0_uart1 IDCR2 0x0121 sdr0_uart2 IDCR2 0x0122 sdr0_cp440 IDCR2 0x0180 sdr0_xcr0 IDCR2 0x01C0 sdr0_xpllc0 IDCR2 0x01C1 sdr0_xplld0 IDCR2 0x01C2 sdr0_xcr1 IDCR2 0x01C3 sdr0_xpllc1 IDCR2 0x01C4 sdr0_xplld1 IDCR2 0x01C5 sdr0_xcr2 IDCR2 0x01C6 sdr0_xpllc2 IDCR2 0x01C7 sdr0_xplld2 IDCR2 0x01C8 sdr0_srst IDCR2 0x0200 sdr0_slpipe IDCR2 0x0220 sdr0_amp0 IDCR2 0x0240 sdr0_amp1 IDCR2 0x0241 sdr0_mirq0 IDCR2 0x0260 sdr0_mirq1 IDCR2 0x0261 sdr0_maltbl IDCR2 0x0280 sdr0_malrbl IDCR2 0x02A0 sdr0_maltbs IDCR2 0x02C0 sdr0_malrbs IDCR2 0x02E0 sdr0_cust0 IDCR2 0x4000 sdr0_sdstp4 IDCR2 0x4001 sdr0_cust1 IDCR2 0x4002 sdr0_sdstp5 IDCR2 0x4003 sdr0_cust2 IDCR2 0x4004 sdr0_sdstp6 IDCR2 0x4005 sdr0_cust3 IDCR2 0x4006 sdr0_sdstp7 IDCR2 0x4007 sdr0_pfc0 IDCR2 0x4100 sdr0_pfc1 IDCR2 0x4101 sdr0_plbtr IDCR2 0x4200 sdr0_mfr IDCR2 0x4300 ; ; ; DDR-SDRAM Controller DCRs ; mcif0_mcstat IDCR3 0x0014 mcif0_mcopt1 IDCR3 0x0020 mcif0_mcopt2 IDCR3 0x0021 mcif0_modt0 IDCR3 0x0022 mcif0_modt1 IDCR3 0x0023 mcif0_codt IDCR3 0x0026 mcif0_vvpr IDCR3 0x0027 ;mcif0_opar1 IDCR3 0x0028 ;mcif0_opar2 IDCR3 0x0029 mcif0_rtr IDCR3 0x0030 mcif0_pmit IDCR3 0x0034 mcif0_mb0cf IDCR3 0x0040 mcif0_mb1cf IDCR3 0x0044 mcif0_initplr0 IDCR3 0x0050 mcif0_initplr1 IDCR3 0x0051 mcif0_initplr2 IDCR3 0x0052 mcif0_initplr3 IDCR3 0x0053 mcif0_initplr4 IDCR3 0x0054 mcif0_initplr5 IDCR3 0x0055 mcif0_initplr6 IDCR3 0x0056 mcif0_initplr7 IDCR3 0x0057 mcif0_initplr8 IDCR3 0x0058 mcif0_initplr9 IDCR3 0x0059 mcif0_initplr10 IDCR3 0x005A mcif0_initplr11 IDCR3 0x005B mcif0_initplr12 IDCR3 0x005C mcif0_initplr13 IDCR3 0x005D mcif0_initplr14 IDCR3 0x005E mcif0_initplr15 IDCR3 0x005F mcif0_rqdc IDCR3 0x0070 mcif0_rfdc IDCR3 0x0074 mcif0_rdcc IDCR3 0x0078 mcif0_dlcr IDCR3 0x007A mcif0_clktr IDCR3 0x0080 mcif0_wrdtr IDCR3 0x0081 mcif0_sdtr1 IDCR3 0x0085 mcif0_sdtr2 IDCR3 0x0086 mcif0_sdtr3 IDCR3 0x0087 mcif0_mmode IDCR3 0x0088 mcif0_memode IDCR3 0x0089 mcif0_ecces IDCR3 0x0098 ; ; ; External Bus Controller DCRs ; ebc0_b0cr IDCR4 0x00 ebc0_b1cr IDCR4 0x01 ebc0_b2cr IDCR4 0x02 ebc0_b0ap IDCR4 0x10 ebc0_b1ap IDCR4 0x11 ebc0_b2ap IDCR4 0x12 ebc0_bear IDCR4 0x20 ebc0_besr IDCR4 0x21 ebc0_cfg IDCR4 0x23 ebc0_cid IDCR4 0x24 ;
Jeff Stevens wrote:
Does anyone know where I can get a BDI2000 config file for AMCC's Luan eval board, and a BDI2000 reg file for the 440SP?
Thanks, Jeff jsteve17@yahoo.com
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Thanks for the files John! What DDR2 memory configuration is this for (DIMM size, manufacturer, part number, etc)? I have the Luan board booting until it relocates into ram, but it never reaches board_init_r. I'm wondering if we have different modules. Also, does anyone know if U-Boot is going to eventually support SPD for DDR2?
Thanks, Jeff Stevens
--- John Otken jotken@softadvances.com wrote:
Does anyone know where I can get a BDI2000 config
file
for AMCC's Luan eval board, and a BDI2000 reg
file for
the 440SP?
06/07/2005 01:03 PM 6,332 evb440sp.cfg 05/30/2005 03:39 PM 11,612 reg440sp.def
Here evb440sp.cfg (page down for reg440sp.def):
;bdiGDB configuration file for AMCC 440SP LUAN 2 Board ;
; [INIT] ; Setup TLB WTLB 0xF0000095 0x1F00003F ;Boot Space 256MB (Flash,SRAM,EPLD) WTLB 0x00000094 0x0000003F ;SDRAM 256MB @ 0x00000000 WTLB 0x10000094 0x0100003F ;SDRAM 256MB @ 0x10000000 ; ; Setup caches WSPR 0x370 0x00000000 ;INV0 WSPR 0x371 0x00000000 ;INV1 WSPR 0x372 0x00000000 ;INV2 WSPR 0x373 0x00000000 ;INV3 WSPR 0x374 0x00000000 ;ITV0 WSPR 0x375 0x00000000 ;ITV1 WSPR 0x376 0x00000000 ;ITV2 WSPR 0x377 0x00000000 ;ITV3 WSPR 0x390 0x00000000 ;DNV0 WSPR 0x391 0x00000000 ;DNV1 WSPR 0x392 0x00000000 ;DNV2 WSPR 0x393 0x00000000 ;DNV3 WSPR 0x394 0x00000000 ;DTV0 WSPR 0x395 0x00000000 ;DTV1 WSPR 0x396 0x00000000 ;DTV2 WSPR 0x397 0x00000000 ;DTV3 WSPR 0x398 0x0001f800 ;DVLIM WSPR 0x399 0x0001f800 ;IVLIM ; ; Setup Peripheral Bus WDCR 0x12 0x00000010 ;Select EBC0_B0AP WDCR 0x13 0x03800000 ;B0AP: Flash and SRAM WDCR 0x12 0x00000000 ;Select EBC0_B0CR WDCR 0x13 0xFFE38000 ;B0CR: 2MB at 0xFFE00000, r/w, 8bit ; WDCR 0x12 0x00000011 ;Select EBC0_B1AP WDCR 0x13 0x02095a40 ;B1AP: EPLD and FRAM WDCR 0x12 0x00000001 ;Select EBC0_B1CR WDCR 0x13 0xf8018000 ;B1CR: 1MB at 0xF8000000, r/w, 8bit ; WDCR 0x12 0x00000012 ;Select EBC0_B2AP WDCR 0x13 0x03800000 ;B2AP: 4 MB Flash WDCR 0x12 0x00000002 ;Select EBC0_B2CR WDCR 0x13 0xff858000 ;B2CR: 4MB at 0xFF800000, r/w, 8bit ; ; Setup DDR2 Controller WDCR 0x10 0x00000021 ;Select MCIF0_MCOPT2 WDCR 0x11 0x84000000 ;MCOPT2: Clear DCEN BIT WDCR 0x10 0x00000020 ;Select MCIF0_MCOPT1 WDCR 0x11 0x2D122000 ;MCOPT1: ECC OFF,64 bits,4 banks,DDR2 WDCR 0x10 0x00000026 ;Select MCIF0_CODT WDCR 0x11 0x00800026 ;CODT: Die Termination On WDCR 0x10 0x00000081 ;Select MCIF0_WRDTR WDCR 0x11 0x82000800 ;WRDTR: Write DQS Adv 90 + Fractional DQS Delay WDCR 0x10 0x00000080 ;Select MCIF0_CLKTR WDCR 0x11 0x80000000 ;CLKTR: Adv Addr clock by 180 deg WDCR 0x10 0x00000040 ;Select MCIF0_MB0CF WDCR 0x11 0x00000201 ;MB0CF: Turn on CS0, N x 10 coll WDCR 0x10 0x00000044 ;Select MCIF0_MB1CF WDCR 0x11 0x00000201 ;MB1CF: Turn on CS0, N x 10 coll WDCR 0x10 0x00000030 ;Select MCIF0_RTR WDCR 0x11 0x08200000 ;RTR: Refresh every 7.8125uS WDCR 0x10 0x00000085 ;Select MCIF0_SDTR1 WDCR 0x11 0x80201000 ;SDTR1: Timing Register 1 WDCR 0x10 0x00000086 ;Select MCIF0_SDTR2 WDCR 0x11 0x42103242 ;SDTR2: Timing Register 2 WDCR 0x10 0x00000087 ;Select MCIF0_SDTR3 WDCR 0x11 0x0C100D14 ;SDTR3: Timing Register 3 WDCR 0x10 0x00000088 ;Select MCIF0_MMODE WDCR 0x11 0x00000642 ;MMODE: CAS = 4 cycles WDCR 0x10 0x00000089 ;Select MCIF0_MEMODE WDCR 0x11 0x00000400 ;MEMODE: Diff DQS disabled, ODT term disabled ; WDCR 0x10 0x00000050 ;Select MCIF0_INITPLR0 WDCR 0x11 0x81b80000 ;INITPLR0: NOP WDCR 0x10 0x00000051 ;Select MCIF0_INITPLR1 WDCR 0x11 0x82100400 ;INITPLR1: PRE WDCR 0x10 0x00000052 ;Select MCIF0_INITPLR2 WDCR 0x11 0x80820000 ;INITPLR2: EMR2 WDCR 0x10 0x00000053 ;Select MCIF0_INITPLR3 WDCR 0x11 0x80830000 ;INITPLR3: EMR3 WDCR 0x10 0x00000054 ;Select MCIF0_INITPLR4 WDCR 0x11 0x80810000 ;INITPLR4: EMR DLL ENABLE WDCR 0x10 0x00000055 ;Select MCIF0_INITPLR5 WDCR 0x11 0x80800542 ;INITPLR5: MR DLL RESET WDCR 0x10 0x00000056 ;Select MCIF0_INITPLR6 WDCR 0x11 0x82100400 ;INITPLR6: PRE WDCR 0x10 0x00000057 ;Select MCIF0_INITPLR7 WDCR 0x11 0x99080000 ;INITPLR7: Refresh WDCR 0x10 0x00000058 ;Select MCIF0_INITPLR8 WDCR 0x11 0x99080000 ;INITPLR8: Refresh WDCR 0x10 0x00000059 ;Select MCIF0_INITPLR9 WDCR 0x11 0x99080000 ;INITPLR9: Refresh WDCR 0x10 0x0000005A ;Select MCIF0_INITPLR10 WDCR 0x11 0x99080000 ;INITPLR10: Refresh WDCR 0x10 0x0000005B ;Select MCIF0_INITPLR11 WDCR 0x11 0x80800442 ;INITPLR11: MR WDCR 0x10 0x0000005C ;Select MCIF0_INITPLR12 WDCR 0x11 0x80810380 ;INITPLR12: EMR OCD Default WDCR 0x10 0x0000005D ;Select MCIF0_INITPLR13 WDCR 0x11 0x80810000 ;INITPLR12: EMR OCD Exit DELAY 10 ; WDCR 0x10 0x00000021 ;Select MCIF0_MCOPT2 WDCR 0x11 0x28000000 ;MCOPT2: Execute Preloaded Initialization Sequence, set DC_EN DELAY 100 ; WDCR 0x40 0x0000F800 ;MQ0_B0BAS: Base Address 0x00000000 / Size 256 MB WDCR 0x41 0x1000F800 ;MQ0_B1BAS: Base Address 0x10000000 / Size 256 MB ; WDCR 0x10 0x00000078 ;Select MCIF0_RDCC WDCR 0x11 0x00000000 ;RDCC: Auto Set Read Stage WDCR 0x10 0x00000070 ;Select MCIF0_RQDC WDCR 0x11 0x8000003A ;RQDC: Read DQS Delay Control Enabled + Fractional DQS Delay WDCR 0x10 0x00000074 ;Select MCIF0_RFDC WDCR 0x11 0x00000200 ;RFDC: 2 clock feedback delay ;
[TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 440 ;the used target CPU type SCANMISC 8 ;IR length is 8 bits for 440SP WAKEUP 50 ;wakeup time after reset BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses one or two hardware breakpoints
[HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mpc860\fibo.elf FORMAT ELF DUMP E:\temp\dump.bin PROMPT 440SP>
[FLASH] ; program large 4MB Flash (AM29LV033C) at 0xff800000 WORKSPACE 0xFFE00000 ;workspace in SRAM for fast programming algorithm CHIPTYPE AM29F ;Flash type CHIPSIZE 0x400000 ;The size of one flash chip in bytes BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE E:\temp\dump256k.bin FORMAT BIN 0xFF800000 ERASE 0xFF800000 ;erase sector 0 of flash (AM29LV033C) ERASE 0xFF810000 ;erase sector 1 of flash ERASE 0xFF820000 ;erase sector 2 of flash ERASE 0xFF830000 ;erase sector 3 of flash ERASE 0xFF840000 ;erase sector 4 of flash ERASE 0xFF850000 ;erase sector 5 of flash ERASE 0xFF860000 ;erase sector 6 of flash ERASE 0xFF870000 ;erase sector 7 of flash
[REGS] IDCR1 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA IDCR2 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA IDCR3 0x010 0x011 ;MCIF0_CFGADDR and MCIF0_CFGDATA IDCR4 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA FILE $reg440sp.def
And here's reg440sp.def:
;Register definition for PPC440SP ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IDCRx indirect accessed DCR's ; x = 1..4 ; the addr and data DCR is defined in the configuration file ; e.g. IDCR1 0x010 0x011 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; ; Special Purpose Registers ; xer SPR 0x001 lr SPR 0x008 ctr SPR 0x009 dec SPR 0x016 srr0 SPR 0x01a srr1 SPR 0x01b pid SPR 0x030 decar SPR 0x036 csrr0 SPR 0x03a csrr1 SPR 0x03b dear SPR 0x03d esr SPR 0x03e ivpr SPR 0x03f usprg0 SPR 0x100 sprg4r SPR 0x104 sprg5r SPR 0x105 sprg6r SPR 0x106 sprg7r SPR 0x107 tblr SPR 0x10c tbur SPR 0x10d sprg0 SPR 0x110 sprg1 SPR 0x111 sprg2 SPR 0x112 sprg3 SPR 0x113 sprg4w SPR 0x114 sprg5w SPR 0x115 sprg6w SPR 0x116 sprg7w SPR 0x117 tblw SPR 0x11c tbuw SPR 0x11d pir SPR 0x11e pvr SPR 0x11f dbsr SPR 0x130 dbcr0 SPR 0x134 dbcr1 SPR 0x135 dbcr2 SPR 0x136 iac1 SPR 0x138 iac2 SPR 0x139 iac3 SPR 0x13a iac4 SPR 0x13b dac1 SPR 0x13c dac2 SPR 0x13d dvc1 SPR 0x13e dvc2 SPR 0x13f tsr SPR 0x150 tcr SPR 0x154 ivor0 SPR 0x190 ivor1 SPR 0x191 ivor2 SPR 0x192 ivor3 SPR 0x193 ivor4 SPR 0x194 ivor5 SPR 0x195 ivor6 SPR 0x196 ivor7 SPR 0x197 ivor8 SPR 0x198 ivor9 SPR 0x199 ivor10 SPR 0x19a ivor11 SPR 0x19b ivor12 SPR 0x19c ivor13 SPR 0x19d ivor14 SPR 0x19e ivor15 SPR 0x19f mcsrr0 SPR 0x23a mcsrr1 SPR 0x23b mcsr SPR 0x23c inv0 SPR 0x370 inv1 SPR 0x371 inv2 SPR 0x372 inv3 SPR 0x373 itv0 SPR 0x374 itv1 SPR 0x375 itv2 SPR 0x376 itv3 SPR 0x377 ccr1 SPR 0x378 dnv0 SPR 0x390 dnv1 SPR 0x391 dnv2 SPR 0x392 dnv3 SPR 0x393 dtv0 SPR 0x394 dtv1 SPR 0x395 dtv2 SPR 0x396 dtv3 SPR 0x397 dvlim SPR 0x398 ivlim SPR 0x399 rstcfg SPR 0x39b dcdbtrl SPR 0x39c dcdbtrh SPR 0x39d icdbtrl SPR 0x39e icdbtrh SPR 0x39f mmucr SPR 0x3b2 ccr0 SPR 0x3b3 icdbdr SPR 0x3d3 dbdr SPR 0x3f3 ; ; Directly Accessed DCR's ; cpr0_cfgaddr DCR 0x00C ;Clocking Configuration Address Register cpr0_cfgdata DCR 0x00D ;Clocking Configuration Data Register sdr0_cfgaddr DCR 0x00E ;System DCR Configuration Address Register sdr0_cfgdata DCR 0x00F ;System DCR Configuration Data Register mcif0_cfgaddr DCR 0x010 ;Memory Controller Configuration Address mcif0_cfgdata DCR 0x011 ;Memory Controller Configuration Data ebc0_cfgaddr DCR 0x012 ;EBC0 Configuration Address ebc0_cfgdata DCR 0x013 ;EBC0 Configuration Data ; ; Internal SRAM Controller ; sram0_sb0cr DCR 0x020 sram0_sb1cr DCR 0x021 sram0_sb2cr DCR 0x022 sram0_sb3cr DCR 0x023 sram0_bear DCR 0x024 sram0_besr0 DCR 0x025 sram0_besr1 DCR 0x026 sram0_pmeg DCR 0x027 sram0_cid DCR 0x028 sram0_revid DCR 0x029 sram0_dpc DCR 0x0a0 ; ; Level 2 cache ; l2c0_cfg DCR 0x030 l2c0_cmd DCR 0x031 l2c0_addr DCR 0x032 l2c0_data DCR 0x033 l2c0_sr DCR 0x034 l2c0_revid DCR 0x035 l2c0_snp0 DCR 0x036 l2c0_snp1 DCR 0x037 ; ; Memory Queue ; mq0_b0bas DCR 0x0040 mq0_b1bas DCR 0x0041 mq0_bauh DCR 0x0043 mq0_cf1h DCR 0x0045 mq0_esh DCR 0x0047 mq0_eauh DCR 0x0048 mq0_ealh DCR 0x0049 mq0_baul DCR 0x004A mq0_cf1l DCR 0x004B mq0_esl DCR 0x004C mq0_eaul DCR 0x004D mq0_eall DCR 0x004E mq0_cfbhl DCR 0x004F ; ; I2O/DMA ; i2o0_llirq0l DCR 0x0060 i2o0_llirq0h DCR 0x0061 i2o0_llwr0m DCR 0x0062 i2o0_llirq1l DCR 0x0063 i2o0_llirq1h DCR 0x0064 i2o0_llwr1m DCR 0x0065 i2o0_ibal DCR 0x0066 i2o0_ibah DCR 0x0067 i2o0_dma0_st DCR 0x0068 i2o0_dma1_st DCR 0x0069 i2o0_istat DCR 0x006A i2o0_dma0_op DCR 0x006B i2o0_dma1_op DCR 0x006C i2o0_seat DCR 0x006D i2o0_sead DCR 0x006E i2o0_i2o_op DCR 0x006F i2o0_hwr0l DCR 0x0070 i2o0_hwr0h DCR 0x0071 i2o0_hwrom DCR 0x0072 i2o0_hwr1l DCR 0x0073 i2o0_hwr1h DCR 0x0074 i2o0_hwr1m DCR 0x0075 i2o0_miscc DCR 0x0076 ; ; PLB Crossbar Arbiter Registers ; plb_revid DCR 0x0080 plb0_acr DCR 0x0081 plb0_besrl DCR 0x0082 plb0_besrh DCR 0x0083 plb0_bearl DCR 0x0084 plb0_bearh DCR 0x0085 plb_ccr DCR 0x0088 plb1_acr DCR 0x0089 plb1_besrl DCR 0x008A plb1_besrh DCR 0x008B plb1_bearl DCR 0x008C plb1_bearh DCR 0x008D ; ; PLB to OPB bridge Registers ; pob0_besr0 DCR 0x0090 pob0_bearl DCR 0x0092 pob0_bearh DCR 0x0093 pob0_besr1 DCR 0x0094 pob0_confg DCR 0x0096 pob0_latency DCR 0x0098 pob0_revid DCR 0x009A ; ; Universal Interrupt Controllers ; uic0_sr DCR 0x0c0 uic0_er DCR 0x0c2 uic0_cr DCR 0x0c3 uic0_pr DCR 0x0c4 uic0_tr DCR 0x0c5 uic0_msr DCR 0x0c6 uic0_vr DCR 0x0c7 uic0_vcr DCR 0x0c8 uic1_sr DCR 0x0d0 uic1_er DCR 0x0d2 uic1_cr DCR 0x0d3 uic1_pr DCR 0x0d4 uic1_tr DCR 0x0d5 uic1_msr DCR 0x0d6 uic1_vr DCR 0x0d7 uic1_vcr DCR 0x0d8 ; ; Clocking and Power Management ; cpm0_er DCR 0x0e0 cpm0_fr DCR 0x0e1 cpm0_sr DCR 0x0e2 ; ; Memory Access Layer ; mal0_cfg DCR 0x0180 mal0_esr DCR 0x0181 mal0_ier DCR 0x0182 mal0_txcasr DCR 0x0184 mal0_txcarr DCR 0x0185 mal0_txeobisr DCR 0x0186 mal0_txdeir DCR 0x0187 mal0_txtattrr DCR 0x0188 mal0_txbaddr DCR 0x0189 mal0_rxcasr DCR 0x0190 mal0_rxcarr DCR 0x0191 mal0_rxeobisr DCR 0x0192 mal0_rxdeir DCR 0x0193 mal0_rxtattrr DCR 0x0194 mal0_rxbaddr DCR 0x0195 mal0_txctp0r DCR 0x01A0 mal0_rxctp0r DCR 0x01C0 mal0_rcbs0 DCR 0x01E0 ; ; ; Indirectly Accessed DCR's ; ; IDCR1 must be set to CPR0_CFGADDR and CPR0_CFGDATA ; IDCR2 must be set to SDR0_CFGADDR and SDR0_CFGDATA ; IDCR3 must be set to MCIF0_CFGADDR and MCIF0_CFGDATA ; IDCR4 must be set to EBC0_CFGADDR and EBC0_CFGDATA ; ; ; Clocking and PowerOn Reset DCR ; cpr0_clkupd IDCR1 0x0020 cpr0_pllc IDCR1 0x0040 cpr0_plld IDCR1 0x0060 cpr0_primad IDCR1 0x0080 cpr0_primbd IDCR1 0x00A0 cpr0_opbd IDCR1 0x00C0 cpr0_perd IDCR1 0x00E0 cpr0_mald IDCR1 0x0100 cpr0_icfg IDCR1 0x0140 ; ; ; System DCR ; sdr0_sdstp0 IDCR2 0x0020 sdr0_sdstp1 IDCR2 0x0021 sdr0_sdstp2 IDCR2 0x0022 sdr0_sdstp3 IDCR2 0x0023 sdr0_pinstp IDCR2 0x0040 sdr0_sdcs IDCR2 0x0060 sdr0_ecid0 IDCR2 0x0080 sdr0_ecid1 IDCR2 0x0081 sdr0_ecid2 IDCR2 0x0082 sdr0_jtag IDCR2 0x00C0 sdr0_ddrdl IDCR2 0x00E1 sdr0_uart0 IDCR2 0x0120 sdr0_uart1 IDCR2 0x0121 sdr0_uart2 IDCR2 0x0122 sdr0_cp440 IDCR2 0x0180 sdr0_xcr0 IDCR2 0x01C0 sdr0_xpllc0 IDCR2 0x01C1 sdr0_xplld0 IDCR2 0x01C2 sdr0_xcr1 IDCR2 0x01C3 sdr0_xpllc1 IDCR2 0x01C4 sdr0_xplld1 IDCR2 0x01C5 sdr0_xcr2 IDCR2 0x01C6 sdr0_xpllc2 IDCR2 0x01C7 sdr0_xplld2 IDCR2 0x01C8 sdr0_srst IDCR2 0x0200 sdr0_slpipe IDCR2 0x0220 sdr0_amp0 IDCR2 0x0240 sdr0_amp1 IDCR2 0x0241 sdr0_mirq0 IDCR2 0x0260 sdr0_mirq1 IDCR2 0x0261 sdr0_maltbl IDCR2 0x0280 sdr0_malrbl IDCR2 0x02A0 sdr0_maltbs IDCR2 0x02C0 sdr0_malrbs IDCR2 0x02E0 sdr0_cust0 IDCR2 0x4000 sdr0_sdstp4 IDCR2 0x4001 sdr0_cust1 IDCR2 0x4002 sdr0_sdstp5 IDCR2 0x4003 sdr0_cust2 IDCR2 0x4004 sdr0_sdstp6 IDCR2 0x4005 sdr0_cust3 IDCR2 0x4006 sdr0_sdstp7 IDCR2 0x4007 sdr0_pfc0 IDCR2 0x4100 sdr0_pfc1 IDCR2 0x4101 sdr0_plbtr IDCR2 0x4200 sdr0_mfr IDCR2 0x4300 ; ; ; DDR-SDRAM Controller DCRs ; mcif0_mcstat IDCR3 0x0014 mcif0_mcopt1 IDCR3 0x0020 mcif0_mcopt2 IDCR3 0x0021 mcif0_modt0 IDCR3 0x0022 mcif0_modt1 IDCR3 0x0023 mcif0_codt IDCR3 0x0026 mcif0_vvpr IDCR3 0x0027 ;mcif0_opar1 IDCR3 0x0028 ;mcif0_opar2 IDCR3 0x0029 mcif0_rtr IDCR3 0x0030 mcif0_pmit IDCR3 0x0034 mcif0_mb0cf IDCR3 0x0040 mcif0_mb1cf IDCR3 0x0044 mcif0_initplr0 IDCR3 0x0050 mcif0_initplr1 IDCR3 0x0051 mcif0_initplr2 IDCR3 0x0052 mcif0_initplr3 IDCR3 0x0053 mcif0_initplr4 IDCR3 0x0054 mcif0_initplr5 IDCR3 0x0055 mcif0_initplr6 IDCR3 0x0056 mcif0_initplr7 IDCR3 0x0057 mcif0_initplr8 IDCR3 0x0058 mcif0_initplr9 IDCR3 0x0059 mcif0_initplr10 IDCR3 0x005A mcif0_initplr11 IDCR3 0x005B mcif0_initplr12 IDCR3 0x005C mcif0_initplr13 IDCR3 0x005D mcif0_initplr14 IDCR3 0x005E mcif0_initplr15 IDCR3 0x005F mcif0_rqdc IDCR3 0x0070 mcif0_rfdc IDCR3 0x0074 mcif0_rdcc IDCR3 0x0078 mcif0_dlcr IDCR3 0x007A mcif0_clktr IDCR3 0x0080 mcif0_wrdtr IDCR3 0x0081 mcif0_sdtr1 IDCR3 0x0085 mcif0_sdtr2 IDCR3 0x0086 mcif0_sdtr3 IDCR3 0x0087 mcif0_mmode IDCR3 0x0088 mcif0_memode IDCR3 0x0089 mcif0_ecces IDCR3 0x0098 ; ; ; External Bus Controller DCRs ; ebc0_b0cr IDCR4 0x00 ebc0_b1cr IDCR4 0x01 ebc0_b2cr IDCR4 0x02 ebc0_b0ap IDCR4 0x10 ebc0_b1ap IDCR4 0x11 ebc0_b2ap IDCR4 0x12 ebc0_bear IDCR4 0x20 ebc0_besr IDCR4 0x21 ebc0_cfg IDCR4 0x23 ebc0_cid IDCR4 0x24 ;
Jeff Stevens wrote:
Does anyone know where I can get a BDI2000 config
file
for AMCC's Luan eval board, and a BDI2000 reg file
for
the 440SP?
Thanks, Jeff jsteve17@yahoo.com
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participants (3)
-
Jeff Stevens -
John Otken -
Jon Loeliger