This driver works with the sdhci controller present on TI's AM65x devices. Change the name to make this clearer and match the compatible with kernel.

Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- configs/am65x_evm_a53_defconfig | 2 +- configs/am65x_evm_r5_defconfig | 2 +- drivers/mmc/Kconfig | 8 ++--- drivers/mmc/Makefile | 2 +- .../mmc/{k3_arsan_sdhci.c => am654_sdhci.c} | 36 +++++++++---------- 5 files changed, 25 insertions(+), 25 deletions(-) rename drivers/mmc/{k3_arsan_sdhci.c => am654_sdhci.c} (68%)

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index a17cf7cb50..6db3dac4c7 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -54,7 +54,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_K3_ARASAN=y +CONFIG_MMC_SDHCI_AM654=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 54d1241adf..d82192911a 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -62,7 +62,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_K3_ARASAN=y +CONFIG_MMC_SDHCI_AM654=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index fbd13964a0..12b9356f0c 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -415,14 +415,14 @@ config MMC_SDHCI_CADENCE

If unsure, say N.

-config MMC_SDHCI_K3_ARASAN - bool "Arasan SDHCI controller for TI's K3 based SoCs" +config MMC_SDHCI_AM654 + bool "SDHCI Controller on TI's Am654 devices" depends on ARCH_K3 depends on MMC_SDHCI depends on DM_MMC && OF_CONTROL && BLK help - Support for Arasan SDHCI host controller on Texas Instruments' - K3 family based SoC platforms + Support for Secure Digital Host Controller Interface (SDHCI) + controllers present on TI's AM654 SOCs.

config MMC_SDHCI_KONA bool "SDHCI support on Broadcom KONA platform" diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 801a26d821..d85e0ff92f 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o -obj-$(CONFIG_MMC_SDHCI_K3_ARASAN) += k3_arsan_sdhci.o +obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o obj-$(CONFIG_MMC_SDHCI_MSM) += msm_sdhci.o obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o diff --git a/drivers/mmc/k3_arsan_sdhci.c b/drivers/mmc/am654_sdhci.c similarity index 68% rename from drivers/mmc/k3_arsan_sdhci.c rename to drivers/mmc/am654_sdhci.c index 785ba135c7..3afdb58293 100644 --- a/drivers/mmc/k3_arsan_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -12,17 +12,17 @@ #include <power-domain.h> #include <sdhci.h>

-#define K3_ARASAN_SDHCI_MIN_FREQ 0 +#define AM654_SDHCI_MIN_FREQ 400000

-struct k3_arasan_sdhci_plat { +struct am654_sdhci_plat { struct mmc_config cfg; struct mmc mmc; unsigned int f_max; };

-static int k3_arasan_sdhci_probe(struct udevice *dev) +static int am654_sdhci_probe(struct udevice *dev) { - struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); struct power_domain sdhci_pwrdmn; @@ -60,7 +60,7 @@ static int k3_arasan_sdhci_probe(struct udevice *dev) host->max_clk = clock;

ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, - K3_ARASAN_SDHCI_MIN_FREQ); + AM654_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; if (ret) return ret; @@ -71,9 +71,9 @@ static int k3_arasan_sdhci_probe(struct udevice *dev) return sdhci_probe(dev); }

-static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +static int am654_sdhci_ofdata_to_platdata(struct udevice *dev) { - struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev);

host->name = dev->name; @@ -84,26 +84,26 @@ static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev) return 0; }

-static int k3_arasan_sdhci_bind(struct udevice *dev) +static int am654_sdhci_bind(struct udevice *dev) { - struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct am654_sdhci_plat *plat = dev_get_platdata(dev);

return sdhci_bind(dev, &plat->mmc, &plat->cfg); }

-static const struct udevice_id k3_arasan_sdhci_ids[] = { - { .compatible = "arasan,sdhci-5.1" }, +static const struct udevice_id am654_sdhci_ids[] = { + { .compatible = "ti,am654-sdhci-5.1" }, { } };

-U_BOOT_DRIVER(k3_arasan_sdhci_drv) = { - .name = "k3_arasan_sdhci", +U_BOOT_DRIVER(am654_sdhci_drv) = { + .name = "am654_sdhci", .id = UCLASS_MMC, - .of_match = k3_arasan_sdhci_ids, - .ofdata_to_platdata = k3_arasan_sdhci_ofdata_to_platdata, + .of_match = am654_sdhci_ids, + .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata, .ops = &sdhci_ops, - .bind = k3_arasan_sdhci_bind, - .probe = k3_arasan_sdhci_probe, + .bind = am654_sdhci_bind, + .probe = am654_sdhci_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), - .platdata_auto_alloc_size = sizeof(struct k3_arasan_sdhci_plat), + .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat), };

In device nodes with more than one entry in the reg property, it is sometimes useful to regmap only of the entries. Add an API regmap_init_mem_index() to facilitate this.

Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/core/regmap.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/regmap.h | 2 ++ 2 files changed, 44 insertions(+)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 5ef0f71c8b..d1d12eef38 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -108,6 +108,48 @@ static int init_range(ofnode node, struct regmap_range *range, int addr_len, return 0; }

+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index) +{ + struct regmap *map; + int addr_len, size_len; + int ret; + + addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); + if (addr_len < 0) { + debug("%s: Error while reading the addr length (ret = %d)\n", + ofnode_get_name(node), addr_len); + return addr_len; + } + + size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + if (size_len < 0) { + debug("%s: Error while reading the size length: (ret = %d)\n", + ofnode_get_name(node), size_len); + return size_len; + } + + map = regmap_alloc(1); + if (!map) + return -ENOMEM; + + ret = init_range(node, map->ranges, addr_len, size_len, index); + if (ret) + return ret; + + if (ofnode_read_bool(node, "little-endian")) + map->endianness = REGMAP_LITTLE_ENDIAN; + else if (ofnode_read_bool(node, "big-endian")) + map->endianness = REGMAP_BIG_ENDIAN; + else if (ofnode_read_bool(node, "native-endian")) + map->endianness = REGMAP_NATIVE_ENDIAN; + else /* Default: native endianness */ + map->endianness = REGMAP_NATIVE_ENDIAN; + + *mapp = map; + + return ret; +} + int regmap_init_mem(ofnode node, struct regmap **mapp) { struct regmap_range *range; diff --git a/include/regmap.h b/include/regmap.h index b2b733fda6..3cd97d3b94 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -280,6 +280,8 @@ int regmap_init_mem(ofnode node, struct regmap **mapp); int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, struct regmap **mapp);

+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index); + /** * regmap_get_range() - Obtain the base memory address of a regmap range *

Add Support for masking some bits in the capabilities register of a host controller.

Also remove the redundant readl() into caps1.

Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/sdhci.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index cdeba914f9..c8a8a299ba 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -8,6 +8,7 @@ */

#include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <mmc.h> @@ -561,8 +562,15 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, u32 f_max, u32 f_min) { u32 caps, caps_1 = 0; + u32 mask[2] = {0}; + int ret; + + ret = dev_read_u32_array(host->mmc->dev, "sdhci-caps-mask", + mask, 2); + if (ret && ret != -1) + return ret;

- caps = sdhci_readl(host, SDHCI_CAPABILITIES); + caps = ~mask[1] & sdhci_readl(host, SDHCI_CAPABILITIES);

#ifdef CONFIG_MMC_SDHCI_SDMA if (!(caps & SDHCI_CAN_DO_SDMA)) { @@ -584,7 +592,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,

/* Check whether the clock multiplier is supported or not */ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + caps_1 = ~mask[0] & sdhci_readl(host, SDHCI_CAPABILITIES_1); host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; } @@ -641,9 +649,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_HS_52MHz; }

- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - if (!(cfg->voltages & MMC_VDD_165_195) || (host->quirks & SDHCI_QUIRK_NO_1_8_V)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |

With changes in the driver requiring phy related properties, add the same for the SD card node to prevent breaking boot with the driver update.

Signed-off-by: Faiz Abbas faiz4000@gmail.com Reviewed-by: Tom Rini trini@konsulko.com --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index f53fe463ac..95e3aad646 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -33,6 +33,8 @@ clocks = <&k3_clks 48 1>; power-domains = <&k3_pds 48>; max-frequency = <25000000>; + ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; };

}; @@ -129,4 +131,5 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; sdhci-caps-mask = <0x7 0x0>; + ti,driver-strength-ohm = <50>; };

Add support in the driver for handling phy specific registers.

Signed-off-by: Faiz Abbas faiz4000@gmail.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 224 +++++++++++++++++++++++++++++++++++++- 2 files changed, 222 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 12b9356f0c..45eb1cd09a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -420,6 +420,7 @@ config MMC_SDHCI_AM654 depends on ARCH_K3 depends on MMC_SDHCI depends on DM_MMC && OF_CONTROL && BLK + depends on REGMAP help Support for Secure Digital Host Controller Interface (SDHCI) controllers present on TI's AM654 SOCs. diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 69914deb0c..123f4c3e8b 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -10,16 +10,190 @@ #include <dm.h> #include <malloc.h> #include <power-domain.h> +#include <regmap.h> #include <sdhci.h>

+/* CTL_CFG Registers */ +#define CTL_CFG_2 0x14 + +#define SLOTTYPE_MASK GENMASK(31, 30) +#define SLOTTYPE_EMBEDDED BIT(30) + +/* PHY Registers */ +#define PHY_CTRL1 0x100 +#define PHY_CTRL2 0x104 +#define PHY_CTRL3 0x108 +#define PHY_CTRL4 0x10C +#define PHY_CTRL5 0x110 +#define PHY_CTRL6 0x114 +#define PHY_STAT1 0x130 +#define PHY_STAT2 0x134 + +#define IOMUX_ENABLE_SHIFT 31 +#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) +#define OTAPDLYENA_SHIFT 20 +#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) +#define OTAPDLYSEL_SHIFT 12 +#define OTAPDLYSEL_MASK GENMASK(15, 12) +#define STRBSEL_SHIFT 24 +#define STRBSEL_MASK GENMASK(27, 24) +#define SEL50_SHIFT 8 +#define SEL50_MASK BIT(SEL50_SHIFT) +#define SEL100_SHIFT 9 +#define SEL100_MASK BIT(SEL100_SHIFT) +#define DLL_TRIM_ICP_SHIFT 4 +#define DLL_TRIM_ICP_MASK GENMASK(7, 4) +#define DR_TY_SHIFT 20 +#define DR_TY_MASK GENMASK(22, 20) +#define ENDLL_SHIFT 1 +#define ENDLL_MASK BIT(ENDLL_SHIFT) +#define DLLRDY_SHIFT 0 +#define DLLRDY_MASK BIT(DLLRDY_SHIFT) +#define PDB_SHIFT 0 +#define PDB_MASK BIT(PDB_SHIFT) +#define CALDONE_SHIFT 1 +#define CALDONE_MASK BIT(CALDONE_SHIFT) +#define RETRIM_SHIFT 17 +#define RETRIM_MASK BIT(RETRIM_SHIFT) + +#define DRIVER_STRENGTH_50_OHM 0x0 +#define DRIVER_STRENGTH_33_OHM 0x1 +#define DRIVER_STRENGTH_66_OHM 0x2 +#define DRIVER_STRENGTH_100_OHM 0x3 +#define DRIVER_STRENGTH_40_OHM 0x4 + #define AM654_SDHCI_MIN_FREQ 400000

struct am654_sdhci_plat { struct mmc_config cfg; struct mmc mmc; unsigned int f_max; + struct regmap *base; + bool non_removable; + u32 otap_del_sel; + u32 trm_icp; + u32 drv_strength; + bool dll_on; };

+static int am654_sdhci_set_ios_post(struct sdhci_host *host) +{ + struct udevice *dev = host->mmc->dev; + struct am654_sdhci_plat *plat = dev_get_platdata(dev); + unsigned int speed = host->mmc->clock; + int sel50, sel100; + u32 mask, val; + int ret; + + /* Reset SD Clock Enable */ + val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + val &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, val, SDHCI_CLOCK_CONTROL); + + /* power off phy */ + if (plat->dll_on) { + regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0); + + plat->dll_on = false; + } + + /* restart clock */ + sdhci_set_clock(host->mmc, speed); + + /* switch phy back on */ + if (speed > AM654_SDHCI_MIN_FREQ) { + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + val = (1 << OTAPDLYENA_SHIFT) | + (plat->otap_del_sel << OTAPDLYSEL_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL4, + mask, val); + switch (speed) { + case 200000000: + sel50 = 0; + sel100 = 0; + break; + case 100000000: + sel50 = 0; + sel100 = 1; + break; + default: + sel50 = 1; + sel100 = 0; + } + + /* Configure PHY DLL frequency */ + mask = SEL50_MASK | SEL100_MASK; + val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL5, + mask, val); + /* Configure DLL TRIM */ + mask = DLL_TRIM_ICP_MASK; + val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; + + /* Configure DLL driver strength */ + mask |= DR_TY_MASK; + val |= plat->drv_strength << DR_TY_SHIFT; + regmap_update_bits(plat->base, PHY_CTRL1, + mask, val); + /* Enable DLL */ + regmap_update_bits(plat->base, PHY_CTRL1, + ENDLL_MASK, 0x1 << ENDLL_SHIFT); + /* + * Poll for DLL ready. Use a one second timeout. + * Works in all experiments done so far + */ + ret = regmap_read_poll_timeout(plat->base, + PHY_STAT1, val, + val & DLLRDY_MASK, + 1000000); + if (ret) + return ret; + + plat->dll_on = true; + } + + return 0; +} + +const struct sdhci_ops am654_sdhci_ops = { + .set_ios_post = &am654_sdhci_set_ios_post, +}; + +int am654_sdhci_init(struct am654_sdhci_plat *plat) +{ + int ctl_cfg_2 = 0; + u32 mask, val; + int ret; + + /* Reset OTAP to default value */ + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0); + + regmap_read(plat->base, PHY_STAT1, &val); + if (~val & CALDONE_MASK) { + /* Calibrate IO lines */ + regmap_update_bits(plat->base, PHY_CTRL1, + PDB_MASK, PDB_MASK); + ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, + val, val & CALDONE_MASK, + 20); + if (ret) + return ret; + } + + /* Enable pins by setting IO mux to 0 */ + regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0); + + /* Set slot type based on SD or eMMC */ + if (plat->non_removable) + ctl_cfg_2 = SLOTTYPE_EMBEDDED; + + regmap_update_bits(plat->base, CTL_CFG_2, ctl_cfg_2, + SLOTTYPE_MASK); + + return 0; +} + static int am654_sdhci_probe(struct udevice *dev) { struct am654_sdhci_plat *plat = dev_get_platdata(dev); @@ -58,13 +232,18 @@ static int am654_sdhci_probe(struct udevice *dev)

ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, AM654_SDHCI_MIN_FREQ); - host->mmc = &plat->mmc; if (ret) return ret; + host->mmc = &plat->mmc; + host->ops = &am654_sdhci_ops; host->mmc->priv = host; host->mmc->dev = dev; upriv->mmc = host->mmc;

+ regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1); + + am654_sdhci_init(plat); + return sdhci_probe(dev); }

@@ -72,11 +251,50 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice *dev) { struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; + u32 drv_strength; + int ret;

host->name = dev->name; host->ioaddr = (void *)dev_read_addr(dev); - host->bus_width = dev_read_u32_default(dev, "bus-width", 4); - plat->f_max = dev_read_u32_default(dev, "max-frequency", 0); + plat->non_removable = !dev_read_bool(dev, "non-removable"); + + ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp); + if (ret) + return ret; + + ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel); + if (ret) + return ret; + + ret = dev_read_u32(dev, "ti,driver-strength-ohm", &drv_strength); + if (ret) + return ret; + + switch (drv_strength) { + case 50: + plat->drv_strength = DRIVER_STRENGTH_50_OHM; + break; + case 33: + plat->drv_strength = DRIVER_STRENGTH_33_OHM; + break; + case 66: + plat->drv_strength = DRIVER_STRENGTH_66_OHM; + break; + case 100: + plat->drv_strength = DRIVER_STRENGTH_100_OHM; + break; + case 40: + plat->drv_strength = DRIVER_STRENGTH_40_OHM; + break; + default: + dev_err(dev, "Invalid driver strength\n"); + return -EINVAL; + } + + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret;

return 0; }

From: Faiz Abbas faiz4000@gmail.com

The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific to arasan/zynq controllers. Add the same to sdhci.h.

Also create a common API to set UHS timings in HOST_CONTROL2.

Signed-off-by: Faiz Abbas faiz4000@gmail.com --- drivers/mmc/sdhci.c | 28 ++++++++++++++++++++++++++++ drivers/mmc/zynq_sdhci.c | 31 ++----------------------------- include/sdhci.h | 19 ++++++++++++++++++- 3 files changed, 48 insertions(+), 30 deletions(-)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 45576502aa..2a6d9e515f 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -451,6 +451,34 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); }

+void sdhci_set_uhs_timing(struct sdhci_host *host) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u32 reg; + + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; + + switch (mmc->selected_mode) { + case UHS_SDR50: + case MMC_HS_52: + reg |= SDHCI_CTRL_UHS_SDR50; + break; + case UHS_DDR50: + case MMC_DDR_52: + reg |= SDHCI_CTRL_UHS_DDR50; + break; + case UHS_SDR104: + case MMC_HS_200: + reg |= SDHCI_CTRL_UHS_SDR104; + break; + default: + reg |= SDHCI_CTRL_UHS_SDR12; + } + + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); +} + #ifdef CONFIG_DM_MMC static int sdhci_set_ios(struct udevice *dev) { diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index b05334dfc8..662b001a29 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -49,11 +49,6 @@ static const u8 mode2timing[] = { [MMC_HS_200] = MMC_HS200_BUS_SPEED, };

-#define SDHCI_HOST_CTRL2 0x3E -#define SDHCI_CTRL2_MODE_MASK 0x7 -#define SDHCI_18V_SIGNAL 0x8 -#define SDHCI_CTRL_EXEC_TUNING 0x0040 -#define SDHCI_CTRL_TUNED_CLK 0x80 #define SDHCI_TUNING_LOOP_COUNT 40

static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid) @@ -191,30 +186,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) }

if (mmc->selected_mode > SD_HS && - mmc->selected_mode <= UHS_DDR50) { - reg = sdhci_readw(host, SDHCI_HOST_CTRL2); - reg &= ~SDHCI_CTRL2_MODE_MASK; - switch (mmc->selected_mode) { - case UHS_SDR12: - reg |= UHS_SDR12_BUS_SPEED; - break; - case UHS_SDR25: - reg |= UHS_SDR25_BUS_SPEED; - break; - case UHS_SDR50: - reg |= UHS_SDR50_BUS_SPEED; - break; - case UHS_SDR104: - reg |= UHS_SDR104_BUS_SPEED; - break; - case UHS_DDR50: - reg |= UHS_DDR50_BUS_SPEED; - break; - default: - break; - } - sdhci_writew(host, reg, SDHCI_HOST_CTRL2); - } + mmc->selected_mode <= UHS_DDR50) + sdhci_set_uhs_timing(host); } #endif

diff --git a/include/sdhci.h b/include/sdhci.h index 725520b0b4..88e2dd7294 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -144,7 +144,23 @@

#define SDHCI_ACMD12_ERR 0x3C

-/* 3E-3F reserved */ +#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_CTRL_UHS_MASK 0x0007 +#define SDHCI_CTRL_UHS_SDR12 0x0000 +#define SDHCI_CTRL_UHS_SDR25 0x0001 +#define SDHCI_CTRL_UHS_SDR50 0x0002 +#define SDHCI_CTRL_UHS_SDR104 0x0003 +#define SDHCI_CTRL_UHS_DDR50 0x0004 +#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_VDD_180 0x0008 +#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 +#define SDHCI_CTRL_DRV_TYPE_B 0x0000 +#define SDHCI_CTRL_DRV_TYPE_A 0x0010 +#define SDHCI_CTRL_DRV_TYPE_C 0x0020 +#define SDHCI_CTRL_DRV_TYPE_D 0x0030 +#define SDHCI_CTRL_EXEC_TUNING 0x0040 +#define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000

#define SDHCI_CAPABILITIES 0x40 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F @@ -423,6 +439,7 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min); #endif /* !CONFIG_BLK */

+void sdhci_set_uhs_timing(struct sdhci_host *host); #ifdef CONFIG_DM_MMC /* Export the operations to drivers */ int sdhci_probe(struct udevice *dev);

From: Faiz Abbas faiz4000@gmail.com

Add a platform specific set_control_reg() callback to help switch to UHS speed modes.

Signed-off-by: Faiz Abbas faiz4000@gmail.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/am654_sdhci.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 123f4c3e8b..583cd37c5f 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -76,6 +76,21 @@ struct am654_sdhci_plat { bool dll_on; };

+static void am654_sdhci_set_control_reg(struct sdhci_host *host) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u32 reg; + + if (IS_SD(host->mmc) && + mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + } + + sdhci_set_uhs_timing(host); +} + static int am654_sdhci_set_ios_post(struct sdhci_host *host) { struct udevice *dev = host->mmc->dev; @@ -156,7 +171,8 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) }

const struct sdhci_ops am654_sdhci_ops = { - .set_ios_post = &am654_sdhci_set_ios_post, + .set_ios_post = &am654_sdhci_set_ios_post, + .set_control_reg = &am654_sdhci_set_control_reg, };

int am654_sdhci_init(struct am654_sdhci_plat *plat)