[U-Boot] [PATCH] ppc4xx: HCU5 board: add register dump
Adds a HCU5 board specific cmd reghcu5 to dump about 140 internal register which define the HW configuration. Needed for documentation purposes and to compare different settings.
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com --- board/netstal/hcu5/Makefile | 2 +- board/netstal/hcu5/cmd_reghcu5.c | 283 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 284 insertions(+), 1 deletions(-) create mode 100644 board/netstal/hcu5/cmd_reghcu5.c
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 4456771..670b100 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -25,7 +25,7 @@ LIB = $(obj)lib$(BOARD).a
# NOBJS : Netstal common objects NOBJS = nm_bsp.o -COBJS = $(BOARD).o sdram.o +COBJS = $(BOARD).o sdram.o cmd_reghcu5.o SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c)) diff --git a/board/netstal/hcu5/cmd_reghcu5.c b/board/netstal/hcu5/cmd_reghcu5.c new file mode 100644 index 0000000..ca330f7 --- /dev/null +++ b/board/netstal/hcu5/cmd_reghcu5.c @@ -0,0 +1,283 @@ +/* + *(C) Copyright 2005-2008 Netstal Maschinen AG + * Bruno Hars (Bruno.Hars@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/************************************************************************ + * cmd_reghcu5.c - CPU Register Dump for HCU5 board with PPC440EPx + ***********************************************************************/ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> + +enum REGISTER_TYPE { + DCR, /* Directly Accessed DCR's */ + IDCR1, /* Indirectly Accessed DCR to SDRAM0_CFGADDR and SDRAM0_CFGDATA */ + IDCR2, /* Indirectly Accessed DCR to EBC0_CFGADDR and EBC0_CFGDATA */ + IDCR3, /* Indirectly Accessed DCR to EBM0_CFGADDR and EBM0_CFGDATA */ + IDCR4, /* Indirectly Accessed DCR to PPM0_CFGADDR and PPM0_CFGDATA */ + IDCR5, /* Indirectly Accessed DCR to CPR0_CFGADDR and CPR0_CFGDATA */ + IDCR6, /* Indirectly Accessed DCR to SDR0_CFGADDR and SDR0_CFGDATA */ + MM /* Directly Accessed MMIO Register */ +}; + +struct cpu_register { + char *name; + enum REGISTER_TYPE type; + unsigned long address; +}; + +/* PPC440EPx registers ordered for output + * name type addr size + * ------------------------------------------- + */ +const struct cpu_register ppc440epx_reg[] = { + {"EBC0_B0CR ", IDCR2, PB0CR}, + {"EBC0_B1CR ", IDCR2, PB1CR}, + {"EBC0_B2CR ", IDCR2, PB2CR}, + {"EBC0_B3CR ", IDCR2, PB3CR}, + {"EBC0_B4CR ", IDCR2, PB4CR}, + {"EBC0_B5CR ", IDCR2, PB5CR}, + {"EBC0_B0AP ", IDCR2, PB0AP}, + {"EBC0_B1AP ", IDCR2, PB1AP}, + {"EBC0_B2AP ", IDCR2, PB2AP}, + {"EBC0_B3AP ", IDCR2, PB3AP}, + {"EBC0_B4AP ", IDCR2, PB4AP}, + {"EBC0_B5AP ", IDCR2, PB5AP}, + {"EBC0_CFG ", IDCR2, 0x23}, + {"SDR0_SDSTP0 ", IDCR6, SDR0_SDSTP0}, + {"SDR0_SDSTP1 ", IDCR6, SDR0_SDSTP1}, + {"SDR0_SDSTP2 ", IDCR6, 0x4001}, + {"SDR0_SDSTP3 ", IDCR6, 0x4003}, + {"SDR0_CUST0 ", IDCR6, SDR0_CUST0}, + {"SDR0_CUST1 ", IDCR6, SDR0_CUST1}, + {"SDR0_EBC0 ", IDCR6, 0x0100}, + {"SDR0_AMP0 ", IDCR6, 0x0240}, + {"SDR0_AMP1 ", IDCR6, 0x0241}, + {"SDR0_CP440 ", IDCR6, SDR0_CP440}, + {"SDR0_CRYP0 ", IDCR6, 0x4500}, + {"SDR0_DDRCFG ", IDCR6, 0x00E0}, + {"SDR0_EMAC0RXST ", IDCR6, 0x4301}, + {"SDR0_EMAC0TXST ", IDCR6, 0x4302}, + {"SDR0_MFR ", IDCR6, SDR0_MFR}, + {"SDR0_PCI0 ", IDCR6, SDR0_PCI0}, + {"SDR0_PFC0 ", IDCR6, SDR0_PFC0}, + {"SDR0_PFC1 ", IDCR6, SDR0_PFC1}, + {"SDR0_PFC2 ", IDCR6, SDR0_PFC2}, + {"SDR0_PFC4 ", IDCR6, SDR0_PFC4}, + {"SDR0_UART0 ", IDCR6, SDR0_UART0}, + {"SDR0_UART1 ", IDCR6, SDR0_UART1}, + {"SDR0_UART2 ", IDCR6, SDR0_UART2}, + {"SDR0_UART3 ", IDCR6, SDR0_UART3}, + {"DDR0_02 ", IDCR1, 2}, + {"DDR0_00 ", IDCR1, 0}, + {"DDR0_01 ", IDCR1, 1}, + {"DDR0_03 ", IDCR1, 3}, + {"DDR0_04 ", IDCR1, 4}, + {"DDR0_05 ", IDCR1, 5}, + {"DDR0_06 ", IDCR1, 6}, + {"DDR0_07 ", IDCR1, 7}, + {"DDR0_08 ", IDCR1, 8}, + {"DDR0_09 ", IDCR1, 9}, + {"DDR0_10 ", IDCR1, 10}, + {"DDR0_11 ", IDCR1, 11}, + {"DDR0_12 ", IDCR1, 12}, + {"DDR0_14 ", IDCR1, 14}, + {"DDR0_17 ", IDCR1, 17}, + {"DDR0_18 ", IDCR1, 18}, + {"DDR0_19 ", IDCR1, 19}, + {"DDR0_20 ", IDCR1, 20}, + {"DDR0_21 ", IDCR1, 21}, + {"DDR0_22 ", IDCR1, 22}, + {"DDR0_23 ", IDCR1, 23}, + {"DDR0_24 ", IDCR1, 24}, + {"DDR0_25 ", IDCR1, 25}, + {"DDR0_26 ", IDCR1, 26}, + {"DDR0_27 ", IDCR1, 27}, + {"DDR0_28 ", IDCR1, 28}, + {"DDR0_31 ", IDCR1, 31}, + {"DDR0_32 ", IDCR1, 32}, + {"DDR0_33 ", IDCR1, 33}, + {"DDR0_34 ", IDCR1, 34}, + {"DDR0_35 ", IDCR1, 35}, + {"DDR0_36 ", IDCR1, 36}, + {"DDR0_37 ", IDCR1, 37}, + {"DDR0_38 ", IDCR1, 38}, + {"DDR0_39 ", IDCR1, 39}, + {"DDR0_40 ", IDCR1, 40}, + {"DDR0_41 ", IDCR1, 41}, + {"DDR0_42 ", IDCR1, 42}, + {"DDR0_43 ", IDCR1, 43}, + {"DDR0_44 ", IDCR1, 44}, + {"CPM0_ER ", DCR, 0x0B0}, + {"CPM1_ER ", DCR, 0x0F0}, + {"CPR0_ICFG ", IDCR5, CPR0_ICFG}, + {"CPR0_MALD ", IDCR5, CPR0_MALD}, + {"CPR0_OPBD0 ", IDCR5, 0x00C0}, + {"CPR0_PERD0 ", IDCR5, 0x00E0}, + {"CPR0_PLLC0 ", IDCR5, 0x0040}, + {"CPR0_PLLD0 ", IDCR5, 0x0060}, + {"CPR0_PRIMAD0 ", IDCR5, 0x0080}, + {"CPR0_PRIMBD0 ", IDCR5, 0x00A0}, + {"CPR0_SPCID ", IDCR5, 0x0120}, + {"SPI0_MODE ", MM, 0xEF600900}, + {"IIC0_CLKDIV ", MM, 0xEF60070C}, + {"PCIL0_PMM0MA ", MM, 0xEF400004}, + {"PCIL0_PMM1MA ", MM, 0xEF400014}, + {"PCIL0_PTM1LA ", MM, 0xEF400034}, + {"PCIL0_PTM1MS ", MM, 0xEF400030}, + {"PCIL0_PTM2LA ", MM, 0xEF40003C}, + {"PCIL0_PTM2MS ", MM, 0xEF400038}, + {"MAL0_CFG ", DCR, MAL0_CFG}, + {"ZMII0_FER ", MM, 0xEF600D00}, + {"ZMII0_SSR ", MM, 0xEF600D04}, + {"EMAC0_IPGVR ", MM, 0xEF600E58}, + {"EMAC0_MR1 ", MM, 0xEF600E04}, + {"EMAC0_PTR ", MM, 0xEF600E2C}, + {"EMAC0_RWMR ", MM, 0xEF600E64}, + {"EMAC0_STACR ", MM, 0xEF600E5C}, + {"EMAC0_TMR0 ", MM, 0xEF600E08}, + {"EMAC0_TMR1 ", MM, 0xEF600E0C}, + {"EMAC0_TRTR ", MM, 0xEF600E60}, + {"EMAC1_MR1 ", MM, 0xEF600F04}, + {"GPIO0_OR ", MM, GPIO0_OR}, + {"GPIO1_OR ", MM, GPIO1_OR}, + {"GPIO0_TCR ", MM, GPIO0_TCR}, + {"GPIO1_TCR ", MM, GPIO1_TCR}, + {"GPIO0_ODR ", MM, GPIO0_ODR}, + {"GPIO1_ODR ", MM, GPIO1_ODR}, + {"GPIO0_OSRL ", MM, GPIO0_OSRL}, + {"GPIO0_OSRH ", MM, GPIO0_OSRH}, + {"GPIO1_OSRL ", MM, GPIO1_OSRL}, + {"GPIO1_OSRH ", MM, GPIO1_OSRH}, + {"GPIO0_TSRL ", MM, GPIO0_TSRL}, + {"GPIO0_TSRH ", MM, GPIO0_TSRH}, + {"GPIO1_TSRL ", MM, GPIO1_TSRL}, + {"GPIO1_TSRH ", MM, GPIO1_TSRH}, + {"GPIO0_IR ", MM, GPIO0_IR}, + {"GPIO1_IR ", MM, GPIO1_IR}, + {"GPIO0_ISR1L ", MM, GPIO0_ISR1L}, + {"GPIO0_ISR1H ", MM, GPIO0_ISR1H}, + {"GPIO1_ISR1L ", MM, GPIO1_ISR1L}, + {"GPIO1_ISR1H ", MM, GPIO1_ISR1H}, + {"GPIO0_ISR2L ", MM, GPIO0_ISR2L}, + {"GPIO0_ISR2H ", MM, GPIO0_ISR2H}, + {"GPIO1_ISR2L ", MM, GPIO1_ISR2L}, + {"GPIO1_ISR2H ", MM, GPIO1_ISR2H}, + {"GPIO0_ISR3L ", MM, GPIO0_ISR3L}, + {"GPIO0_ISR3H ", MM, GPIO0_ISR3H}, + {"GPIO1_ISR3L ", MM, GPIO1_ISR3L}, + {"GPIO1_ISR3H ", MM, GPIO1_ISR3H}, + {"SDR0_USB2PHY0CR", IDCR6, SDR0_USB2PHY0CR}, + {"SDR0_USB2H0CR ", IDCR6, SDR0_USB2H0CR}, + {"SDR0_USB2D0CR ", IDCR6, SDR0_USB2D0CR}, + {"PLB4A0_ACR ", DCR, 0x081}, + {"PLB4A1_ACR ", DCR, 0x089}, + {"PLB3A0_ACR ", DCR, 0x077}, + {"OPB2PLB40_BCTRL", DCR, 0x350}, + {"P4P3BO0_CFG ", DCR, 0x026} +}; + +/* + * CPU Register dump of PPC440EPx + * Output in order of struct ppc440epx_reg + */ +int do_reghcu5(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int i; + unsigned int n; + unsigned long value; + enum REGISTER_TYPE type; + + printf + ("\nRegister Dump PPC440EPx for comparison with document A0001492\n\n"); + n = sizeof(ppc440epx_reg) / sizeof(ppc440epx_reg[0]); + for (i = 0; i < n; i++) { + value = 0; + type = ppc440epx_reg[i].type; + switch (type) { + case DCR: /* Directly Accessed DCR's */ + switch (ppc440epx_reg[i].address) { + /* following list includes only registers included in struct */ + case 0x0b0: + value = mfdcr(0x0b0); + break; + case 0x0f0: + value = mfdcr(0x0f0); + break; + case 0x0180: + value = mfdcr(0x0180); + break; + case 0x081: + value = mfdcr(0x081); + break; + case 0x089: + value = mfdcr(0x089); + break; + case 0x077: + value = mfdcr(0x077); + break; + case 0x350: + value = mfdcr(0x350); + break; + case 0x026: + value = mfdcr(0x026); + break; + default: + printf("\nERROR: unknown DCR address: 0x%lX\n", + ppc440epx_reg[i].address); + break; + } + break; + case IDCR1: /* Indirectly Accessed DCR to SDRAM0_CFGADDR/DDR0_CFGDATA */ + mtdcr(SDRAM0_CFGADDR, ppc440epx_reg[i].address); + value = mfdcr(SDRAM0_CFGDATA); + break; + case IDCR2: /* Indirectly Accessed DCR to EBC0_CFGADDR/EBC0_CFGDATA */ + mtdcr(EBC0_CFGADDR, ppc440epx_reg[i].address); + value = mfdcr(EBC0_CFGDATA); + break; + case IDCR5: /* Indirectly Accessed DCR to CPR0_CFGADDR/CPR0_CFGDATA */ + mtdcr(CPR0_CFGADDR, ppc440epx_reg[i].address); + value = mfdcr(CPR0_CFGDATA); + break; + case IDCR6: /* Indirectly Accessed DCR to SDR0_CFGADDR/SDR0_CFGDATA */ + mtdcr(SDR0_CFGADDR, ppc440epx_reg[i].address); + value = mfdcr(SDR0_CFGDATA); + break; + case MM: /* Directly Accessed MMIO Register */ + value = + *(volatile unsigned long + *)(ppc440epx_reg[i].address); + break; + default: + printf + ("\nERROR: struct entry %d: unknown register type\n", + i); + break; + } + printf("0x%08lx %16s: 0x%08lx\n", ppc440epx_reg[i].address, + ppc440epx_reg[i].name, value); + } + return 0; +} + +/* define do_reghcu5 as u-boot command */ +U_BOOT_CMD(reghcu5, 2, 1, do_reghcu5, + "reghcu5 - print register information for HCU5\n",);
- CONFIG_SYS_BOOTMAPSZ for 16 instead of 8 MB, moved to common - baudrate back to 9600 for backward compatibility - HCU4: CONFIG_SYS_ICACHE_SACR_VALUE defined - CONFIG_VXWORKS_PREBOOT for HCU4 and MCU25 - HCU5: Add CPU and OCM POST
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com --- include/configs/hcu4.h | 9 ++------- include/configs/hcu5.h | 38 +++++++++++++++++++++++--------------- include/configs/mcu25.h | 8 ++------ include/configs/netstal-common.h | 9 ++++++--- 4 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 369b368..fddfebc 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 /* Do not set up locked dcache as init ram. */ #undef CONFIG_SYS_INIT_DCACHE_CS +#define CONFIG_SYS_ICACHE_SACR_VALUE 0x80000001
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ #define CONFIG_SYS_TEMP_STACK_OCM 1 @@ -200,6 +201,7 @@ /*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/ +#define CONFIG_VXWORKS_PREBOOT 1 #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -243,13 +245,6 @@ #define CONFIG_SYS_GPIO0_TCR 0x7FFE0000 /* GPIO value */ #define CONFIG_SYS_GPIO0_ODR 0x00E897FC /* GPIO value */
-/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ - /* Init Memory Controller: * * BR0/1 and OR0/1 (FLASH) diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 26d2d0c..6b90705 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -92,7 +92,7 @@ * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 9600 #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_UART1_CONSOLE
@@ -131,7 +131,9 @@ #define CONFIG_SYS_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ #define CONFIG_SYS_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */ #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ -#define CONFIG_DDR_ECC 1 /* enable ECC */ +/* warum gibt es Fehler mit #undef CONFIG_DDR_ECC (Hub) */ +#define CONFIG_DDR_ECC +#undef DISABLE_DDR_ECC_AFTER_POST /* disable ECC after POST tests */
/* Following two definitions must be kept in sync with config.h of vxWorks */ #define USER_RESERVED_MEM ( 0) /* in kB */ @@ -155,11 +157,12 @@ CONFIG_NETSTAL_DEF_ENV_POWERPC \ ""
-#define CONFIG_M88E1111_PHY 1 +/* HCU5 has a SMII for 10/100Mbps Micrel KS8001 */ +#define CONFIG_MICREL_KS8001_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 - -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR 2 +#define CONFIG_PHY_DYNAMIC_ANEG 1 +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_ADDR 1 /* PHY address */
/* USB */ #define CONFIG_USB_OHCI @@ -205,18 +208,30 @@ #define CONFIG_CMD_USB
/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_UART | \ +#define CONFIG_POST (CONFIG_SYS_POST_UART | \ CONFIG_SYS_POST_I2C | \ CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_OCM | \ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) +#define CONFIG_SYS_POST_MEMORY_EXTENDED /* 1 * in case of memory error execute extended test */ #define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
+#define CONFIG_SYS_OCM_SIZE (16 << 10) +#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 +#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 +#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 +#define CONFIG_SYS_OCM_STATUS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) + #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ +/* defining CONFIG_4xx_DCACHE leads to erros in memory_extended_tests */ +#undef CONFIG_WATCHDOG +/* Watchdog cannot be enabled, as it would be still enabled booting vxWorks */ +#undef CONFIG_4xx_DCACHE
#define CONFIG_SUPPORT_VFAT
@@ -255,13 +270,6 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - /*----------------------------------------------------------------------- * Flash *----------------------------------------------------------------------*/ diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index 5f31198..ef8a48c 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 /* Do not set up locked dcache as init ram. */ #undef CONFIG_SYS_INIT_DCACHE_CS +#define CONFIG_SYS_ICACHE_SACR_VALUE 0x80000001
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ #define CONFIG_SYS_TEMP_STACK_OCM 1 @@ -208,6 +209,7 @@ /*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/ +#define CONFIG_VXWORKS_PREBOOT 1 #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -256,12 +258,6 @@ #define CONFIG_SYS_GPIO0_OR 0x087FFFFF /* GPIO value */ #define CONFIG_SYS_GPIO0_TCR 0x7FFF8000 /* GPIO value */ #define CONFIG_SYS_GPIO0_ODR 0xFFFF0000 /* GPIO value */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* Init Memory Controller: * diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4bed7ae..0d1f6bb 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -92,6 +92,8 @@ #define CONFIG_CMD_REGINFO #define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_RESET_TO_RETRY +#define CONFIG_SHOW_ACTIVITY + /* * Miscellaneous configurable options */ @@ -142,10 +144,11 @@
/* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the 40x Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/* * Internal Definitions
Various cleanups for our boards: - vxworks_preboot to get clock input right for HCU4/MCU25 - reboot if SW-install-input is activated - clear vxWorks exception msg - HCU5: various HW-registers updated - HCU5: 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values - HCU5: PATCH HAB: WRITE PIPELINING OFF - HCU5: no pci_init if board has no PCI - MCU25: corrected address to read slot id - Lindent -pcs for hcu5.c
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com --- board/netstal/common/nm.h | 3 + board/netstal/common/nm_bsp.c | 14 ++++ board/netstal/hcu4/hcu4.c | 9 +++ board/netstal/hcu5/hcu5.c | 150 ++++++++++++++++++++++++++++------------- board/netstal/hcu5/sdram.c | 128 +++++++++++++++++++++++------------ board/netstal/mcu25/mcu25.c | 5 +- 6 files changed, 216 insertions(+), 93 deletions(-)
diff --git a/board/netstal/common/nm.h b/board/netstal/common/nm.h index 3dff1d6..128b0c3 100644 --- a/board/netstal/common/nm.h +++ b/board/netstal/common/nm.h @@ -18,12 +18,15 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */
+#include <exports.h> + extern void hcu_led_set(u32 value); extern u32 get_serial_number(void); extern u32 hcu_get_slot(void); extern int board_with_pci(void); extern void nm_show_print(int generation, int index, int hw_capabilities); extern void set_params_for_sw_install(int install_requested, char *board_name ); +extern int sys_install_requested(void); extern void common_misc_init_r(void);
enum { diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c index 237f4ed..e22cc58 100644 --- a/board/netstal/common/nm_bsp.c +++ b/board/netstal/common/nm_bsp.c @@ -37,6 +37,7 @@ generation_info generations[6] = { {HW_GENERATION_MCU20, "MCU20"}, {HW_GENERATION_MCU25, "MCU25"}, }; +static int installRequested;
void nm_show_print(int generation, int index, int hw_capabilities) { @@ -60,6 +61,7 @@ void nm_show_print(int generation, int index, int hw_capabilities)
void set_params_for_sw_install(int install_requested, char *board_name ) { + memset((void *)0x4300, 0, 0x100); /* clear vxWorks exception msg */ if (install_requested) { char string[128];
@@ -115,3 +117,15 @@ void common_misc_init_r(void) saveenv(); } } + +void show_activity(int arg) +{ + hcu_led_set(arg); + if( sys_install_requested() !=installRequested ) + { + printf("%s: installRequested 0x%x 0x%x\n", __FUNCTION__, + installRequested, + sys_install_requested()); + do_reset (); + } +} diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 40bec8e..75be92e 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define CPC0_CR0_VALUE 0x0030103c #define CPC0_CR1_VALUE 0x00004051 +#define CPCO_CR1_USE_EXTERNAL 0x00804051
int board_early_init_f (void) { @@ -154,6 +155,14 @@ int misc_init_r(void) return 0; }
+int vxworks_preboot(void) { + if (sys_install_requested()) + { + mtdcr(CPC0_CR1, CPCO_CR1_USE_EXTERNAL); + } + return 0; +} + phys_size_t initdram(int board_type) { long dram_size = 0; diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 836c034..46eb9d1 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -45,6 +45,9 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000) #define HCU_SW_INSTALL_REQUESTED 0x10
+#define OPB2PLB40_BCTRL 0x350 +#define P4P3BO0_CFG 0x026 + /* * This function is run very early, out of flash, and before devices are * initialized. It is called by lib_ppc/board.c:board_init_f by virtue @@ -74,17 +77,17 @@ int board_early_init_f(void)
mfcpr(CPR0_ICFG, cpr0icfg); if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { - mtcpr(CPR0_MALD, 0x02000000); - mtcpr(CPR0_OPBD, 0x02000000); - mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ - mtcpr(CPR0_PLLC, 0x40000238); - mtcpr(CPR0_PLLD, 0x01010414); + mtcpr(CPR0_MALD, 0x02000000); + mtcpr(CPR0_OPBD, 0x02000000); + mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ + mtcpr(CPR0_PLLC, 0x40000238); + mtcpr(CPR0_PLLD, 0x01010414); mtcpr(CPR0_PRIMAD, 0x01000000); mtcpr(CPR0_PRIMBD, 0x01000000); - mtcpr(CPR0_SPCID, 0x03000000); - mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ - mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); + mtcpr(CPR0_SPCID, 0x03000000); + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1 */ + mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
/* * Initiate system reset in debug control register DBCR @@ -92,7 +95,7 @@ int board_early_init_f(void) dbcr = mfspr(SPRN_DBCR0); mtspr(SPRN_DBCR0, dbcr | CHIP_RESET); } - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1 */ #endif mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xb8400000); @@ -155,6 +158,9 @@ int board_early_init_f(void) mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
+ /* 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values */ + mtsdr(SDR0_PFC2, 0x4642DB00); + /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350);
@@ -220,7 +226,6 @@ u32 get_serial_number(void) return in_be32(serial); }
- /* * hcu_get_slot */ @@ -230,7 +235,6 @@ u32 hcu_get_slot(void) return in_be16(slot) & 0x7f; }
- /* * misc_init_r. */ @@ -239,6 +243,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; + unsigned long addr;
#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ @@ -251,7 +256,8 @@ int misc_init_r(void) /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND + + 2 * CONFIG_ENV_SECT_SIZE -1, &flash_info[0]); #endif #endif @@ -266,59 +272,101 @@ int misc_init_r(void) mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr);
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
/* An 8-bit/60MHz interface is the only possible alternative * when connecting the Device to the PHY */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */
/* To enable the USB 2.0 Device function through the UTMI interface */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ + usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ + sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */
mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB2D0CR, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr);
- /*clear resets*/ + /*clear resets */ udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n");
+ /* Set priority for all PLB3 devices to 2. */ + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0xCF30B400) | 0x8A20B400); + + /* Set PLB3 arbiter to fair mode. */ + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ + + /* + * Set priority for all PLB4 devices to 2. + */ + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0xFFF3FD00) | 0xAAA2FD00); + + /* + * Set PLB4 arbiter to: + * fair mode, High Bus Utilisation Enabled, + * 2 Deep read pipe, Write pipeline disabled. + */ + addr = (mfdcr(PLB4_ACR & 0xFF000000) | 0xDA000000); + mtdcr(PLB4_ACR, addr); + + /* + * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. + * Workaround: Disable write pipelining to DDR SDRAM by setting + * PLB0_ACR[WRP] = 0. + */ + mtdcr(PLB0_ACR, + (mfdcr(PLB0_ACR) & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_DISABLED); + + /* Segment1 */ + mtdcr(PLB1_ACR, + (mfdcr(PLB1_ACR) & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_DISABLED); + + /* Set priority of OPB-to-PLB4 Bridge */ + mtdcr(OPB2PLB40_BCTRL, + (mfdcr(OPB2PLB40_BCTRL) & ~0xC0000000) | 0x80000000); + + /* Set priority of PLB4 to PLB3 Bridge */ + mtdcr(P4P3BO0_CFG, (mfdcr(P4P3BO0_CFG) & ~0x00C00000) | 0x00800000); + common_misc_init_r(); - set_params_for_sw_install( sys_install_requested(), "hcu5" ); + set_params_for_sw_install(sys_install_requested(), "hcu5"); /* We cannot easily enable trace before, as there are other * routines messing around with sdr0_pfc1. And I do not need it. */ if (mfspr(SPRN_DBCR0) & 0x80000000) { /* External debugger alive * enable trace facilty for Lauterbach - * CCR0[DTB]=0 Enable broadcast of trace information - * SDR0_PFC0[TRE] Trace signals are enabled instead of - * GPIO49-63 + * CCR0[DTB]=0 Enable broadcast of trace information + * SDR0_PFC0[TRE] Trace signals are enabled instead of + * GPIO49-63 */ - mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB)); - mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE); + mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~(CCR0_DTB)); + mtsdr(SDR0_PFC0, SDR0_PFC1 | SDR0_PFC0_TRE_ENABLE); } return 0; } + #ifdef CONFIG_PCI int board_with_pci(void) { @@ -344,7 +392,9 @@ int pci_pre_init(struct pci_controller *hose) { unsigned long addr;
- if (!board_with_pci()) { return 0; } + if (!board_with_pci()) { + return 0; + }
/* * Set priority for all PLB3 devices to 0. @@ -353,7 +403,7 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(SD0_AMP1, addr); mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
/* * Set priority for all PLB4 devices to 0. @@ -361,17 +411,17 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(SD0_AMP0, addr); mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); /* Sequoia */ + mtdcr(PLB4_ACR, addr); /* Sequoia */
/* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting * PLB0_ACR[WRP] = 0. */ - mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */ - mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
return board_with_pci(); } @@ -386,14 +436,16 @@ int pci_pre_init(struct pci_controller *hose) */ void pci_target_init(struct pci_controller *hose) { - if (!board_with_pci()) { return; } + if (!board_with_pci()) { + return; + } /* * Set up Direct MMIO registers * * PowerPC440EPX PCI Master configuration. * Map one 1Gig range of PLB/processor addresses to PCI memory space. * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address - * 0xA0000000-0xDFFFFFFF + * 0xA0000000-0xDFFFFFFF * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ @@ -448,7 +500,9 @@ void pci_target_init(struct pci_controller *hose) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; - if (!board_with_pci()) { return; } + if (!board_with_pci()) { + return; + }
/*--------------------------------------------------------------- * Write the PowerPC440 EP PCI Configuration regs. @@ -479,7 +533,7 @@ int is_pci_host(struct pci_controller *hose) { return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST) /* @@ -488,12 +542,12 @@ int is_pci_host(struct pci_controller *hose) */ int post_hotkeys_pressed(void) { - return 0; /* No hotkeys supported */ + return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t * bd) { ft_cpu_setup(blob, bd);
@@ -504,7 +558,7 @@ void ft_board_setup(void *blob, bd_t *bd) * Hardcoded flash setup: * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. */ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t * info) { if (banknum == 0) { /* non-CFI boot flash */ info->portwidth = 1; diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0546cd7..d52cf99 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,9 +36,11 @@ #include <asm/mmu.h> #include <asm/cache.h> #include <ppc440.h> +#include <post.h>
void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); +void zero_all_memory(unsigned long start_address, unsigned long num_bytes);
#define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -48,6 +50,11 @@ void dcbz_area(u32 start_address, u32 num_bytes); #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
+/* PPC440EPx Erratum CHIP_11: End of memory range area restricted access. + * -> no access to last 256 Bytes!!! + */ +#define NO_TOUCH_BYTES_AT_END 256 + void board_add_ram_info(int use_default) { PPC4xx_SYS_INFO board_cfg; @@ -114,29 +121,29 @@ static int wait_for_dlllock(void) ************************************************************************/ void sdram_panic(const char *reason) { - printf("\n%s: reason %s", __FUNCTION__, reason); + printf("\n%s: reason %s", __FUNCTION__, reason); hcu_led_set(0xff); while (1) { } /* Never return */ }
-#ifdef CONFIG_DDR_ECC void blank_string(int size) { int i;
- for (i=0; i<size; i++) + for (i = 0; i < size; i++) putc('\b'); - for (i=0; i<size; i++) + for (i = 0; i < size; i++) putc(' '); - for (i=0; i<size; i++) + for (i = 0; i < size; i++) putc('\b'); } + /*---------------------------------------------------------------------------+ - * program_ecc. + * zero_all_memory. *---------------------------------------------------------------------------*/ -static void program_ecc(unsigned long start_address, unsigned long num_bytes) +void zero_all_memory(unsigned long start_address, unsigned long num_bytes) { u32 val; char str[] = "ECC generation -"; @@ -149,15 +156,15 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) * Check whether vxWorks is using EDR logging, if yes zero * also PostMortem and user reserved memory */ - magicPtr = (u32 *)(start_address + num_bytes - - (CONFIG_PRAM*1024) + sizeof(u32)); + magicPtr = (u32 *) (start_address + num_bytes - + (CONFIG_PRAM * 1024) + sizeof(u32)); magic = in_be32(magicPtr); debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n", - __FUNCTION__, CONFIG_PRAM, - magicPtr, magic); + __FUNCTION__, CONFIG_PRAM, magicPtr, magic); if (magic == 0xbeefbabe) { - printf("%s: preserving at %p\n", __FUNCTION__, magicPtr); - num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; + printf("%s: preserving at %p\n", __FUNCTION__, + magicPtr); + num_bytes -= (CONFIG_PRAM * 1024) - PM_RESERVED_MEM; } } #endif @@ -186,23 +193,21 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
/* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); - mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | + mtsdram(DDR0_01, ((val & ~DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
return; } -#endif
- -/*********************************************************************** - * - * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) +/* + * post_memory_setup - + * used for memory post test and memory setup + */ +phys_size_t post_memory_setup(int ecc_enable) { unsigned int dram_size = 0;
+ printf("%s: ecc %d\n", __FUNCTION__, ecc_enable); mtsdram(DDR0_02, 0x00000000);
/* Values must be kept in sync with Excel-table <<A0001492.>> ! */ @@ -211,19 +216,26 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020307); - switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) { + switch (in_be16((u16 *) HCU_HW_VERSION_REGISTER) & + HCU_HW_SDRAM_CONFIG_MASK) { + case 2: + dram_size = 512 * 1024 * 1024; + mtsdram(DDR0_06, 0x0102C816); /* 512MB RAM */ + mtsdram(DDR0_11, 0x0017C800); /* 512MB RAM */ + mtsdram(DDR0_43, 0x030A0201); /* 512MB RAM */ + break; case 1: - dram_size = 256 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ - mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ - mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ + dram_size = 256 * 1024 * 1024; + mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ + mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ + mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ break; case 0: default: - dram_size = 128 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ - mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ - mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ + dram_size = 128 * 1024 * 1024; + mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ + mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ + mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ break; } mtsdram(DDR0_07, 0x00090100); @@ -242,11 +254,10 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_19, 0x1D1D1D1D); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); -#ifdef CONFIG_DDR_ECC - mtsdram(DDR0_22, ECC_RAM); -#else - mtsdram(DDR0_22, NO_ECC_RAM); -#endif + if (ecc_enable) + mtsdram(DDR0_22, ECC_RAM); + else + mtsdram(DDR0_22, NO_ECC_RAM);
mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01020001); @@ -258,26 +269,57 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); wait_for_dlllock(); - mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ + mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
/* - * Program tlb entries for this size (dynamic) + * Program TLB entries with caches enabled, for best performace */ remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20); - program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); +#ifdef CONFIG_4xx_DCACHE + program_tlb(CONFIG_SYS_SDRAM_BASE, 0, dram_size, 0); +#else + program_tlb(CONFIG_SYS_SDRAM_BASE, 0, dram_size, + TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); +#endif
/* * Setup 2nd TLB with same physical address but different virtual * address with cache enabled. This is done for fast ECC generation. */ - program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0); + program_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_DDR_CACHED_ADDR, + dram_size, 0);
-#ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ - program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size); + zero_all_memory(CONFIG_SYS_DDR_CACHED_ADDR, dram_size); + return dram_size - NO_TOUCH_BYTES_AT_END; +} + +/*********************************************************************** + * + * initdram -- 440EPx's DDR controller is a DENALI Core + * + ************************************************************************/ +phys_size_t initdram(int board_type) +{ +#ifdef CONFIG_DDR_ECC + return post_memory_setup(1) + NO_TOUCH_BYTES_AT_END; +#else + return post_memory_setup(0) + NO_TOUCH_BYTES_AT_END; #endif +} + +int check_for_ecc_errors(const char *reason);
- return (dram_size); +int post_memory_progress(int ret, int checkEcc, const char *reason) +{ + static int led; + led++; +#if defined(CONFIG_DDR_ECC) && (CONFIG_POST & CONFIG_SYS_POST_ECC) + if (checkEcc) + ret |= check_for_ecc_errors(reason); +#endif + hcu_led_set(led); + return ret; } diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 9054282..d0ca1c5 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -27,9 +27,9 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MCU25_SLOT_ADDRESS (0x7A000000 + 0x0A) #define MCU25_DIGITAL_IO_REGISTER (0x7A000000 + 0xc0)
+#define MCU25_SLOT_ADDRESS (0x7C000000 + 0x0A) #define MCU25_LED_REGISTER_ADDRESS (0x7C000000 + 0x10) #define MCU25_VERSIONS_REGISTER (0x7C000000 + 0x0C) #define MCU25_IO_CONFIGURATION (0x7C000000 + 0x0e) @@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* Attention: If you want 1 microsecs times from the external oscillator * 0x00004051 is okay for u-boot/linux, but different from old vxworks values - * 0x00804051 causes problems with u-boot and linux! + * 0x00804051 causes problems with u-boot and linux, but must be set if we + * want to boot old vxWorks installation */ #define CPC0_CR0_VALUE 0x0007F03C #define CPC0_CR1_VALUE 0x00004051
Hi Niklaus,
On Wednesday 23 September 2009 17:22:49 Niklaus Giger wrote:
Various cleanups for our boards:
- vxworks_preboot to get clock input right for HCU4/MCU25
- reboot if SW-install-input is activated
- clear vxWorks exception msg
- HCU5: various HW-registers updated
- HCU5: 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values
- HCU5: PATCH HAB: WRITE PIPELINING OFF
- HCU5: no pci_init if board has no PCI
- MCU25: corrected address to read slot id
- Lindent -pcs for hcu5.c
Please find some comments below.
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com
board/netstal/common/nm.h | 3 + board/netstal/common/nm_bsp.c | 14 ++++ board/netstal/hcu4/hcu4.c | 9 +++ board/netstal/hcu5/hcu5.c | 150 ++++++++++++++++++++++++++++------------- board/netstal/hcu5/sdram.c | 128 +++++++++++++++++++++++------------ board/netstal/mcu25/mcu25.c | 5 +- 6 files changed, 216 insertions(+), 93 deletions(-)
diff --git a/board/netstal/common/nm.h b/board/netstal/common/nm.h index 3dff1d6..128b0c3 100644 --- a/board/netstal/common/nm.h +++ b/board/netstal/common/nm.h @@ -18,12 +18,15 @@
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA */
+#include <exports.h>
extern void hcu_led_set(u32 value); extern u32 get_serial_number(void); extern u32 hcu_get_slot(void); extern int board_with_pci(void); extern void nm_show_print(int generation, int index, int hw_capabilities); extern void set_params_for_sw_install(int install_requested, char *board_name ); +extern int sys_install_requested(void); extern void common_misc_init_r(void);
enum { diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c index 237f4ed..e22cc58 100644 --- a/board/netstal/common/nm_bsp.c +++ b/board/netstal/common/nm_bsp.c @@ -37,6 +37,7 @@ generation_info generations[6] = { {HW_GENERATION_MCU20, "MCU20"}, {HW_GENERATION_MCU25, "MCU25"}, }; +static int installRequested;
void nm_show_print(int generation, int index, int hw_capabilities) { @@ -60,6 +61,7 @@ void nm_show_print(int generation, int index, int hw_capabilities)
void set_params_for_sw_install(int install_requested, char *board_name ) {
- memset((void *)0x4300, 0, 0x100); /* clear vxWorks exception msg */ if (install_requested) { char string[128];
@@ -115,3 +117,15 @@ void common_misc_init_r(void) saveenv(); } }
+void show_activity(int arg) +{
- hcu_led_set(arg);
- if( sys_install_requested() !=installRequested )
- {
if (sys_install_requested() != installRequested ) {
printf("%s: installRequested 0x%x 0x%x\n", __FUNCTION__,installRequested,sys_install_requested());do_reset ();
do_reset();
- }
+} diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 40bec8e..75be92e 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define CPC0_CR0_VALUE 0x0030103c #define CPC0_CR1_VALUE 0x00004051 +#define CPCO_CR1_USE_EXTERNAL 0x00804051
int board_early_init_f (void) { @@ -154,6 +155,14 @@ int misc_init_r(void) return 0; }
+int vxworks_preboot(void) {
- if (sys_install_requested())
- {
mtdcr(CPC0_CR1, CPCO_CR1_USE_EXTERNAL);- }
if (sys_install_requested()) mtdcr(CPC0_CR1, CPCO_CR1_USE_EXTERNAL);
- return 0;
+}
phys_size_t initdram(int board_type) { long dram_size = 0; diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 836c034..46eb9d1 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -45,6 +45,9 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000) #define HCU_SW_INSTALL_REQUESTED 0x10
+#define OPB2PLB40_BCTRL 0x350 +#define P4P3BO0_CFG 0x026
/*
- This function is run very early, out of flash, and before devices are
- initialized. It is called by lib_ppc/board.c:board_init_f by virtue
@@ -74,17 +77,17 @@ int board_early_init_f(void)
mfcpr(CPR0_ICFG, cpr0icfg); if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
mtcpr(CPR0_MALD, 0x02000000);mtcpr(CPR0_OPBD, 0x02000000);mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */mtcpr(CPR0_PLLC, 0x40000238);mtcpr(CPR0_PLLD, 0x01010414);
mtcpr(CPR0_MALD, 0x02000000);mtcpr(CPR0_OPBD, 0x02000000);mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */mtcpr(CPR0_PLLC, 0x40000238);mtcpr(CPR0_PLLD, 0x01010414);
mtcpr(CPR0_SPCID, 0x03000000);mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
mtcpr(CPR0_SPCID, 0x03000000);mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1 */mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);/*
- Initiate system reset in debug control register DBCR
@@ -92,7 +95,7 @@ int board_early_init_f(void) dbcr = mfspr(SPRN_DBCR0); mtspr(SPRN_DBCR0, dbcr | CHIP_RESET); }
- mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
- mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1 */
#endif mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xb8400000); @@ -155,6 +158,9 @@ int board_early_init_f(void) mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
- /* 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values */
- mtsdr(SDR0_PFC2, 0x4642DB00);
- /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350);
@@ -220,7 +226,6 @@ u32 get_serial_number(void) return in_be32(serial); }
/*
- hcu_get_slot
*/ @@ -230,7 +235,6 @@ u32 hcu_get_slot(void) return in_be16(slot) & 0x7f; }
/*
- misc_init_r.
*/ @@ -239,6 +243,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1;
- unsigned long addr;
#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ @@ -251,7 +256,8 @@ int misc_init_r(void) /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
CONFIG_ENV_ADDR_REDUND +2 * CONFIG_ENV_SECT_SIZE -1, &flash_info[0]);#endif #endif @@ -266,59 +272,101 @@ int misc_init_r(void) mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr);
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
/* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY
*/
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */
/* To enable the USB 2.0 Device function through the UTMI interface */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
- usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */
mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB2D0CR, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr);
- /*clear resets*/
/*clear resets */ udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n");
/* Set priority for all PLB3 devices to 2. */
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0xCF30B400) | 0x8A20B400);
/* Set PLB3 arbiter to fair mode. */
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
/*
* Set priority for all PLB4 devices to 2.*/mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0xFFF3FD00) | 0xAAA2FD00);
/*
* Set PLB4 arbiter to:* fair mode, High Bus Utilisation Enabled,* 2 Deep read pipe, Write pipeline disabled.*/addr = (mfdcr(PLB4_ACR & 0xFF000000) | 0xDA000000);
mtdcr(PLB4_ACR, addr);
/*
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.* Workaround: Disable write pipelining to DDR SDRAM by setting* PLB0_ACR[WRP] = 0.*/mtdcr(PLB0_ACR,
(mfdcr(PLB0_ACR) & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_DISABLED);/* Segment1 */
mtdcr(PLB1_ACR,
(mfdcr(PLB1_ACR) & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_DISABLED);/* Set priority of OPB-to-PLB4 Bridge */
mtdcr(OPB2PLB40_BCTRL,
(mfdcr(OPB2PLB40_BCTRL) & ~0xC0000000) | 0x80000000);/* Set priority of PLB4 to PLB3 Bridge */
mtdcr(P4P3BO0_CFG, (mfdcr(P4P3BO0_CFG) & ~0x00C00000) | 0x00800000);
common_misc_init_r();
- set_params_for_sw_install( sys_install_requested(), "hcu5" );
- set_params_for_sw_install(sys_install_requested(), "hcu5"); /* We cannot easily enable trace before, as there are other
*/ if (mfspr(SPRN_DBCR0) & 0x80000000) { /* External debugger alive
- routines messing around with sdr0_pfc1. And I do not need it.
- enable trace facilty for Lauterbach
* CCR0[DTB]=0 Enable broadcast of trace information* SDR0_PFC0[TRE] Trace signals are enabled instead of* GPIO49-63
* CCR0[DTB]=0 Enable broadcast of trace information* SDR0_PFC0[TRE] Trace signals are enabled instead of* GPIO49-63
mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~(CCR0_DTB));mtsdr(SDR0_PFC0, SDR0_PFC1 | SDR0_PFC0_TRE_ENABLE);}
#ifdef CONFIG_PCI int board_with_pci(void) { @@ -344,7 +392,9 @@ int pci_pre_init(struct pci_controller *hose) { unsigned long addr;
- if (!board_with_pci()) { return 0; }
- if (!board_with_pci()) {
return 0;- }
if (!board_with_pci()) return 0;
/* * Set priority for all PLB3 devices to 0. @@ -353,7 +403,7 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(SD0_AMP1, addr); mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB3_ACR);
- mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
/*
- Set priority for all PLB4 devices to 0.
@@ -361,17 +411,17 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(SD0_AMP0, addr); mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
- mtdcr(PLB4_ACR, addr); /* Sequoia */
mtdcr(PLB4_ACR, addr); /* Sequoia */
/*
- As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
- Workaround: Disable write pipelining to DDR SDRAM by setting
- PLB0_ACR[WRP] = 0.
*/
- mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */
- mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
return board_with_pci();
} @@ -386,14 +436,16 @@ int pci_pre_init(struct pci_controller *hose) */ void pci_target_init(struct pci_controller *hose) {
- if (!board_with_pci()) { return; }
- if (!board_with_pci()) {
return;- }
if (!board_with_pci()) return;
/* * Set up Direct MMIO registers * * PowerPC440EPX PCI Master configuration. * Map one 1Gig range of PLB/processor addresses to PCI memory space. * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
* 0xA0000000-0xDFFFFFFF
* 0xA0000000-0xDFFFFFFF*/
- Use byte reversed out routines to handle endianess.
- Make this region non-prefetchable.
@@ -448,7 +500,9 @@ void pci_target_init(struct pci_controller *hose) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short;
- if (!board_with_pci()) { return; }
- if (!board_with_pci()) {
return;- }
Again.
/*--------------------------------------------------------------- * Write the PowerPC440 EP PCI Configuration regs. @@ -479,7 +533,7 @@ int is_pci_host(struct pci_controller *hose) { return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST) /* @@ -488,12 +542,12 @@ int is_pci_host(struct pci_controller *hose) */ int post_hotkeys_pressed(void) {
- return 0; /* No hotkeys supported */
- return 0; /* No hotkeys supported */
} #endif /* CONFIG_POST */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t * bd) { ft_cpu_setup(blob, bd);
@@ -504,7 +558,7 @@ void ft_board_setup(void *blob, bd_t *bd)
- Hardcoded flash setup:
- Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
*/ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t
- info) { if (banknum == 0) { /* non-CFI boot flash */ info->portwidth = 1;
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0546cd7..d52cf99 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,9 +36,11 @@ #include <asm/mmu.h> #include <asm/cache.h> #include <ppc440.h> +#include <post.h>
void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); +void zero_all_memory(unsigned long start_address, unsigned long num_bytes);
#define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -48,6 +50,11 @@ void dcbz_area(u32 start_address, u32 num_bytes); #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
+/* PPC440EPx Erratum CHIP_11: End of memory range area restricted access.
- -> no access to last 256 Bytes!!!
- */
+#define NO_TOUCH_BYTES_AT_END 256
Please take a look at this define in sequoia.h:
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */
Doesn't this work for you as well?
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Dear Niklaus Giger,
In message 1253719369-26565-3-git-send-email-niklaus.giger@netstal.com you wrote:
Various cleanups for our boards:
- vxworks_preboot to get clock input right for HCU4/MCU25
- reboot if SW-install-input is activated
- clear vxWorks exception msg
- HCU5: various HW-registers updated
- HCU5: 2nd Ethernet = SMII, Ethernet PLL Config. = recommended values
- HCU5: PATCH HAB: WRITE PIPELINING OFF
- HCU5: no pci_init if board has no PCI
- MCU25: corrected address to read slot id
- Lindent -pcs for hcu5.c
Please don't mix white space cleanup / formatting changes with changes of real content.
+void show_activity(int arg) +{
- hcu_led_set(arg);
- if( sys_install_requested() !=installRequested )
- {
printf("%s: installRequested 0x%x 0x%x\n", __FUNCTION__,installRequested,sys_install_requested());do_reset ();- }
Incorrect brace style. Please fix globally.
...
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0546cd7..d52cf99 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,9 +36,11 @@ #include <asm/mmu.h> #include <asm/cache.h> #include <ppc440.h> +#include <post.h>
void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); +void zero_all_memory(unsigned long start_address, unsigned long num_bytes);
#define ECC_RAM 0x03267F0B #define NO_ECC_RAM 0x00267F0B @@ -48,6 +50,11 @@ void dcbz_area(u32 start_address, u32 num_bytes); #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
+/* PPC440EPx Erratum CHIP_11: End of memory range area restricted access.
- -> no access to last 256 Bytes!!!
- */
Incorrect multiline comment style. Please fix globally.
Best regards,
Wolfgang Denk
Dear Niklaus Giger,
In message 1253719369-26565-2-git-send-email-niklaus.giger@netstal.com you wrote:
- CONFIG_SYS_BOOTMAPSZ for 16 instead of 8 MB, moved to common
- baudrate back to 9600 for backward compatibility
- HCU4: CONFIG_SYS_ICACHE_SACR_VALUE defined
- CONFIG_VXWORKS_PREBOOT for HCU4 and MCU25
- HCU5: Add CPU and OCM POST
...
-#define CONFIG_DDR_ECC 1 /* enable ECC */ +/* warum gibt es Fehler mit #undef CONFIG_DDR_ECC (Hub) */ +#define CONFIG_DDR_ECC +#undef DISABLE_DDR_ECC_AFTER_POST /* disable ECC after POST tests */
I recommend to use comments in one language only.
...
+/* defining CONFIG_4xx_DCACHE leads to erros in memory_extended_tests */ +#undef CONFIG_WATCHDOG +/* Watchdog cannot be enabled, as it would be still enabled booting vxWorks */ +#undef CONFIG_4xx_DCACHE
It seems comments and code are mixed pretty randomly. I guess this is not intentional?
...
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Hm.. "Increase" is more suitable for the change log, but as a comment? Assume you read this in two years from now. What is being increased?
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de I have the simplest tastes. I am always satisfied with the best. -- Oscar Wilde
Hi Niklaus,
+enum REGISTER_TYPE {
- DCR, /* Directly Accessed DCR's */
- IDCR1, /* Indirectly Accessed DCR to SDRAM0_CFGADDR and SDRAM0_CFGDATA */
- IDCR2, /* Indirectly Accessed DCR to EBC0_CFGADDR and EBC0_CFGDATA */
- IDCR3, /* Indirectly Accessed DCR to EBM0_CFGADDR and EBM0_CFGDATA */
- IDCR4, /* Indirectly Accessed DCR to PPM0_CFGADDR and PPM0_CFGDATA */
- IDCR5, /* Indirectly Accessed DCR to CPR0_CFGADDR and CPR0_CFGDATA */
- IDCR6, /* Indirectly Accessed DCR to SDR0_CFGADDR and SDR0_CFGDATA */
- MM /* Directly Accessed MMIO Register */
+};
The lines above are well over 80 lines.
+struct cpu_register {
- char *name;
- enum REGISTER_TYPE type;
- unsigned long address;
+};
+/* PPC440EPx registers ordered for output
- name type addr size
- */
+const struct cpu_register ppc440epx_reg[] = {
- {"EBC0_B0CR ", IDCR2, PB0CR},
- {"EBC0_B1CR ", IDCR2, PB1CR},
- {"EBC0_B2CR ", IDCR2, PB2CR},
- {"EBC0_B3CR ", IDCR2, PB3CR},
- {"EBC0_B4CR ", IDCR2, PB4CR},
- {"EBC0_B5CR ", IDCR2, PB5CR},
- {"EBC0_B0AP ", IDCR2, PB0AP},
- {"EBC0_B1AP ", IDCR2, PB1AP},
- {"EBC0_B2AP ", IDCR2, PB2AP},
- {"EBC0_B3AP ", IDCR2, PB3AP},
You should be able to remove all those empty spaces in the strings above and use a fancy printf format to get your alignment right.
<snip>
+/*
- CPU Register dump of PPC440EPx
- Output in order of struct ppc440epx_reg
- */
+int do_reghcu5(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{
- unsigned int i;
- unsigned int n;
- unsigned long value;
- enum REGISTER_TYPE type;
- printf
("\nRegister Dump PPC440EPx for comparison with document A0001492\n\n");- n = sizeof(ppc440epx_reg) / sizeof(ppc440epx_reg[0]);
- for (i = 0; i < n; i++) {
value = 0;type = ppc440epx_reg[i].type;switch (type) {case DCR: /* Directly Accessed DCR's */switch (ppc440epx_reg[i].address) {/* following list includes only registers included in struct */case 0x0b0:value = mfdcr(0x0b0);break;case 0x0f0:value = mfdcr(0x0f0);break;case 0x0180:value = mfdcr(0x0180);break;case 0x081:value = mfdcr(0x081);break;case 0x089:value = mfdcr(0x089);break;case 0x077:value = mfdcr(0x077);break;case 0x350:value = mfdcr(0x350);break;case 0x026:value = mfdcr(0x026);break;
Replace all the above "value = ...; break;" with 1 "value = mfdcr(ppc440epx_reg[i].address); break;"?
<snip>
+/* define do_reghcu5 as u-boot command */ +U_BOOT_CMD(reghcu5, 2, 1, do_reghcu5,
"reghcu5 - print register information for HCU5\n",);
This command's help message won't be printed correctly.
Best, Peter
Hi Peter
Thanks for your feedback, but ..
Am Mittwoch 23 September 2009 17:59:10 schrieb Peter Tyser:
Hi Niklaus,
<snip>
case 0x350:value = mfdcr(0x350);break;case 0x026:value = mfdcr(0x026);break;Replace all the above "value = ...; break;" with 1 "value = mfdcr(ppc440epx_reg[i].address); break;"?
This cannot be done, as mfdcr is assembler mfdcr register, ID_OF_DCR ID_OF_DCR cannot be a variable.
<snip>
+/* define do_reghcu5 as u-boot command */ +U_BOOT_CMD(reghcu5, 2, 1, do_reghcu5,
"reghcu5 - print register information for HCU5\n",);This command's help message won't be printed correctly.
Best, Peter
All the rest will show up in the coming next patch.
Best regards
Hi Niklaus,
On Wednesday 23 September 2009 17:22:47 Niklaus Giger wrote:
Adds a HCU5 board specific cmd reghcu5 to dump about 140 internal register which define the HW configuration. Needed for documentation purposes and to compare different settings.
Apart from Peter's comments, I also have a more general comment. Please correct me if I'm wring, but this register dump doesn't seem to be HCU5 specific, but PPC440EPx specific. If this is the case, we (you) should probably move this code into the cpu/ppc4xx directory. Perhaps something like:
cpu/ppc4xx/440epx_regdump.c
What do you think?
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Am Mittwoch 23 September 2009 18:49:34 schrieb Stefan Roese:
Hi Niklaus,
On Wednesday 23 September 2009 17:22:47 Niklaus Giger wrote:
Adds a HCU5 board specific cmd reghcu5 to dump about 140 internal register which define the HW configuration. Needed for documentation purposes and to compare different settings.
Apart from Peter's comments, I also have a more general comment. Please correct me if I'm wring, but this register dump doesn't seem to be HCU5 specific, but PPC440EPx specific. If this is the case, we (you) should probably move this code into the cpu/ppc4xx directory. Perhaps something like:
cpu/ppc4xx/440epx_regdump.c
What do you think?
I feel honoured if you consider this patch useful for other boards, too. I will rename the cmd to "440epx_regdump" unless you have a better idea.
Patch will follow tomorrow from my office.
Will remove the reference to our internal documentation, too.
Best regards
Cheers, Stefan
On Wednesday 23 September 2009 19:51:24 Niklaus Giger wrote:
Adds a HCU5 board specific cmd reghcu5 to dump about 140 internal register which define the HW configuration. Needed for documentation purposes and to compare different settings.
Apart from Peter's comments, I also have a more general comment. Please correct me if I'm wring, but this register dump doesn't seem to be HCU5 specific, but PPC440EPx specific. If this is the case, we (you) should probably move this code into the cpu/ppc4xx directory. Perhaps something like:
cpu/ppc4xx/440epx_regdump.c
What do you think?
I feel honoured if you consider this patch useful for other boards, too. I will rename the cmd to "440epx_regdump" unless you have a better idea.
Thinking a bit more about it, we should probably choose a more generic name, so that other 4xx variants may use this command as well. How about just using "regdump"?
And please base you patch against the "4xx-register-cleanup" branch of my u- boot-ppc4xx repo.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
On Thu, 2009-09-24 at 11:21 +0200, Stefan Roese wrote:
On Wednesday 23 September 2009 19:51:24 Niklaus Giger wrote:
Adds a HCU5 board specific cmd reghcu5 to dump about 140 internal register which define the HW configuration. Needed for documentation purposes and to compare different settings.
Apart from Peter's comments, I also have a more general comment. Please correct me if I'm wring, but this register dump doesn't seem to be HCU5 specific, but PPC440EPx specific. If this is the case, we (you) should probably move this code into the cpu/ppc4xx directory. Perhaps something like:
cpu/ppc4xx/440epx_regdump.c
What do you think?
I feel honoured if you consider this patch useful for other boards, too. I will rename the cmd to "440epx_regdump" unless you have a better idea.
Thinking a bit more about it, we should probably choose a more generic name, so that other 4xx variants may use this command as well. How about just using "regdump"?
And please base you patch against the "4xx-register-cleanup" branch of my u- boot-ppc4xx repo.
What about adding a common 4xx_reginfo() function instead, then calling it from common/cmd_reginfo.c? Some of the 4xx dumping already in cmd_reginfo.c could also be moved to cpu/ppc4xx/[reginfo.c|cpu.c] to clean it up. Unless there's a good reason to have both "regdump" and "reginfo" commands...
Best, Peter
On Thursday 24 September 2009 12:04:53 Peter Tyser wrote:
Thinking a bit more about it, we should probably choose a more generic name, so that other 4xx variants may use this command as well. How about just using "regdump"?
And please base you patch against the "4xx-register-cleanup" branch of my u- boot-ppc4xx repo.
What about adding a common 4xx_reginfo() function instead, then calling it from common/cmd_reginfo.c? Some of the 4xx dumping already in cmd_reginfo.c could also be moved to cpu/ppc4xx/[reginfo.c|cpu.c] to clean it up.
Good idea. I totally forgot about this code. At least the 4xx part is stone age and can be dropper or replaced by the new concept introduced by Niklaus.
Unless there's a good reason to have both "regdump" and "reginfo" commands...
I can't think of any. Niklaus, is this ok with you too?
If yes, then please create a patch as suggested by Peter, calling ppc4xx_reginfo() function in common/cmd_reginfo.c (analog to mpc86xx_reginfo()). And add cpu/ppc4xx/reginfo.c with this function.
I (or somebody else?) will then, if time permits, add some other 4xx variants to this ppc4xx reginfo command as well.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Dear Niklaus Giger,
In message 1253719369-26565-1-git-send-email-niklaus.giger@netstal.com you wrote:
Adds a HCU5 board specific cmd reghcu5 to dump about 140 internal register which define the HW configuration. Needed for documentation purposes and to compare different settings.
Signed-off-by: Niklaus Giger niklaus.giger@netstal.com
board/netstal/hcu5/Makefile | 2 +- board/netstal/hcu5/cmd_reghcu5.c | 283 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 284 insertions(+), 1 deletions(-) create mode 100644 board/netstal/hcu5/cmd_reghcu5.c
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index 4456771..670b100 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -25,7 +25,7 @@ LIB = $(obj)lib$(BOARD).a
# NOBJS : Netstal common objects NOBJS = nm_bsp.o -COBJS = $(BOARD).o sdram.o +COBJS = $(BOARD).o sdram.o cmd_reghcu5.o
Please keep lists sorted. Consider using only one file entry per line.
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c)) diff --git a/board/netstal/hcu5/cmd_reghcu5.c b/board/netstal/hcu5/cmd_reghcu5.c new file mode 100644 index 0000000..ca330f7 --- /dev/null +++ b/board/netstal/hcu5/cmd_reghcu5.c
...
+/************************************************************************
- cmd_reghcu5.c - CPU Register Dump for HCU5 board with PPC440EPx
- ***********************************************************************/
Incorrect multiline comment style.
+#include <common.h> +#include <command.h> +#include <asm/processor.h>
+enum REGISTER_TYPE {
- DCR, /* Directly Accessed DCR's */
- IDCR1, /* Indirectly Accessed DCR to SDRAM0_CFGADDR and SDRAM0_CFGDATA */
- IDCR2, /* Indirectly Accessed DCR to EBC0_CFGADDR and EBC0_CFGDATA */
- IDCR3, /* Indirectly Accessed DCR to EBM0_CFGADDR and EBM0_CFGDATA */
- IDCR4, /* Indirectly Accessed DCR to PPM0_CFGADDR and PPM0_CFGDATA */
- IDCR5, /* Indirectly Accessed DCR to CPR0_CFGADDR and CPR0_CFGDATA */
- IDCR6, /* Indirectly Accessed DCR to SDR0_CFGADDR and SDR0_CFGDATA */
- MM /* Directly Accessed MMIO Register */
Lines too long. Please fix globally.
+/* PPC440EPx registers ordered for output
- name type addr size
- */
Incorrect multiline comment style. Please fix globally.
+const struct cpu_register ppc440epx_reg[] = {
- {"EBC0_B0CR ", IDCR2, PB0CR},
- {"EBC0_B1CR ", IDCR2, PB1CR},
- {"EBC0_B2CR ", IDCR2, PB2CR},
- {"EBC0_B3CR ", IDCR2, PB3CR},
- {"EBC0_B4CR ", IDCR2, PB4CR},
- {"EBC0_B5CR ", IDCR2, PB5CR},
- {"EBC0_B0AP ", IDCR2, PB0AP},
- {"EBC0_B1AP ", IDCR2, PB1AP},
...
Instead of wasting memory for white space padded strings...
...
printf("0x%08lx %16s: 0x%08lx\n", ppc440epx_reg[i].address,ppc440epx_reg[i].name, value);
... you shoudl change this into
printf("0x%08lx %-16s: 0x%08lx\n", ...
which will give you the same left-aligned output.
Best regards,
Wolfgang Denk
participants (6)
-
Niklaus Giger -
Niklaus Giger -
Niklaus Giger -
Peter Tyser -
Stefan Roese -
Wolfgang Denk