Hi Alemao,

In my MPC8360 board I have the BMS bit (from the reset configuration word high register, CFG_HRCW_HIGH in u-boot) seted to '0', that means:

8 Mbytes at 0x0000_0000 to 0x007F_FFFF

Yep, an 8MB window starting at address zero. The processor will jump to address 0x100 when it comes out of reset.

But then still in u-boot I set my DDR & Flash:

CFG_DDR_BASE 0x00000000

CFG_FLASH_BASE 0xFF000000

So it wont conflict?

U-boot moves the memory map around during processor initialization and avoids any conflict.

Or the reset configuration word is used only when the core comes out of reset and then u-boot remmap things to CFG_DDR_BASE and CFG_FLASH_BASE?

My new flash is only 1MB, so can i set CFG_FLASH_BASE 0xFFF00000 ? Or it has a minimum like 8MB (0xFF800000) ?

You can put it where ever you like, so either of the addresses you mention would be ok.

If you happen to have an evaluation board, then just put your flash in the same location as the eval board, it'll save you having to remember which address to use when you're flipping between boards :)

Cheers, Dave