This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot.

Signed-off-by: Chunhe Lan Chunhe.Lan@freescale.com --- arch/powerpc/cpu/mpc85xx/Kconfig | 1 + board/freescale/t4rdb/MAINTAINERS | 1 + board/freescale/t4rdb/Makefile | 6 ++- board/freescale/t4rdb/ddr.c | 6 ++- board/freescale/t4rdb/spl.c | 95 +++++++++++++++++++++++++++++++++++++ board/freescale/t4rdb/t4_pbi.cfg | 3 - board/freescale/t4rdb/t4_rcw.cfg | 6 +- board/freescale/t4rdb/tlb.c | 8 +++ configs/T4240RDB_SDCARD_defconfig | 5 ++ include/configs/T4240RDB.h | 71 ++++++++++++++++++++++++--- 10 files changed, 186 insertions(+), 16 deletions(-) create mode 100644 board/freescale/t4rdb/spl.c create mode 100644 configs/T4240RDB_SDCARD_defconfig

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index adb5bd3..27eea29 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -131,6 +131,7 @@ config TARGET_T4240QDS

config TARGET_T4240RDB bool "Support T4240RDB" + select SUPPORT_SPL

config TARGET_CONTROLCENTERD bool "Support controlcenterd" diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS index 845c1b6..53ccabc 100644 --- a/board/freescale/t4rdb/MAINTAINERS +++ b/board/freescale/t4rdb/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/t4rdb/ F: include/configs/T4240RDB.h F: configs/T4160RDB_defconfig F: configs/T4240RDB_defconfig +F: configs/T4240RDB_SDCARD_defconfig diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 3886e3d..83b55ee 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T4240RDB) += t4240rdb.o obj-y += cpld.o -obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 5a43c1b..27b37b5 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -108,11 +108,15 @@ phys_size_t initdram(int board_type)

puts("Initializing....using SPD\n");

+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram();

dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif

- puts(" DDR: "); return dram_size; } diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c new file mode 100644 index 0000000..68ecde7 --- /dev/null +++ b/board/freescale/t4rdb/spl.c @@ -0,0 +1,95 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * Author: Chunhe Lan Chunhe.Lan@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> + +#include "t4rdb.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + + puts("\nSD boot...\n"); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + + mmc_boot(); +} diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg index c9f8ced..e7bb673 100644 --- a/board/freescale/t4rdb/t4_pbi.cfg +++ b/board/freescale/t4rdb/t4_pbi.cfg @@ -19,9 +19,6 @@ 09000d00 00000000 09000d04 fff80000 09000d08 81000012 -#slow mdio clock -095fc030 00008148 -095fd030 00808148 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg index e46c7b2..282fea4 100644 --- a/board/freescale/t4rdb/t4_rcw.cfg +++ b/board/freescale/t4rdb/t4_rcw.cfg @@ -2,6 +2,6 @@ aa55aa55 010e0100 #serdes protocol 27_55_1_9 16070019 18101916 00000000 00000000 -6c6e0848 00448c00 6c020000 f5000000 -00000000 ee0000ee 00000000 000287fc -00000000 50000000 00000000 00000028 +6c6e0848 00448c00 ec020000 f5000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 474301e..6a6b4b5 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -51,6 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),

+#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -91,6 +92,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif + #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -111,6 +114,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 18, BOOKE_PAGESZ_2G, 1) +#endif };

int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig new file mode 100644 index 0000000..648b789 --- /dev/null +++ b/configs/T4240RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T4240RDB=y diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b644a6c..e58d301 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -21,11 +21,53 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */

#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg +#ifndef CONFIG_SDCARD +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + #endif +#endif /* CONFIG_RAMBOOT_PBL */

#define CONFIG_DDR_ECC

@@ -84,7 +126,16 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)

#define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -112,7 +163,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)

+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif

#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R @@ -135,7 +190,7 @@ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

/* Serial Port - controlled on board with jumper J8 @@ -351,7 +406,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND @@ -618,11 +673,11 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)