[PATCH 0/7] [U-Boot] spi: atmel-quadspi: Refresh and add classic mode support
Hello everyone,
this patch series is for U-Boot, although Linux might be affected.
The quadspi controller on microchip (former atmel) sama5d2, sam9x60 and other soc variants of the at91 family is usually used in hardware accelerated spi-mem mode. It also supports a classic mode for interfacing all kinds of SPI peripherals like ADCs, IO expanders, displays, you name it. However the drivers in Linux and U-Boot did not support that mode, yet.
While spi-mem subsystem interface is comparable between Linux and U-Boot, SPI subsystem interface is rather different in Linux and U-Boot. So there's no previously written Linux support just ported here. I tried that, but the simple implementation for U-Boot's .xfer() used here does not work for Linux' .transfer_one() because of the OVRES flag set all the time. I guess a more sophisticated approach has to be taken in Linux with interrupts, completions and/or dma?
According to commit 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver") message, the initial U-Boot variant of this driver was ported from Linux v5.1-rc5 back then. I hope it's okay to squash the fixes added to Linux after that into patch 2 and 3 of this series?
Patch 4 and 5 come from my efforts to hack this feature into the Linux driver. (Not sure if those should be added to the Linux driver anyways, even if nobody ever implements transfer_one() over there?)
Patch 5 is the actual work, very much inspired by the current U-Boot driver atmel_spi for the generic SPI controllers on at91 family.
Patch 1 is copied from my other spi series for U-Boot, just added it here for better build results.
Patch 6 is optional, because not portable towards Linux.
Tested on top of v2024.10, because v2025.01 won't build as debug for sam9x60 as described in another thread. But there are almost no changes related to at91 socs, boards, and drivers in the last months here, so it should be comparable.
Greets Alex
(Cc-ing the contributors of the Linux fixes here.) Cc: Tudor Ambarus tudor.ambarus@microchip.com Cc: Yoshitaka Ikeda ikeda@nskint.co.jp Cc: Csókás Bence csokas.bence@prolan.hu
Alexander Dahl (7): spi: atmel-quadspi: Depend on SPI_MEM spi: atmel-quadspi: Port collected fixes from Linux v5.10 and v5.15 spi: atmel-quadspi: Avoid overwriting MR register settings spi: atmel-quadspi: Remove default mode setting at probe time spi: atmel-quadspi: Allow setting SMM to classic SPI mode spi: atmel-quadspi: Add support for classic SPI mode spi: atmel-quadspi: Improve probe debugging
drivers/spi/Kconfig | 2 +- drivers/spi/atmel-quadspi.c | 294 ++++++++++++++++++++++++++++-------- 2 files changed, 228 insertions(+), 68 deletions(-)
base-commit: 2eed5a1ff36217372e19f7513bd07077fc76718a
Most other spi-mem drivers also depend on SPI_MEM. Fixes this build error:
arm-v5te-linux-gnueabi-ld.bfd: drivers/spi/atmel-quadspi.o: in function `atmel_qspi_supports_op': /mnt/data/adahl/src/u-boot/drivers/spi/atmel-quadspi.c:460: undefined reference to `spi_mem_default_supports_op' make[1]: *** [/mnt/data/adahl/src/u-boot/Makefile:1821: u-boot] Error 1
Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 96ea033082b..d55fc49f637 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -85,7 +85,7 @@ config ATH79_SPI
config ATMEL_QSPI bool "Atmel Quad SPI Controller" - depends on ARCH_AT91 + depends on ARCH_AT91 && SPI_MEM help Enable the Atmel Quad SPI controller in master mode. This driver does not support generic SPI. The implementation supports only the
Port changes from a 4 piece patch series from Linux kernel v5.10, merged with v5.10-rc1-83-gc732b7567d869 ("Merge series "spi: atmel-quadspi: Fix AHB memory accesses" from Tudor Ambarus …").
Port the single fix v5.15-rc1-14-g09134c5322df9 ("spi: Fixed division by zero warning").
Reduces differences between linux and u-boot driver.
Cc: Tudor Ambarus tudor.ambarus@microchip.com Cc: Yoshitaka Ikeda ikeda@nskint.co.jp Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/atmel-quadspi.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 3efb661803b..ea045acab65 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -474,7 +474,7 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, return mode; ifr |= atmel_qspi_modes[mode].config;
- if (op->dummy.buswidth && op->dummy.nbytes) + if (op->dummy.nbytes) dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
/* @@ -529,10 +529,14 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, if (dummy_cycles) ifr |= QSPI_IFR_NBDUM(dummy_cycles);
- /* Set data enable */ - if (op->data.nbytes) + /* Set data enable and data transfer type. */ + if (op->data.nbytes) { ifr |= QSPI_IFR_DATAEN;
+ if (op->addr.nbytes) + ifr |= QSPI_IFR_TFRTYP_MEM; + } + /* * If the QSPI controller is set in regular SPI mode, set it in * Serial Memory Mode (SMM). @@ -545,27 +549,24 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, /* Clear pending interrupts */ (void)atmel_qspi_read(aq, QSPI_SR);
- if (aq->caps->has_ricr) { - if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN) - ifr |= QSPI_IFR_APBTFRTYP_READ; - - /* Set QSPI Instruction Frame registers */ + /* Set QSPI Instruction Frame registers. */ + if (op->addr.nbytes && !op->data.nbytes) atmel_qspi_write(iar, aq, QSPI_IAR); + + if (aq->caps->has_ricr) { if (op->data.dir == SPI_MEM_DATA_IN) atmel_qspi_write(icr, aq, QSPI_RICR); else atmel_qspi_write(icr, aq, QSPI_WICR); - atmel_qspi_write(ifr, aq, QSPI_IFR); } else { - if (op->data.dir == SPI_MEM_DATA_OUT) + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
- /* Set QSPI Instruction Frame registers */ - atmel_qspi_write(iar, aq, QSPI_IAR); atmel_qspi_write(icr, aq, QSPI_ICR); - atmel_qspi_write(ifr, aq, QSPI_IFR); }
+ atmel_qspi_write(ifr, aq, QSPI_IFR); + return 0; }
Port these commits:
- v6.11-rc5-90-g329ca3eed4a9a ("spi: atmel-quadspi: Avoid overwriting delay register settings") - v6.12-rc1-1-g162d9b5d2308c ("spi: atmel-quadspi: Fix wrong register value written to MR"). - v6.13-rc2-27-gf663898d047a7 ("spi: atmel-quadspi: Factor out switching to Serial Memory Mode to function")
Cc: Csókás Bence csokas.bence@prolan.hu Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/atmel-quadspi.c | 96 ++++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 45 deletions(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index ea045acab65..9e596b7448c 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -395,6 +395,26 @@ static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) writel(value, aq->regs + offset); }
+static int atmel_qspi_reg_sync(struct atmel_qspi *aq) +{ + u32 val; + + return readl_poll_timeout(aq->regs + QSPI_SR2, val, + !(val & QSPI_SR2_SYNCBSY), + ATMEL_QSPI_SYNC_TIMEOUT); +} + +static int atmel_qspi_update_config(struct atmel_qspi *aq) +{ + int ret; + + ret = atmel_qspi_reg_sync(aq); + if (ret) + return ret; + atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); + return atmel_qspi_reg_sync(aq); +} + static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, const struct atmel_qspi_mode *mode) { @@ -458,6 +478,25 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave, return true; }
+/* + * If the QSPI controller is set in regular SPI mode, set it in + * Serial Memory Mode (SMM). + */ +static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq) +{ + int ret = 0; + + if (!(aq->mr & QSPI_MR_SMM)) { + aq->mr |= QSPI_MR_SMM; + atmel_qspi_write(aq->mr, aq, QSPI_MR); + + if (aq->caps->has_gclk) + ret = atmel_qspi_update_config(aq); + } + + return ret; +} + static int atmel_qspi_set_cfg(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 *offset) { @@ -537,14 +576,9 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, ifr |= QSPI_IFR_TFRTYP_MEM; }
- /* - * If the QSPI controller is set in regular SPI mode, set it in - * Serial Memory Mode (SMM). - */ - if (aq->mr != QSPI_MR_SMM) { - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); - aq->mr = QSPI_MR_SMM; - } + mode = atmel_qspi_set_serial_memory_mode(aq); + if (mode < 0) + return mode;
/* Clear pending interrupts */ (void)atmel_qspi_read(aq, QSPI_SR); @@ -598,26 +632,6 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq, ATMEL_QSPI_TIMEOUT); }
-static int atmel_qspi_reg_sync(struct atmel_qspi *aq) -{ - u32 val; - - return readl_poll_timeout(aq->regs + QSPI_SR2, val, - !(val & QSPI_SR2_SYNCBSY), - ATMEL_QSPI_SYNC_TIMEOUT); -} - -static int atmel_qspi_update_config(struct atmel_qspi *aq) -{ - int ret; - - ret = atmel_qspi_reg_sync(aq); - if (ret) - return ret; - atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); - return atmel_qspi_reg_sync(aq); -} - static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 *offset) { @@ -669,17 +683,9 @@ static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, ifr |= QSPI_IFR_TFRTYP_MEM; }
- /* - * If the QSPI controller is set in regular SPI mode, set it in - * Serial Memory Mode (SMM). - */ - if (aq->mr != QSPI_MR_SMM) { - atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); - ret = atmel_qspi_update_config(aq); - if (ret) - return ret; - aq->mr = QSPI_MR_SMM; - } + ret = atmel_qspi_set_serial_memory_mode(aq); + if (ret < 0) + return ret;
/* Clear pending interrupts */ (void)atmel_qspi_read(aq, QSPI_SR); @@ -903,11 +909,10 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz) }
/* Set the QSPI controller by default in Serial Memory Mode */ - atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); - ret = atmel_qspi_update_config(aq); - if (ret) + aq->mr |= QSPI_MR_DQSDLYEN; + ret = atmel_qspi_set_serial_memory_mode(aq); + if (ret < 0) return ret; - aq->mr = QSPI_MR_SMM;
/* Enable the QSPI controller. */ ret = atmel_qspi_reg_sync(aq); @@ -1048,8 +1053,9 @@ static int atmel_qspi_init(struct atmel_qspi *aq) atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
/* Set the QSPI controller by default in Serial Memory Mode */ - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); - aq->mr = QSPI_MR_SMM; + ret = atmel_qspi_set_serial_memory_mode(aq); + if (ret < 0) + return ret;
/* Enable the QSPI controller */ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
The Serial Memory Mode (SMM) is enabled with atmel_qspi_set_cfg() on each invocation of atmel_qspi_exec_op(). Setting SMM through atmel_qspi_init() at probe time is redundant.
Removing the SMM setting at probe time should therefore 1) be safe to do and 2) allows for setting it to a different value in a future implementation of .xfer() which needs to disable SMM.
Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/atmel-quadspi.c | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 9e596b7448c..467f29c01ca 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -1052,11 +1052,6 @@ static int atmel_qspi_init(struct atmel_qspi *aq) /* Reset the QSPI controller */ atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
- /* Set the QSPI controller by default in Serial Memory Mode */ - ret = atmel_qspi_set_serial_memory_mode(aq); - if (ret < 0) - return ret; - /* Enable the QSPI controller */ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
Switching between Serial Memory Mode (SMM) and (classic) SPI mode is a preparation for implementing .xfer() in the future.
Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/atmel-quadspi.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 467f29c01ca..d29b5ab96e9 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -479,15 +479,19 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave, }
/* - * If the QSPI controller is set in regular SPI mode, set it in - * Serial Memory Mode (SMM). + * Switch QSPI controller between regular SPI mode or Serial Memory Mode (SMM). */ -static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq) +static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq, + bool enable) { int ret = 0;
- if (!(aq->mr & QSPI_MR_SMM)) { - aq->mr |= QSPI_MR_SMM; + /* only write if designated state differs from current state */ + if (!!(aq->mr & QSPI_MR_SMM) != enable) { + if (enable) + aq->mr |= QSPI_MR_SMM; + else + aq->mr &= ~QSPI_MR_SMM; atmel_qspi_write(aq->mr, aq, QSPI_MR);
if (aq->caps->has_gclk) @@ -576,7 +580,7 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, ifr |= QSPI_IFR_TFRTYP_MEM; }
- mode = atmel_qspi_set_serial_memory_mode(aq); + mode = atmel_qspi_set_serial_memory_mode(aq, true); if (mode < 0) return mode;
@@ -683,7 +687,7 @@ static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, ifr |= QSPI_IFR_TFRTYP_MEM; }
- ret = atmel_qspi_set_serial_memory_mode(aq); + ret = atmel_qspi_set_serial_memory_mode(aq, true); if (ret < 0) return ret;
@@ -910,7 +914,7 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz)
/* Set the QSPI controller by default in Serial Memory Mode */ aq->mr |= QSPI_MR_DQSDLYEN; - ret = atmel_qspi_set_serial_memory_mode(aq); + ret = atmel_qspi_set_serial_memory_mode(aq, true); if (ret < 0) return ret;
The qspi controller on sama5d2 and sam9x60 supports "classic" SPI mode without spi-mem enhancements and accelerations, very similar to the old SPI controller on sam9g20 or the modern flexcom controllers of the same SoC family.
Register interface differs somewhat, especially because only one hardware controlled CS line is supported. Some fields are missing, some are in different registers, but in principal it works similar. So code is very much inspired by the old atmel-spi driver.
Tested on sam9x60 with a non-mainline driver to configure an FPGA.
Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/atmel-quadspi.c | 155 +++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index d29b5ab96e9..a2faac5a505 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -10,11 +10,13 @@ */
#include <malloc.h> +#include <asm/gpio.h> #include <asm/io.h> #include <clk.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <log.h> #include <dm/device_compat.h> #include <linux/bitfield.h> #include <linux/bitops.h> @@ -258,6 +260,7 @@ struct atmel_qspi_caps {
struct atmel_qspi_priv_ops;
+#define MAX_CS_COUNT 2 struct atmel_qspi { void __iomem *regs; void __iomem *mem; @@ -267,6 +270,7 @@ struct atmel_qspi { struct udevice *dev; ulong bus_clk_rate; u32 mr; + struct gpio_desc cs_gpios[MAX_CS_COUNT]; };
struct atmel_qspi_priv_ops { @@ -940,6 +944,135 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz) return ret; }
+static int atmel_qspi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + int ret; + + aq->mr &= ~QSPI_MR_CSMODE_MASK; + aq->mr |= QSPI_MR_CSMODE_LASTXFER | QSPI_MR_WDRBT; + atmel_qspi_write(aq->mr, aq, QSPI_MR); + + ret = atmel_qspi_set_serial_memory_mode(aq, false); + if (ret) + return log_ret(ret); + + /* de-assert all chip selects */ + if (IS_ENABLED(CONFIG_DM_GPIO)) { + for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { + if (dm_gpio_is_valid(&aq->cs_gpios[i])) + dm_gpio_set_value(&aq->cs_gpios[i], 0); + } + } + + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); + + return 0; +} + +static int atmel_qspi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + + /* de-assert all chip selects */ + if (IS_ENABLED(CONFIG_DM_GPIO)) { + for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { + if (dm_gpio_is_valid(&aq->cs_gpios[i])) + dm_gpio_set_value(&aq->cs_gpios[i], 0); + } + } + + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); + + return 0; +} + +static int atmel_qspi_set_cs(struct udevice *dev, int value) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + int cs = spi_chip_select(dev); + + if (IS_ENABLED(CONFIG_DM_GPIO)) { + if (!dm_gpio_is_valid(&aq->cs_gpios[cs])) + return log_ret(-ENOENT); + + return dm_gpio_set_value(&aq->cs_gpios[cs], value); + } else { + return -ENOENT; + } +} + +static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + unsigned int len, len_rx, len_tx; + const u8 *txp = dout; + u8 *rxp = din; + u32 reg; + int ret; + + if (bitlen == 0) + goto out; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + ret = atmel_qspi_set_cs(dev, 1); + if (ret) + return log_ret(ret); + reg = atmel_qspi_read(aq, QSPI_RD); + } + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + u32 status = atmel_qspi_read(aq, QSPI_SR); + u8 value; + + if (status & QSPI_SR_OVRES) + return log_ret(-1); + + if (len_tx < len && (status & QSPI_SR_TDRE)) { + if (txp) + value = *txp++; + else + value = 0; + atmel_qspi_write(value, aq, QSPI_TD); + len_tx++; + } + + if (status & QSPI_SR_RDRF) { + value = atmel_qspi_read(aq, QSPI_RD); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + readl_poll_timeout(aq->regs + QSPI_SR, reg, + reg & QSPI_SR_TXEMPTY, + ATMEL_QSPI_TIMEOUT); + + atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); + + ret = atmel_qspi_set_cs(dev, 0); + if (ret) + return log_ret(ret); + } + + return 0; +} + static int atmel_qspi_set_speed(struct udevice *bus, uint hz) { struct atmel_qspi *aq = dev_get_priv(bus); @@ -1089,6 +1222,23 @@ static int atmel_qspi_probe(struct udevice *dev) else aq->ops = &atmel_qspi_priv_ops;
+ if (IS_ENABLED(CONFIG_DM_GPIO)) { + ret = gpio_request_list_by_name(dev, "cs-gpios", aq->cs_gpios, + ARRAY_SIZE(aq->cs_gpios), 0); + if (ret < 0) { + pr_err("Can't get %s gpios! Error: %d", dev->name, ret); + return ret; + } + + for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { + if (!dm_gpio_is_valid(&aq->cs_gpios[i])) + continue; + + dm_gpio_set_dir_flags(&aq->cs_gpios[i], + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + } + /* Map the registers */ ret = dev_read_resource_byname(dev, "qspi_base", &res); if (ret) { @@ -1127,9 +1277,12 @@ static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { };
static const struct dm_spi_ops atmel_qspi_ops = { + .claim_bus = atmel_qspi_claim_bus, + .release_bus = atmel_qspi_release_bus, + .xfer = atmel_qspi_xfer, + .mem_ops = &atmel_qspi_mem_ops, .set_speed = atmel_qspi_set_speed, .set_mode = atmel_qspi_set_mode, - .mem_ops = &atmel_qspi_mem_ops, };
static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
Report spi clk speed and make use of `log_ret()`.
Signed-off-by: Alexander Dahl ada@thorsis.com --- drivers/spi/atmel-quadspi.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index a2faac5a505..8aa7a83aef4 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -1082,6 +1082,7 @@ static int atmel_qspi_set_speed(struct udevice *bus, uint hz) return atmel_qspi_sama7g5_set_speed(bus, hz);
/* Compute the QSPI baudrate */ + dev_dbg(bus, "bus_clk_rate: %lu, hz: %u\n", aq->bus_clk_rate, hz); scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz); if (scbr > 0) scbr--; @@ -1214,7 +1215,7 @@ static int atmel_qspi_probe(struct udevice *dev) aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev); if (!aq->caps) { dev_err(dev, "Could not retrieve QSPI caps\n"); - return -EINVAL; + return log_ret(-EINVAL); };
if (aq->caps->has_gclk) @@ -1227,7 +1228,7 @@ static int atmel_qspi_probe(struct udevice *dev) ARRAY_SIZE(aq->cs_gpios), 0); if (ret < 0) { pr_err("Can't get %s gpios! Error: %d", dev->name, ret); - return ret; + return log_ret(ret); }
for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { @@ -1243,32 +1244,32 @@ static int atmel_qspi_probe(struct udevice *dev) ret = dev_read_resource_byname(dev, "qspi_base", &res); if (ret) { dev_err(dev, "missing registers\n"); - return ret; + return log_ret(ret); }
aq->regs = devm_ioremap(dev, res.start, resource_size(&res)); if (IS_ERR(aq->regs)) - return PTR_ERR(aq->regs); + return log_ret(PTR_ERR(aq->regs));
/* Map the AHB memory */ ret = dev_read_resource_byname(dev, "qspi_mmap", &res); if (ret) { dev_err(dev, "missing AHB memory\n"); - return ret; + return log_ret(ret); }
aq->mem = devm_ioremap(dev, res.start, resource_size(&res)); if (IS_ERR(aq->mem)) - return PTR_ERR(aq->mem); + return log_ret(PTR_ERR(aq->mem));
aq->mmap_size = resource_size(&res);
ret = atmel_qspi_enable_clk(dev); if (ret) - return ret; + return log_ret(ret);
aq->dev = dev; - return atmel_qspi_init(aq); + return log_ret(atmel_qspi_init(aq)); }
static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
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Alexander Dahl