[U-Boot] [PATCH 0/9] x86: Patches to enable running U-Boot from coreboot
This series carries on from Gabe Black's work to upstream support for running U-Boot from coreboot.
Aditional follow-on patches are also required, depending on feedback here.
Gabe Black (4): x86: Allow excluding reset handling code from u-boot. x86: Add some missing includes. x86: coreboot: Tell u-boot about PCI bus 0 when initializing x86: coreboot: Implement recursively scanning PCI busses
Simon Glass (3): x86: Change board baud_rate to ulong x86: Add initial memory barrier macros x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE
Stefan Reinauer (1): x86: coreboot: Move non-board specific files to coreboot arch directory
Vadim Bendebury (1): x86: coreboot: Modify u-boot code to allow building coreboot payload
arch/x86/cpu/coreboot/Makefile | 2 + .../x86/cpu}/coreboot/coreboot.c | 0 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c | 35 ++++++++++++++++++ arch/x86/cpu/resetvec.S | 6 +++ arch/x86/cpu/start16.S | 4 ++ arch/x86/cpu/u-boot.lds | 3 ++ arch/x86/include/asm/global_data.h | 2 + arch/x86/include/asm/io.h | 8 ++++ arch/x86/include/asm/pci.h | 2 +- arch/x86/include/asm/u-boot.h | 5 ++- board/chromebook-x86/coreboot/Makefile | 2 - board/chromebook-x86/coreboot/config.mk | 37 ++++++++++++++++++++ board/chromebook-x86/coreboot/coreboot_start16.S | 6 +++ board/eNET/eNET_start16.S | 4 ++ common/cmd_bdinfo.c | 2 +- include/configs/coreboot.h | 6 +++- 16 files changed, 118 insertions(+), 6 deletions(-) rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%) rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (51%) create mode 100644 board/chromebook-x86/coreboot/config.mk
This is a ulong for some architectures and just unsigned for others. Change x86 to be consistent.
Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h index da667c5..0671b8d 100644 --- a/arch/x86/include/asm/u-boot.h +++ b/arch/x86/include/asm/u-boot.h @@ -48,7 +48,7 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_baudrate; /* Console Baudrate */ + unsigned long bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ struct /* RAM configuration */ { diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 23bd8a5..9bc0ebc 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); print_mhz("ethspeed", bd->bi_ethspeed); #endif - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %ld bps\n", bd->bi_baudrate);
return 0; }
Acked-by: Gabe Black gabeblack@chromium.org
These are available on other architectures, so add them on x86.
Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/include/asm/io.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 9b757d4..b12bdd8 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -234,4 +234,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr) return (phys_addr_t)(vaddr); }
+/* + * TODO: The kernel offers some more advanced versions of barriers, it might + * have some advantages to use them instead of the simple one here. + */ +#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define __iormb() dmb() +#define __iowmb() dmb() + #endif
Acked-by: Gabe Black gabeblack@chromium.org
From: Gabe Black gabeblack@chromium.org
When running from coreboot we don't want this code.
This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely.
Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/resetvec.S | 6 ++++++ arch/x86/cpu/start16.S | 4 ++++ arch/x86/cpu/u-boot.lds | 3 +++ board/chromebook-x86/coreboot/coreboot_start16.S | 6 ++++++ board/eNET/eNET_start16.S | 4 ++++ 5 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index 44aee5f..5b359ff 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -25,6 +25,10 @@
/* Reset vector, jumps to start16.S */
+#include <config.h> + +#ifndef CONFIG_NO_RESET_CODE + .extern start16
.section .resetvec, "ax" @@ -36,3 +40,5 @@ reset_vector:
.org 0xf nop + +#endif diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index cc393ff..d944840 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -28,11 +28,14 @@
#include <asm/global_data.h> #include <asm/processor-flags.h> +#include <config.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; #define o32 .byte 0x66;
+#ifndef CONFIG_NO_RESET_CODE + .section .start16, "ax" .code16 .globl start16 @@ -141,3 +144,4 @@ gdt: .byte 0x93 /* access */ .byte 0xcf /* flags + limit_high */ .byte 0x00 /* base_high */ +#endif diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index fe28030..2a90a01 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -85,6 +85,8 @@ SECTIONS __bios_start = LOADADDR(.bios); __bios_size = SIZEOF(.bios);
+#ifndef CONFIG_NO_RESET_CODE + /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM @@ -94,4 +96,5 @@ SECTIONS
. = RESET_VEC_LOC; .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } +#endif } diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S index 9ad06df..6fac3d6 100644 --- a/board/chromebook-x86/coreboot/coreboot_start16.S +++ b/board/chromebook-x86/coreboot/coreboot_start16.S @@ -28,6 +28,10 @@ * that is used by U-boot to its final destination. */
+#include <config.h> + +#ifndef CONFIG_NO_RESET_CODE + .text .section .start16, "ax" .code16 @@ -35,6 +39,8 @@ board_init16: jmp board_init16_ret
+#endif + .section .bios, "ax" .code16 .globl realmode_reset diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 5e3f44c..43dda2f 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -32,6 +32,8 @@ #include <asm/arch/sc520.h> #include <generated/asm-offsets.h>
+#ifndef CONFIG_NO_RESET_CODE + .text .section .start16, "ax" .code16 @@ -63,6 +65,8 @@ board_init16:
jmp board_init16_ret
+#endif + .section .bios, "ax" .code16 .globl realmode_reset
Hi Simon,
At first I thought this patch dealt with the 'board reset' code but then realised it deals with the 'reset vector' - Can you fix the patch subject please
On Thu, Oct 4, 2012 at 10:39 AM, Simon Glass sjg@chromium.org wrote:
From: Gabe Black gabeblack@chromium.org
When running from coreboot we don't want this code.
This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely.
Could this be done by #ifdef'ing the section in the linker script?
Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/resetvec.S | 6 ++++++ arch/x86/cpu/start16.S | 4 ++++ arch/x86/cpu/u-boot.lds | 3 +++ board/chromebook-x86/coreboot/coreboot_start16.S | 6 ++++++ board/eNET/eNET_start16.S | 4 ++++ 5 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index 44aee5f..5b359ff 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -25,6 +25,10 @@
/* Reset vector, jumps to start16.S */
+#include <config.h>
+#ifndef CONFIG_NO_RESET_CODE
.extern start16
.section .resetvec, "ax" @@ -36,3 +40,5 @@ reset_vector:
.org 0xf nop
+#endif
Condition it out in the Makefile instead
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index cc393ff..d944840 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -28,11 +28,14 @@
#include <asm/global_data.h> #include <asm/processor-flags.h> +#include <config.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; #define o32 .byte 0x66;
+#ifndef CONFIG_NO_RESET_CODE
.section .start16, "ax" .code16 .globl start16 @@ -141,3 +144,4 @@ gdt: .byte 0x93 /* access */ .byte 0xcf /* flags + limit_high */ .byte 0x00 /* base_high */ +#endif
Ditto
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index fe28030..2a90a01 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -85,6 +85,8 @@ SECTIONS __bios_start = LOADADDR(.bios); __bios_size = SIZEOF(.bios);
+#ifndef CONFIG_NO_RESET_CODE
/* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM@@ -94,4 +96,5 @@ SECTIONS
. = RESET_VEC_LOC; .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }+#endif }
The commit comment states "and the linker will either leave them empty for the loader to ignore or remove them entirely" but you are actually explicitly remove them anyway - If they are not compiled, is this necessary?
diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S index 9ad06df..6fac3d6 100644 --- a/board/chromebook-x86/coreboot/coreboot_start16.S +++ b/board/chromebook-x86/coreboot/coreboot_start16.S @@ -28,6 +28,10 @@
- that is used by U-boot to its final destination.
*/
+#include <config.h>
+#ifndef CONFIG_NO_RESET_CODE
.text .section .start16, "ax" .code16 @@ -35,6 +39,8 @@ board_init16: jmp board_init16_ret
+#endif
.section .bios, "ax" .code16 .globl realmode_reset
Hmm, I doubt coreboot really need a board level start16.S and (quite frankly) the whole 'realmode reset' code (i.e. BIOS reset) is crap and should be globally tossed (no one will ever call it)
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 5e3f44c..43dda2f 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -32,6 +32,8 @@ #include <asm/arch/sc520.h> #include <generated/asm-offsets.h>
+#ifndef CONFIG_NO_RESET_CODE
.text .section .start16, "ax" .code16 @@ -63,6 +65,8 @@ board_init16:
jmp board_init16_ret+#endif
.section .bios, "ax" .code16 .globl realmode_reset
All the above should mean there is no reason to touch the eNET code
Regards,
Graeme
Hi Graeme,
On Wed, Oct 3, 2012 at 6:01 PM, Graeme Russ graeme.russ@gmail.com wrote:
Hi Simon,
At first I thought this patch dealt with the 'board reset' code but then realised it deals with the 'reset vector' - Can you fix the patch subject please
Will do.
On Thu, Oct 4, 2012 at 10:39 AM, Simon Glass sjg@chromium.org wrote:
From: Gabe Black gabeblack@chromium.org
When running from coreboot we don't want this code.
This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely.
Could this be done by #ifdef'ing the section in the linker script?
Yes, in fact that is already in this patch.
Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/resetvec.S | 6 ++++++ arch/x86/cpu/start16.S | 4 ++++ arch/x86/cpu/u-boot.lds | 3 +++ board/chromebook-x86/coreboot/coreboot_start16.S | 6 ++++++ board/eNET/eNET_start16.S | 4 ++++ 5 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index 44aee5f..5b359ff 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -25,6 +25,10 @@
/* Reset vector, jumps to start16.S */
+#include <config.h>
+#ifndef CONFIG_NO_RESET_CODE
.extern start16
.section .resetvec, "ax" @@ -36,3 +40,5 @@ reset_vector:
.org 0xf nop
+#endif
Condition it out in the Makefile instead
I suspect the reason it was done here is these lines in the top-level Makefile.
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif
If we just take it out of the .lds file then start16.o and resetvec.o are not included in the image. But they will still be built. We could add an additional condition here perhaps, like:
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) ifneq ($(CONFIG_NO_RESET_CODE),y) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif endif
Here is the menu as I see it - what would you prefer? - top level Makefile change - arch/arm/cpu/Makefile change (pointless if top level Makefile includes these files anyway) - building everything but removing unneeded object files in the link script
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index cc393ff..d944840 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -28,11 +28,14 @@
#include <asm/global_data.h> #include <asm/processor-flags.h> +#include <config.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; #define o32 .byte 0x66;
+#ifndef CONFIG_NO_RESET_CODE
.section .start16, "ax" .code16 .globl start16 @@ -141,3 +144,4 @@ gdt: .byte 0x93 /* access */ .byte 0xcf /* flags + limit_high */ .byte 0x00 /* base_high */ +#endif
Ditto
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index fe28030..2a90a01 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -85,6 +85,8 @@ SECTIONS __bios_start = LOADADDR(.bios); __bios_size = SIZEOF(.bios);
+#ifndef CONFIG_NO_RESET_CODE
/* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM@@ -94,4 +96,5 @@ SECTIONS
. = RESET_VEC_LOC; .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }+#endif }
The commit comment states "and the linker will either leave them empty for the loader to ignore or remove them entirely" but you are actually explicitly remove them anyway - If they are not compiled, is this necessary?
We need either or.
diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S index 9ad06df..6fac3d6 100644 --- a/board/chromebook-x86/coreboot/coreboot_start16.S +++ b/board/chromebook-x86/coreboot/coreboot_start16.S @@ -28,6 +28,10 @@
- that is used by U-boot to its final destination.
*/
+#include <config.h>
+#ifndef CONFIG_NO_RESET_CODE
.text .section .start16, "ax" .code16 @@ -35,6 +39,8 @@ board_init16: jmp board_init16_ret
+#endif
.section .bios, "ax" .code16 .globl realmode_reset
Hmm, I doubt coreboot really need a board level start16.S and (quite frankly) the whole 'realmode reset' code (i.e. BIOS reset) is crap and should be globally tossed (no one will ever call it)
Will drop this.
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 5e3f44c..43dda2f 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -32,6 +32,8 @@ #include <asm/arch/sc520.h> #include <generated/asm-offsets.h>
+#ifndef CONFIG_NO_RESET_CODE
.text .section .start16, "ax" .code16 @@ -63,6 +65,8 @@ board_init16:
jmp board_init16_ret+#endif
.section .bios, "ax" .code16 .globl realmode_reset
All the above should mean there is no reason to touch the eNET code
Will remove this change.
Regards,
Graeme
Regards, Simon
Hi Simon,
On Wed, Oct 10, 2012 at 8:15 AM, Simon Glass sjg@chromium.org wrote:
diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index 44aee5f..5b359ff 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -25,6 +25,10 @@
/* Reset vector, jumps to start16.S */
+#include <config.h>
+#ifndef CONFIG_NO_RESET_CODE
.extern start16
.section .resetvec, "ax" @@ -36,3 +40,5 @@ reset_vector:
.org 0xf nop
+#endif
Condition it out in the Makefile instead
I suspect the reason it was done here is these lines in the top-level Makefile.
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif
I have often wondered about these lines in the top-level Makefile considering they are also in arch/x86/cpu/Makefile. I keep meaning to test if they are actually needed in the top-level Makefile but keep forgetting
(I see why now - see below)
If we just take it out of the .lds file then start16.o and resetvec.o are not included in the image. But they will still be built. We could add an additional condition here perhaps, like:
I don't see a huge problem with that. Yes, it's a waste of CPU cycles during the build but really, who cares.
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) ifneq ($(CONFIG_NO_RESET_CODE),y) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif endif
Looks good for the time being (again, see beloW).
Here is the menu as I see it - what would you prefer?
- top level Makefile change
- arch/arm/cpu/Makefile change (pointless if top level Makefile
includes these files anyway)
- building everything but removing unneeded object files in the link script
Can we not invert the logic of CONFIG_X86_NO_RESET_VECTOR using some Makefile magic and then do this in arch/x86/cpu/Makefile:
START-$(INCLUDE_X86_RESET_VECTOR) += resetvec.o START-y = start.o START-$(INCLUDE_X86_RESET_VECTOR) += start16.o
Actuall, to be honest, it should be:
SOBJS-y += start.o
SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += resetvec.o SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += start16.o
SRCS := $(SOBJS16-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) OBJS16 := $(addprefix $(obj),$(SOBJS16))
all: $(obj).depend $(OBJS16) $(LIB)
start.S is not at all related to the reset vector / protected mode switch, and so can safely be moved into the main (32-bit) lib. ENTRY(_start) in the linker script and:
.section .text .code32 .globl _start .type _start, @function .globl _start .type _start, @function
in start.S will always guarantee that the code in start.S appears first in u-boot.bin.
Ah Ha! now I get it - Now I see why the top-level Makefile includes:
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif
These files are not in $(CPUDIR)/lib$(CPU).o so they must be pulled in individually!
OK, by moving start.o into the lib we can drop the first line...
Now, if we create a 16-bit lib in arch/x86/cpu/Makefile:
LIB = $(obj)lib$(CPU).o LIB16 = $(obj)lib16$(CPU).o
SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += resetvec.o SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += start16.o
SOBJS-y += start.o COBJS-y += cpu.o COBJS-y += interrupts.o
SRCS := $(SOBJS16-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS16 := $(addprefix $(obj),$(SOBJS16)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB) $(LIB16)
$(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS))
$(LIB16): $(OBJS16) $(call cmd_link_o_target, $(OBJS16))
And then in the top-level Makefile:
LIBS-$(INCLUDE_X86_RESET_VECTOR) += $(CPUDIR)/lib16$(CPU).o
Much cleaner :)
(Hmmm, looking at arch/x86/lib/Makefile is appears that it is safe to mix 16- and 32-bit code in the same lib - maybe that is a better solution...)
But don't worry too much about all that in these patches - Make the changes as you have already suggested and I will tweak the rest later
Regards,
Graeme
Hi Graeme,
On Tue, Oct 9, 2012 at 3:58 PM, Graeme Russ graeme.russ@gmail.com wrote:
Hi Simon,
On Wed, Oct 10, 2012 at 8:15 AM, Simon Glass sjg@chromium.org wrote:
diff --git a/arch/x86/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index 44aee5f..5b359ff 100644 --- a/arch/x86/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -25,6 +25,10 @@
/* Reset vector, jumps to start16.S */
+#include <config.h>
+#ifndef CONFIG_NO_RESET_CODE
.extern start16
.section .resetvec, "ax" @@ -36,3 +40,5 @@ reset_vector:
.org 0xf nop
+#endif
Condition it out in the Makefile instead
I suspect the reason it was done here is these lines in the top-level Makefile.
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif
I have often wondered about these lines in the top-level Makefile considering they are also in arch/x86/cpu/Makefile. I keep meaning to test if they are actually needed in the top-level Makefile but keep forgetting
(I see why now - see below)
If we just take it out of the .lds file then start16.o and resetvec.o are not included in the image. But they will still be built. We could add an additional condition here perhaps, like:
I don't see a huge problem with that. Yes, it's a waste of CPU cycles during the build but really, who cares.
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) ifneq ($(CONFIG_NO_RESET_CODE),y) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif endif
Looks good for the time being (again, see beloW).
Here is the menu as I see it - what would you prefer?
- top level Makefile change
- arch/arm/cpu/Makefile change (pointless if top level Makefile
includes these files anyway)
- building everything but removing unneeded object files in the link script
Can we not invert the logic of CONFIG_X86_NO_RESET_VECTOR using some Makefile magic and then do this in arch/x86/cpu/Makefile:
START-$(INCLUDE_X86_RESET_VECTOR) += resetvec.o START-y = start.o START-$(INCLUDE_X86_RESET_VECTOR) += start16.o
Actuall, to be honest, it should be:
SOBJS-y += start.o
SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += resetvec.o SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += start16.o
SRCS := $(SOBJS16-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) OBJS16 := $(addprefix $(obj),$(SOBJS16))
all: $(obj).depend $(OBJS16) $(LIB)
start.S is not at all related to the reset vector / protected mode switch, and so can safely be moved into the main (32-bit) lib. ENTRY(_start) in the linker script and:
.section .text .code32 .globl _start .type _start, @function .globl _start .type _start, @function
in start.S will always guarantee that the code in start.S appears first in u-boot.bin.
Ah Ha! now I get it - Now I see why the top-level Makefile includes:
OBJS = $(CPUDIR)/start.o ifeq ($(CPU),x86) OBJS += $(CPUDIR)/start16.o OBJS += $(CPUDIR)/resetvec.o endif
These files are not in $(CPUDIR)/lib$(CPU).o so they must be pulled in individually!
OK, by moving start.o into the lib we can drop the first line...
Now, if we create a 16-bit lib in arch/x86/cpu/Makefile:
LIB = $(obj)lib$(CPU).o LIB16 = $(obj)lib16$(CPU).o
SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += resetvec.o SOBJS16-$(INCLUDE_X86_RESET_VECTOR) += start16.o
SOBJS-y += start.o COBJS-y += cpu.o COBJS-y += interrupts.o
SRCS := $(SOBJS16-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS16 := $(addprefix $(obj),$(SOBJS16)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB) $(LIB16)
$(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS))
$(LIB16): $(OBJS16) $(call cmd_link_o_target, $(OBJS16))
And then in the top-level Makefile:
LIBS-$(INCLUDE_X86_RESET_VECTOR) += $(CPUDIR)/lib16$(CPU).o
Much cleaner :)
(Hmmm, looking at arch/x86/lib/Makefile is appears that it is safe to mix 16- and 32-bit code in the same lib - maybe that is a better solution...)
But don't worry too much about all that in these patches - Make the changes as you have already suggested and I will tweak the rest later
Looks good - yes I will prepare a new series to send likely on Thursday.
Not that it matters for now, but who will define INCLUDE_X86_RESET_VECTOR?
Regards, Simon
Regards,
Graeme
Hi Simon,
On Wed, Oct 10, 2012 at 10:11 AM, Simon Glass sjg@chromium.org wrote:
Looks good - yes I will prepare a new series to send likely on Thursday.
Not that it matters for now, but who will define INCLUDE_X86_RESET_VECTOR?
It's calculated in the Makefile as an inversion of CONFIG_X86_NO_RESET_VECTOR
Regards,
Graeme
From: Gabe Black gabeblack@chromium.org
I suspect these includes were usually available because something else included them earlier or because they were brought in transitively.
Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/include/asm/global_data.h | 2 ++ arch/x86/include/asm/u-boot.h | 3 +++ 2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 6d29c0b..3c79508 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -33,6 +33,8 @@
#ifndef __ASSEMBLY__
+#include <asm/u-boot.h> + typedef struct global_data { /* NOTE: gd_addr MUST be first member of struct global_data! */ unsigned long gd_addr; /* Location of Global Data */ diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h index 0671b8d..e2ba845 100644 --- a/arch/x86/include/asm/u-boot.h +++ b/arch/x86/include/asm/u-boot.h @@ -36,6 +36,9 @@ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1
+#include <config.h> +#include <compiler.h> + typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */
From: Stefan Reinauer reinauer@chromium.org
coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit)
Signed-off-by: Stefan Reinauer reinauer@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/Makefile | 2 ++ .../x86/cpu}/coreboot/coreboot.c | 0 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c | 0 board/chromebook-x86/coreboot/Makefile | 2 -- 4 files changed, 2 insertions(+), 2 deletions(-) rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%) rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (100%)
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 13f5f8a..fbf5a00 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -33,10 +33,12 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).o
+COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o COBJS-$(CONFIG_SYS_COREBOOT) += tables.o COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o +COBJS-$(CONFIG_PCI) += pci.o
SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c similarity index 100% rename from board/chromebook-x86/coreboot/coreboot.c rename to arch/x86/cpu/coreboot/coreboot.c diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/arch/x86/cpu/coreboot/pci.c similarity index 100% rename from board/chromebook-x86/coreboot/coreboot_pci.c rename to arch/x86/cpu/coreboot/pci.c diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index cfcc0df..2bddf04 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -32,8 +32,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS-y += coreboot.o -COBJS-$(CONFIG_PCI) += coreboot_pci.o SOBJS-y += coreboot_start16.o SOBJS-y += coreboot_start.o
Acked-by: Gabe Black gabeblack@chromium.org
Hi Simon,
On Thu, Oct 4, 2012 at 10:39 AM, Simon Glass sjg@chromium.org wrote:
From: Stefan Reinauer reinauer@chromium.org
coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit)
You are right - this PCI code needs to move to arch/x86/lib but the naming will clash with the existing arch/x86/lib/pci.c (which is 16-bit PCI BIOS stuff)
Right, OK... It's about time I said this - All 16-bit code in U-Boot after the reset vector and protected mode switch is crap!
I did do a whole heap of work to enable U-Boot to boot Linux without the stupid BIOS stub. That work expanded upon what the coreboot guys have done and went so far as to strip the protected-mode and real-mode header components of the bzImage out. The vendor of the board I was working on lost interest and the project lost momentum and it all got too hard :(
But anyway - You will get no resistance from me if you want to take to the 16-bit code with a flame thrower (I'll even dig up my old patches, but that may take a little time)
Regards,
Graeme
Signed-off-by: Stefan Reinauer reinauer@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/coreboot/Makefile | 2 ++ .../x86/cpu}/coreboot/coreboot.c | 0 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c | 0 board/chromebook-x86/coreboot/Makefile | 2 -- 4 files changed, 2 insertions(+), 2 deletions(-) rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%) rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (100%)
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 13f5f8a..fbf5a00 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -33,10 +33,12 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).o
+COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o COBJS-$(CONFIG_SYS_COREBOOT) += tables.o COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o +COBJS-$(CONFIG_PCI) += pci.o
SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c similarity index 100% rename from board/chromebook-x86/coreboot/coreboot.c rename to arch/x86/cpu/coreboot/coreboot.c diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/arch/x86/cpu/coreboot/pci.c similarity index 100% rename from board/chromebook-x86/coreboot/coreboot_pci.c rename to arch/x86/cpu/coreboot/pci.c diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index cfcc0df..2bddf04 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -32,8 +32,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS-y += coreboot.o -COBJS-$(CONFIG_PCI) += coreboot_pci.o SOBJS-y += coreboot_start16.o SOBJS-y += coreboot_start.o
-- 1.7.7.3
Hi Graeme,
On Wed, Oct 3, 2012 at 6:12 PM, Graeme Russ graeme.russ@gmail.com wrote:
Hi Simon,
On Thu, Oct 4, 2012 at 10:39 AM, Simon Glass sjg@chromium.org wrote:
From: Stefan Reinauer reinauer@chromium.org
coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit)
You are right - this PCI code needs to move to arch/x86/lib but the naming will clash with the existing arch/x86/lib/pci.c (which is 16-bit PCI BIOS stuff)
Right, OK... It's about time I said this - All 16-bit code in U-Boot after the reset vector and protected mode switch is crap!
I did do a whole heap of work to enable U-Boot to boot Linux without the stupid BIOS stub. That work expanded upon what the coreboot guys have done and went so far as to strip the protected-mode and real-mode header components of the bzImage out. The vendor of the board I was working on lost interest and the project lost momentum and it all got too hard :(
But anyway - You will get no resistance from me if you want to take to the 16-bit code with a flame thrower (I'll even dig up my old patches, but that may take a little time)
Hmm ok. So, should we look at moving pci.c into lib/ now (and renaming it). Or leave that until later?
Not sure about removing all the 16-bit code. Are there really no users?
Regards, Simon
Regards,
Graeme
Signed-off-by: Stefan Reinauer reinauer@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/coreboot/Makefile | 2 ++ .../x86/cpu}/coreboot/coreboot.c | 0 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c | 0 board/chromebook-x86/coreboot/Makefile | 2 -- 4 files changed, 2 insertions(+), 2 deletions(-) rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%) rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (100%)
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 13f5f8a..fbf5a00 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -33,10 +33,12 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).o
+COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o COBJS-$(CONFIG_SYS_COREBOOT) += tables.o COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o +COBJS-$(CONFIG_PCI) += pci.o
SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c similarity index 100% rename from board/chromebook-x86/coreboot/coreboot.c rename to arch/x86/cpu/coreboot/coreboot.c diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/arch/x86/cpu/coreboot/pci.c similarity index 100% rename from board/chromebook-x86/coreboot/coreboot_pci.c rename to arch/x86/cpu/coreboot/pci.c diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index cfcc0df..2bddf04 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -32,8 +32,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS-y += coreboot.o -COBJS-$(CONFIG_PCI) += coreboot_pci.o SOBJS-y += coreboot_start16.o SOBJS-y += coreboot_start.o
-- 1.7.7.3
Hi Simon,
On Thu, Oct 4, 2012 at 11:17 AM, Simon Glass sjg@chromium.org wrote:
Hi Graeme,
On Wed, Oct 3, 2012 at 6:12 PM, Graeme Russ graeme.russ@gmail.com wrote:
Hi Simon,
On Thu, Oct 4, 2012 at 10:39 AM, Simon Glass sjg@chromium.org wrote:
From: Stefan Reinauer reinauer@chromium.org
coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit)
You are right - this PCI code needs to move to arch/x86/lib but the naming will clash with the existing arch/x86/lib/pci.c (which is 16-bit PCI BIOS stuff)
Right, OK... It's about time I said this - All 16-bit code in U-Boot after the reset vector and protected mode switch is crap!
I did do a whole heap of work to enable U-Boot to boot Linux without the stupid BIOS stub. That work expanded upon what the coreboot guys have done and went so far as to strip the protected-mode and real-mode header components of the bzImage out. The vendor of the board I was working on lost interest and the project lost momentum and it all got too hard :(
But anyway - You will get no resistance from me if you want to take to the 16-bit code with a flame thrower (I'll even dig up my old patches, but that may take a little time)
Hmm ok. So, should we look at moving pci.c into lib/ now (and renaming it). Or leave that until later?
I think it's about time it moved
Not sure about removing all the 16-bit code. Are there really no users?
There is exactly one - eNET and as it's maintainer, I am very happy to see that code disappear. It will give me incentive to dust of my eNET (which I have not touched for two years) and get the kernel booting without the real-mode fluff.
The main issue is how the Linux kernel is built - You end up with bzImage that looks like:
+-----------------------+ | Header | +-----------------------+ | Real-Mode code | +-----------------------+ | Decompress Code | | (Protected Mode) | +-----------------------+ | Compressed | | Protected Mode Code | | (The Kernel) | | | +-----------------------+
What you end up with is a double-copy - bzImage from storage to RAM and then a decompress by the bzImage's own decompress code. I had some script which stripped out the Real-Mode and Decompress code and produced two files (the Header and the compressed kernel) - From there you could read the header and the decompress directly from the file system to the kernel's final resting place
Now HPA will not like that one little bit :) But I'm open to suggestions
Regards,
Graeme
From: Gabe Black gabeblack@chromium.org
U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point.
It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it.
Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/pci.c | 15 +++++++++++++++ arch/x86/include/asm/pci.h | 2 +- 2 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 732ca3c..0ddc975 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -25,6 +25,21 @@ * MA 02111-1307 USA */
+#include <common.h> +#include <pci.h> +#include <asm/pci.h> + +static struct pci_controller coreboot_hose; + void pci_init_board(void) { + coreboot_hose.first_busno = 0; + coreboot_hose.last_busno = 0xff; + coreboot_hose.region_count = 0; + + pci_setup_type1(&coreboot_hose); + + pci_register_hose(&coreboot_hose); + + coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); } diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 37cc7e3..6d68ab6 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -24,7 +24,7 @@ */
#ifndef _PCI_I386_H_ -#define _PCI_I386_H_ 1 +#define _PCI_I386_H_
#define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[]
From: Vadim Bendebury vbendeb@chromium.org
This prevents the preprocessor from complaining when processing variadic macros
Signed-off-by: Vadim Bendebury vbendeb@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- board/chromebook-x86/coreboot/config.mk | 37 +++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 board/chromebook-x86/coreboot/config.mk
diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk new file mode 100644 index 0000000..f720851 --- /dev/null +++ b/board/chromebook-x86/coreboot/config.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following disclaimer +# in the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Google Inc. nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Alternatively, this software may be distributed under the terms of the +# GNU General Public License ("GPL") version 2 as published by the Free +# Software Foundation. +# + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
Acked-by: Gabe Black gabeblack@chromium.org
From: Gabe Black gabeblack@chromium.org
A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus.
On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy.
This was tested as follows:
Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot.
Signed-off-by: Gabe Black gabeblack@chromium.org Signed-off-by: Vincent Palatin vpalatin@chromium.org Signed-off-by: Stefan Reinauer reinauer@chromium.org Signed-off-by: Simon Glass sjg@chromium.org --- arch/x86/cpu/coreboot/pci.c | 26 +++++++++++++++++++++++--- 1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 0ddc975..8f94167 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -31,15 +31,35 @@
static struct pci_controller coreboot_hose;
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + hose->last_busno = max(hose->last_busno, secondary); + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_coreboot_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + void pci_init_board(void) { + coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0xff; - coreboot_hose.region_count = 0; + coreboot_hose.last_busno = 0; + + pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + coreboot_hose.region_count = 1;
pci_setup_type1(&coreboot_hose);
pci_register_hose(&coreboot_hose);
- coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); + pci_hose_scan(&coreboot_hose); }
Coreboot boards have an LPC TPM connected, so enable this. We also need to skip the reset code.
Signed-off-by: Simon Glass sjg@chromium.org --- include/configs/coreboot.h | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 2c65d74..75db176 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -37,7 +37,7 @@ #define CONFIG_SYS_COREBOOT #undef CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT - +#define CONFIG_NO_RESET_CODE
/*----------------------------------------------------------------------- * Watchdog Configuration @@ -45,6 +45,10 @@ #undef CONFIG_WATCHDOG #undef CONFIG_HW_WATCHDOG
+/* Generic TPM interfaced through LPC bus */ +#define CONFIG_GENERIC_LPC_TPM +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 + /*----------------------------------------------------------------------- * Real Time Clock Configuration */
Acked-by: Gabe Black gabeblack@chromium.org
participants (3)
-
Gabe Black -
Graeme Russ -
Simon Glass