[PATCH V2 1/2] ARM: socfpga: Permit overriding the default timer frequency
The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet.
Signed-off-by: Marek Vasut marex@denx.de Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- V2: Drop misleading comment --- include/configs/socfpga_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..54a43569dc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,12 +94,13 @@ * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif
/* * L4 Watchdog
The Denali SPL shim won't build without these options set, set them accordingly to fix the build error and let the SPL shim to work correctly.
Signed-off-by: Marek Vasut marex@denx.de Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- V2: No changes --- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 54a43569dc..29b0a5d69d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -121,6 +121,8 @@ * NAND Support */ #ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
-----Original Message----- From: Marek Vasut marex@denx.de Sent: Tuesday, February 18, 2020 1:30 AM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Subject: [PATCH V2 2/2] ARM: socfpga: Add missing Denali NAND config options
The Denali SPL shim won't build without these options set, set them accordingly to fix the build error and let the SPL shim to work correctly.
Signed-off-by: Marek Vasut marex@denx.de Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
V2: No changes
include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 54a43569dc..29b0a5d69d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -121,6 +121,8 @@
- NAND Support
*/ #ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_NAND_USE_FLASH_BBT
Didn't see Denali Nand driver use CONFIG_SYS_NAND_USE_FLASH_BBT. But, denali.c always set NAND_BBT_USE_FLASH flag.
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS --
Regards Ley Foon
Am 17.02.2020 um 18:30 schrieb Marek Vasut:
The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet.
Signed-off-by: Marek Vasut marex@denx.de Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
V2: Drop misleading comment
include/configs/socfpga_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..54a43569dc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,12 +94,13 @@
- L4 OSC1 Timer 0
*/ #ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif
/*
- L4 Watchdog
-----Original Message----- From: Marek Vasut marex@denx.de Sent: Tuesday, February 18, 2020 1:30 AM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Subject: [PATCH V2 1/2] ARM: socfpga: Permit overriding the default timer frequency
The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet.
Signed-off-by: Marek Vasut marex@denx.de Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com
V2: Drop misleading comment
include/configs/socfpga_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..54a43569dc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,12 +94,13 @@
- L4 OSC1 Timer 0
*/ #ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif
/*
- L4 Watchdog
-- 2.24.1
participants (3)
-
Marek Vasut -
Simon Goldschmidt -
Tan, Ley Foon