From: Lionel Debieve lionel.debieve@foss.st.com

New IP adds a conditional reset that impact the clock error management. It is now linked to a new compatible.

Signed-off-by: Lionel Debieve lionel.debieve@foss.st.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

drivers/rng/stm32mp1_rng.c | 61 +++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 14 deletions(-)

diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c index 8ea00e3e890..89da78c6c8b 100644 --- a/drivers/rng/stm32mp1_rng.c +++ b/drivers/rng/stm32mp1_rng.c @@ -18,22 +18,28 @@ #include <linux/iopoll.h> #include <linux/kernel.h>

-#define RNG_CR 0x00 -#define RNG_CR_RNGEN BIT(2) -#define RNG_CR_CED BIT(5) +#define RNG_CR 0x00 +#define RNG_CR_RNGEN BIT(2) +#define RNG_CR_CED BIT(5) +#define RNG_CR_CONDRST BIT(30)

-#define RNG_SR 0x04 -#define RNG_SR_SEIS BIT(6) -#define RNG_SR_CEIS BIT(5) -#define RNG_SR_SECS BIT(2) -#define RNG_SR_DRDY BIT(0) +#define RNG_SR 0x04 +#define RNG_SR_SEIS BIT(6) +#define RNG_SR_CEIS BIT(5) +#define RNG_SR_SECS BIT(2) +#define RNG_SR_DRDY BIT(0)

-#define RNG_DR 0x08 +#define RNG_DR 0x08 + +struct stm32_rng_data { + bool has_cond_reset; +};

struct stm32_rng_plat { fdt_addr_t base; struct clk clk; struct reset_ctl rst; + const struct stm32_rng_data *data; };

static int stm32_rng_read(struct udevice *dev, void *data, size_t len) @@ -83,18 +89,36 @@ static int stm32_rng_read(struct udevice *dev, void *data, size_t len) static int stm32_rng_init(struct stm32_rng_plat *pdata) { int err; + u32 cr, sr;

err = clk_enable(&pdata->clk); if (err) return err;

+ cr = readl(pdata->base + RNG_CR); + /* Disable CED */ - writel(RNG_CR_RNGEN | RNG_CR_CED, pdata->base + RNG_CR); + cr |= RNG_CR_CED; + if (pdata->data->has_cond_reset) { + cr |= RNG_CR_CONDRST; + writel(cr, pdata->base + RNG_CR); + cr &= ~RNG_CR_CONDRST; + writel(cr, pdata->base + RNG_CR); + err = readl_poll_timeout(pdata->base + RNG_CR, cr, + (!(cr & RNG_CR_CONDRST)), 10000); + if (err) + return err; + }

/* clear error indicators */ writel(0, pdata->base + RNG_SR);

- return 0; + cr |= RNG_CR_RNGEN; + writel(cr, pdata->base + RNG_CR); + + err = readl_poll_timeout(pdata->base + RNG_SR, sr, + sr & RNG_SR_DRDY, 10000); + return err; }

static int stm32_rng_cleanup(struct stm32_rng_plat *pdata) @@ -108,6 +132,8 @@ static int stm32_rng_probe(struct udevice *dev) { struct stm32_rng_plat *pdata = dev_get_plat(dev);

+ pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev); + reset_assert(&pdata->rst); udelay(20); reset_deassert(&pdata->rst); @@ -146,10 +172,17 @@ static const struct dm_rng_ops stm32_rng_ops = { .read = stm32_rng_read, };

+static const struct stm32_rng_data stm32mp13_rng_data = { + .has_cond_reset = true, +}; + +static const struct stm32_rng_data stm32_rng_data = { + .has_cond_reset = false, +}; + static const struct udevice_id stm32_rng_match[] = { - { - .compatible = "st,stm32-rng", - }, + {.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data}, + {.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data}, {}, };

Add support of STM32MP13x Rev.Y for the Silicon revision REV_ID = 0x1003.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

Changes in v2: - fix value of CPU_REV1_2 = 0x1003, because minor version in REV_ID is bitfield at SoC level (0 = 0, 1 = 1, 2 = 3, 3 = 7, 4 =F, ....)

arch/arm/mach-stm32mp/include/mach/sys_proto.h | 1 + arch/arm/mach-stm32mp/stm32mp13x.c | 3 +++ 2 files changed, 4 insertions(+)

diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 4b564e86dc5..f19a70e53e0 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -41,6 +41,7 @@ u32 get_cpu_dev(void);

#define CPU_REV1 0x1000 #define CPU_REV1_1 0x1001 +#define CPU_REV1_2 0x1003 #define CPU_REV2 0x2000 #define CPU_REV2_1 0x2001

diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp13x.c index bd3f24c349a..845d973ad1b 100644 --- a/arch/arm/mach-stm32mp/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp13x.c @@ -126,6 +126,9 @@ void get_soc_name(char name[SOC_NAME_SIZE]) case CPU_REV1_1: cpu_r = "Z"; break; + case CPU_REV1_2: + cpu_r = "Y"; + break; default: cpu_r = "?"; break;

Device tree alignment with Linux kernel v5.19-rc1 with: - ARM: dts: stm32: add UserPA13 button on stm32mp135f-dk - ARM: dts: stm32: add blue led (Linux heartbeat) on stm32mp135f-dk - ARM: dts: stm32: add EXTI interrupt-parent to pinctrl node on stm32mp131 - ARM: dts: stm32: enable RTC support on stm32mp135f-dk - ARM: dts: stm32: add RTC node on stm32mp131 - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

arch/arm/dts/stm32mp131.dtsi | 19 ++++++++++++++++++- arch/arm/dts/stm32mp135f-dk.dts | 29 +++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 950e172e455..a30989f287e 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -75,6 +75,12 @@ compatible = "fixed-clock"; clock-frequency = <99000000>; }; + + clk_rtc_k: clk-rtc-k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; };

intc: interrupt-controller@a0021000 { @@ -218,6 +224,15 @@ status = "disabled"; };

+ rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>, <&clk_rtc_k>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + bsec: efuse@5c005000 { compatible = "st,stm32mp13-bsec"; reg = <0x5c005000 0x400>; @@ -239,11 +254,13 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; pins-are-numbered;

gpioa: gpio@50002000 { diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index ee100d108ea..09d6226d598 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -6,6 +6,9 @@

/dts-v1/;

+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -23,6 +26,28 @@ reg = <0xc0000000 0x20000000>; };

+ gpio-keys { + compatible = "gpio-keys"; + + user-pa13 { + label = "User-PA13"; + linux,code = <BTN_1>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -37,6 +62,10 @@ status = "okay"; };

+&rtc { + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;

Activate the led managed in stm32mp1 board for U-Boot indication in STM32MP13F-DK device tree.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi index dfe5bbb2e34..cbe4eb56083 100644 --- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -11,8 +11,18 @@ };

config { + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; }; + + leds { + led-red { + color = <LED_COLOR_ID_RED>; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; };

&uart4 {

On STM32MP13x STMicroelectronics boards, the UART can reliably go up to 4000000 bauds when connected to the external ST-LINKV3.

This patch adds the support of higher baudrates on STMicroelectronics STM32MP13x boards with ST-LINKV3.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

include/configs/stm32mp13_st_common.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h index ec64b12f7ab..c51022b40d2 100644 --- a/include/configs/stm32mp13_st_common.h +++ b/include/configs/stm32mp13_st_common.h @@ -14,4 +14,9 @@

#include <configs/stm32mp13_common.h>

+/* uart with on-board st-link */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600, \ + 1000000, 2000000, 4000000} + #endif

Activate the RNG driver provided by OP-TEE.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

configs/stm32mp13_defconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index b5dcec78f51..3fa1642b2e4 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y @@ -44,6 +45,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_RESET_SCMI=y +CONFIG_DM_RNG=y +CONFIG_RNG_OPTEE=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y

Activate the RTC driver in STM32MP13x config.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

configs/stm32mp13_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 3fa1642b2e4..9b0c5a36b04 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -47,6 +47,8 @@ CONFIG_DM_REGULATOR_SCMI=y CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y CONFIG_RNG_OPTEE=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y

Activate the I2C driver in STM32MP13x config.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

configs/stm32mp13_defconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 9b0c5a36b04..f58c73b7c79 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -37,6 +38,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_CLK_SCMI=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y CONFIG_STM32_SDMMC2=y CONFIG_DM_ETH=y CONFIG_PINCONF=y

Activate useful commands in STM32MP13x config, already activated in stm32mp15_defconfig.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---

(no changes since v1)

configs/stm32mp13_defconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index f58c73b7c79..f94798a9ff8 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -20,17 +20,25 @@ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_UNZIP=y CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y +CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y @@ -38,9 +46,16 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_CLK_SCMI=y +CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_DM_ETH=y CONFIG_PINCONF=y CONFIG_DM_REGULATOR=y @@ -58,6 +73,7 @@ CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set CONFIG_ERRNO_STR=y +CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16

Hi Patrick

On 6/30/22 10:20, Patrick Delaunay wrote:

The stm32mp13 soc differs from the stm32mp15 in terms of clear register offset for controlling the FMP (Fast Mode Plus).

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com

(no changes since v1)

drivers/i2c/stm32f7_i2c.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index c6ae65badb7..bf2a6c9b4bd 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -267,6 +267,10 @@ static const struct stm32_i2c_data stm32mp15_data = { .fmp_clr_offset = 0x40, };

+static const struct stm32_i2c_data stm32mp13_data = {

• .fmp_clr_offset = 0x4,

+};

static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -957,6 +961,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { static const struct udevice_id stm32_i2c_of_match[] = { { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data },

• { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data }, {}

};

Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com

Thanks Patrice