On 20.10.22 23:21, Hamish Martin wrote:

The uart1 node was missing the 'clock-frequency' property. This meant the driver for this device would fail at probe. The clock for uart1 is fed from the same source as uart0 and is a fixed 200MHz clock. This is confirmed via documentation for the CN9130 SoC and from the equivalent code in Linux at: <linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi where uart0 and uart1 share a common 'clocks' definition.

Signed-off-by: Hamish Martin hamish.martin@alliedtelesis.co.nz

arch/arm/dts/armada-ap80x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/armada-ap80x.dtsi b/arch/arm/dts/armada-ap80x.dtsi index 8787a872d85e..ab3c32e0e586 100644 --- a/arch/arm/dts/armada-ap80x.dtsi +++ b/arch/arm/dts/armada-ap80x.dtsi @@ -181,7 +181,7 @@ reg-io-width = <1>; clocks = <&ap_syscon 3>; status = "disabled";

• 		clock-frequency = <200000000>;
  };
  
  watchdog: watchdog@610000 {
  

Even though we should strive to sync the A7/8k dts/dtsi files with Linux, this looks okay in the meantime. So:

Reviewed-by: Stefan Roese sr@denx.de

But I you could find some time to work on the DT sync (with driver updates where needed) I would be grateful.

Thanks, Stefan