From: Igal Liberman igall@marvell.com

Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions.

This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Signed-off-by: Igal Liberman igall@marvell.com Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

arch/arm/dts/armada-3720-db.dts | 8 +- arch/arm/dts/armada-3720-espressobin.dts | 12 +- arch/arm/dts/armada-3720-turris-mox.dts | 12 +- arch/arm/dts/armada-3720-uDPU.dts | 23 ++-- arch/arm/dts/armada-7040-db-nand.dts | 24 ++-- arch/arm/dts/armada-7040-db.dts | 22 ++-- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 30 ++--- arch/arm/dts/armada-8040-db.dts | 24 ++-- arch/arm/dts/armada-8040-mcbin.dts | 27 +++-- arch/arm/dts/armada-8040-puzzle-m801.dts | 32 ++--- arch/arm/dts/cn9130-crb-A.dts | 16 +-- arch/arm/dts/cn9130-crb-B.dts | 16 +-- board/CZ.NIC/turris_mox/turris_mox.c | 8 +- drivers/phy/marvell/comphy_a3700.c | 70 +++++------ drivers/phy/marvell/comphy_core.c | 14 +-- drivers/phy/marvell/comphy_cp110.c | 124 +++++++++++--------- drivers/phy/marvell/comphy_mux.c | 10 +- include/dt-bindings/comphy/comphy_data.h | 90 +++++++------- 18 files changed, 288 insertions(+), 274 deletions(-)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 1b1b66b94de6..fd1892ac8106 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -70,13 +70,13 @@

&comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 96a4b3d95b88..3cea5218d2b3 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -83,18 +83,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; };

phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_SATA0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA0>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 974270cc8c68..8e0ebf508d44 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -73,18 +73,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_3_125G>; };

phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 7f4b8222f4af..4b30f3cea8c7 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -108,18 +108,19 @@

&comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; - phy1 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_3_125G>; - }; - - phy2 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; - }; };

&eth0 { diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts index f249c71f6561..ccf470b317f1 100644 --- a/arch/arm/dts/armada-7040-db-nand.dts +++ b/arch/arm/dts/armada-7040-db-nand.dts @@ -129,33 +129,33 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; };

phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 6037f12f0e9f..f475fb361071 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -122,32 +122,32 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; };

phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 86df6ac0b202..ce5832c2fbd7 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -160,22 +160,22 @@ * Lane 5: Not connected */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; };

@@ -272,25 +272,25 @@ * Lane 5: SGMII2 - Connected to Topaz switch */ phy0 { - phy-type = <PHY_TYPE_SATA1>; - phy-invert = <PHY_POLARITY_RXD_INVERT>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-invert = <COMPHY_POLARITY_RXD_INVERT>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; };

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index a2b7c992a406..1edfaab682eb 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -89,22 +89,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; };

@@ -188,22 +188,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_PEX1>; + phy-type = <COMPHY_TYPE_PEX1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; };

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index b0a36e328bc9..98a582df26fe 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -171,22 +171,22 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; };

@@ -286,22 +286,23 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SGMII3>; + phy-type = <COMPHY_TYPE_SGMII3>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index ff46ce50cbc7..0becc4ff0d34 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -220,24 +220,24 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; };

@@ -367,23 +367,23 @@ * Lane 5: SGMII2 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; }; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts index fa21ef314cba..5c5e0fb2eb1e 100644 --- a/arch/arm/dts/cn9130-crb-A.dts +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -15,29 +15,29 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy4 { - phy-type = <PHY_TYPE_SFI>; - phy-speed = <PHY_SPEED_10_3125G>; + phy-type = <COMPHY_TYPE_SFI>; + phy-speed = <COMPHY_SPEED_10_3125G>; };

phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; };

diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts index 7cb587ada826..6041084a2c87 100644 --- a/arch/arm/dts/cn9130-crb-B.dts +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -15,29 +15,29 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; };

phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; };

phy3 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; };

phy4 { - phy-type = <PHY_TYPE_SFI>; - phy-speed = <PHY_SPEED_10_3125G>; + phy-type = <COMPHY_TYPE_SFI>; + phy-speed = <COMPHY_SPEED_10_3125G>; };

phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; };

diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 486680a49e88..15cbf92550e6 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -216,13 +216,13 @@ int comphy_update_map(struct comphy_map *serdes_map, int count)

if (sfpindex >= 0 && swindex >= 0) { if (sfpindex < swindex) - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; else - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; } else if (sfpindex >= 0) { - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; } else if (swindex >= 0) { - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; }

return 0; diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 12523d18a805..06822d1d12e0 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -17,33 +17,33 @@ DECLARE_GLOBAL_DATA_PTR;

struct comphy_mux_data a3700_comphy_mux_data[] = { -/* Lane 0 */ + /* Lane 0 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0 }, - { PHY_TYPE_SGMII1, 0x0 }, - { PHY_TYPE_USB3_HOST0, 0x1 }, - { PHY_TYPE_USB3_DEVICE, 0x1 } + { COMPHY_TYPE_UNCONNECTED, 0x0 }, + { COMPHY_TYPE_SGMII1, 0x0 }, + { COMPHY_TYPE_USB3_HOST0, 0x1 }, + { COMPHY_TYPE_USB3_DEVICE, 0x1 } } }, -/* Lane 1 */ + /* Lane 1 */ { 3, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SGMII0, 0x0}, - { PHY_TYPE_PEX0, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SGMII0, 0x0}, + { COMPHY_TYPE_PEX0, 0x1} } }, -/* Lane 2 */ + /* Lane 2 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SATA0, 0x0}, - { PHY_TYPE_USB3_HOST0, 0x1}, - { PHY_TYPE_USB3_DEVICE, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SATA0, 0x0}, + { COMPHY_TYPE_USB3_HOST0, 0x1}, + { COMPHY_TYPE_USB3_DEVICE, 0x1} } }, }; @@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 10. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);

/* @@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert) /* * 0. Check the Polarity invert bits */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) data |= bs_txd_inv;

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) data |= bs_rxd_inv;

reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); @@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 9. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);

/* @@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) * Set Soft ID for Host mode (Device mode works with Hard ID * detection) */ - if (type == PHY_TYPE_USB3_HOST0) { + if (type == COMPHY_TYPE_USB3_HOST0) { /* * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) * clear BIT1: set SOFT_ID = Host @@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) * comparison to 3.125 Gbps values. These register values are * stored in "sgmii_phy_init_fix" array. */ - if ((speed != PHY_SPEED_1_25G) && - (sgmii_phy_init_fix[fix_idx].addr == addr)) { + if (speed != COMPHY_SPEED_1_25G && + sgmii_phy_init_fix[fix_idx].addr == addr) { /* Use new value */ val = sgmii_phy_init_fix[fix_idx].value; if (fix_idx < fix_arr_sz) @@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide * COMPHY bit rate */ - if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ + if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x8 << rf_gen_rx_sel_shift) | (0x8 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select);

- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ + } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x6 << rf_gen_rx_sel_shift) | (0x6 << rf_gen_tx_sel_shift), @@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * registers are OK. */ debug("Running C-DPI phy init %s mode\n", - speed == PHY_SPEED_3_125G ? "2G5" : "1G"); + speed == COMPHY_SPEED_3_125G ? "2G5" : "1G"); if (get_ref_clk() == 40) comphy_sgmii_phy_init(lane, speed);

@@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 18. Check the PHY Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);

/* @@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, comphy_map->type, comphy_map->invert);

switch (comphy_map->type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break;

- case PHY_TYPE_PEX0: + case COMPHY_TYPE_PEX0: ret = comphy_pcie_power_up(comphy_map->speed, comphy_map->invert); break;

- case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, comphy_map->type, comphy_map->speed, comphy_map->invert); break;

- case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: ret = comphy_sgmii_power_up(lane, comphy_map->speed, comphy_map->invert); break;

- case PHY_TYPE_SATA0: + case COMPHY_TYPE_SATA0: ret = comphy_sata_power_up(comphy_map->invert); break;

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index cffceb1395bb..f1f061d7c116 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -29,7 +29,7 @@ static const char *get_speed_string(u32 speed) "6.25 Gbps", "10.31 Gbps" };

- if (speed < 0 || speed > PHY_SPEED_MAX) + if (speed < 0 || speed > COMPHY_SPEED_MAX) return "invalid";

return speed_strings[speed]; @@ -46,7 +46,7 @@ static const char *get_type_string(u32 type) "RXAUI0", "RXAUI1", "SFI", "IGNORE" };

- if (type < 0 || type > PHY_TYPE_MAX) + if (type < 0 || type > COMPHY_TYPE_MAX) return "invalid";

return type_strings[type]; @@ -59,7 +59,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,

for (lane = 0; lane < chip_cfg->comphy_lanes_count; lane++, comphy_map_data++) { - if (comphy_map_data->speed == PHY_SPEED_INVALID) { + if (comphy_map_data->speed == COMPHY_SPEED_INVALID) { printf("Comphy-%d: %-13s\n", lane, get_type_string(comphy_map_data->type)); } else { @@ -136,16 +136,16 @@ static int comphy_probe(struct udevice *dev) continue;

comphy_map_data[lane].speed = fdtdec_get_int( - blob, subnode, "phy-speed", PHY_TYPE_INVALID); + blob, subnode, "phy-speed", COMPHY_TYPE_INVALID); comphy_map_data[lane].type = fdtdec_get_int( - blob, subnode, "phy-type", PHY_SPEED_INVALID); + blob, subnode, "phy-type", COMPHY_SPEED_INVALID); comphy_map_data[lane].invert = fdtdec_get_int( - blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); + blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT); comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, "clk-src"); comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, "end_point"); - if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { + if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a323de7c76d0..e4ab90121c74 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -74,35 +74,47 @@ struct utmi_phy_data { * Eth_port_0 that include (SGMII0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ - {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ - {PHY_TYPE_SATA0, 0x4} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ - {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII1, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 0 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, + {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 2 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, + {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 3 */ + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, + {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 4 */ + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, + {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, + {COMPHY_TYPE_SGMII1, 0x1} } }, + /* Lane 5 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, };

struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, - {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ - {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ - {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ + /* Lane 0 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2}, + {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 2 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 3 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 4 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } }, + /* Lane 5 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } }, };

static u32 polling_with_timeout(void __iomem *addr, u32 val, @@ -868,9 +880,9 @@ static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); /* Fix the type after check the PHY and PIPE configuration */ for (lane = 0; lane < comphy_max_count; lane++) { - if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && - (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) - serdes_map[lane].type = PHY_TYPE_UNCONNECTED; + if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) && + (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED)) + serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED; } }

@@ -895,7 +907,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, /* Check if the first 4 lanes configured as By-4 */ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; lane++, ptr_comphy_map++) { - if (ptr_comphy_map->type != PHY_TYPE_PEX0) + if (ptr_comphy_map->type != COMPHY_TYPE_PEX0) break; pcie_width++; } @@ -912,14 +924,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, pcie_width = 1; } switch (ptr_comphy_map->type) { - case PHY_TYPE_UNCONNECTED: - case PHY_TYPE_IGNORE: + case COMPHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_IGNORE: continue; break; - case PHY_TYPE_PEX0: - case PHY_TYPE_PEX1: - case PHY_TYPE_PEX2: - case PHY_TYPE_PEX3: + case COMPHY_TYPE_PEX0: + case COMPHY_TYPE_PEX1: + case COMPHY_TYPE_PEX2: + case COMPHY_TYPE_PEX3: mode = COMPHY_FW_PCIE_FORMAT(pcie_width, ptr_comphy_map->clk_src, COMPHY_PCIE_MODE, @@ -928,30 +940,30 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: + case COMPHY_TYPE_SATA2: + case COMPHY_TYPE_SATA3: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, mode); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: "); debug("SGMII PHY speed in lane %d is invalid,", lane); debug(" set PHY speed to 1.25G\n"); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; }

/* @@ -965,12 +977,12 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII2: + case COMPHY_TYPE_SGMII3: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; }

mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, @@ -980,7 +992,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SFI: + case COMPHY_TYPE_SFI: mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, COMPHY_UNIT_ID0, ptr_comphy_map->speed); @@ -988,8 +1000,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: ret = comphy_rxauii_power_up(lane, hpipe_base_addr, comphy_base_addr); break; @@ -1001,9 +1013,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, if (ret == 0) { /* * If interface wans't initialized, set the lane to - * PHY_TYPE_UNCONNECTED state. + * COMPHY_TYPE_UNCONNECTED state. */ - ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; + ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED; pr_err("PLL is not locked - Failed to initialize lane %d\n", lane); } diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 98327557a899..aaef736b75dd 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -15,7 +15,7 @@ * description: this function passes over the COMPHY lanes and check if the type * is valid for specific lane. If the type is not valid, * the function update the struct and set the type of the lane as - * PHY_TYPE_UNCONNECTED + * COMPHY_TYPE_UNCONNECTED */ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes) @@ -28,7 +28,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { /* Don't check ignored COMPHYs */ - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue;

mux_opt = mux_data->mux_values; @@ -43,8 +43,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, debug("lane number %d, had invalid type %d\n", lane, comphy_map_data->type); debug("set lane %d as type %d\n", lane, - PHY_TYPE_UNCONNECTED); - comphy_map_data->type = PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED); + comphy_map_data->type = COMPHY_TYPE_UNCONNECTED; } else { debug("lane number %d, has type %d\n", lane, comphy_map_data->type); @@ -88,7 +88,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,

for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue;

/* diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 08544fa758bf..7d62dcf7fa51 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -6,53 +6,53 @@ #ifndef _COMPHY_DATA_H_ #define _COMPHY_DATA_H_

-#define PHY_SPEED_1_25G 0 -#define PHY_SPEED_1_5G 1 -#define PHY_SPEED_2_5G 2 -#define PHY_SPEED_3G 3 -#define PHY_SPEED_3_125G 4 -#define PHY_SPEED_5G 5 -#define PHY_SPEED_5_15625G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 -#define PHY_SPEED_INVALID 0xff +#define COMPHY_SPEED_1_25G 0 +#define COMPHY_SPEED_1_5G 1 +#define COMPHY_SPEED_2_5G 2 +#define COMPHY_SPEED_3G 3 +#define COMPHY_SPEED_3_125G 4 +#define COMPHY_SPEED_5G 5 +#define COMPHY_SPEED_5_15625G 6 +#define COMPHY_SPEED_6G 7 +#define COMPHY_SPEED_6_25G 8 +#define COMPHY_SPEED_10_3125G 9 +#define COMPHY_SPEED_MAX 10 +#define COMPHY_SPEED_INVALID 0xff

-#define PHY_TYPE_UNCONNECTED 0 -#define PHY_TYPE_PEX0 1 -#define PHY_TYPE_PEX1 2 -#define PHY_TYPE_PEX2 3 -#define PHY_TYPE_PEX3 4 -#define PHY_TYPE_SATA0 5 -#define PHY_TYPE_SATA1 6 -#define PHY_TYPE_SATA2 7 -#define PHY_TYPE_SATA3 8 -#define PHY_TYPE_SGMII0 9 -#define PHY_TYPE_SGMII1 10 -#define PHY_TYPE_SGMII2 11 -#define PHY_TYPE_SGMII3 12 -#define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3 14 -#define PHY_TYPE_USB3_HOST0 15 -#define PHY_TYPE_USB3_HOST1 16 -#define PHY_TYPE_USB3_DEVICE 17 -#define PHY_TYPE_XAUI0 18 -#define PHY_TYPE_XAUI1 19 -#define PHY_TYPE_XAUI2 20 -#define PHY_TYPE_XAUI3 21 -#define PHY_TYPE_RXAUI0 22 -#define PHY_TYPE_RXAUI1 23 -#define PHY_TYPE_SFI 24 -#define PHY_TYPE_IGNORE 25 -#define PHY_TYPE_MAX 26 -#define PHY_TYPE_INVALID 0xff +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PEX0 1 +#define COMPHY_TYPE_PEX1 2 +#define COMPHY_TYPE_PEX2 3 +#define COMPHY_TYPE_PEX3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SATA2 7 +#define COMPHY_TYPE_SATA3 8 +#define COMPHY_TYPE_SGMII0 9 +#define COMPHY_TYPE_SGMII1 10 +#define COMPHY_TYPE_SGMII2 11 +#define COMPHY_TYPE_SGMII3 12 +#define COMPHY_TYPE_QSGMII 13 +#define COMPHY_TYPE_USB3 14 +#define COMPHY_TYPE_USB3_HOST0 15 +#define COMPHY_TYPE_USB3_HOST1 16 +#define COMPHY_TYPE_USB3_DEVICE 17 +#define COMPHY_TYPE_XAUI0 18 +#define COMPHY_TYPE_XAUI1 19 +#define COMPHY_TYPE_XAUI2 20 +#define COMPHY_TYPE_XAUI3 21 +#define COMPHY_TYPE_RXAUI0 22 +#define COMPHY_TYPE_RXAUI1 23 +#define COMPHY_TYPE_SFI 24 +#define COMPHY_TYPE_IGNORE 25 +#define COMPHY_TYPE_MAX 26 +#define COMPHY_TYPE_INVALID 0xff

-#define PHY_POLARITY_NO_INVERT 0 -#define PHY_POLARITY_TXD_INVERT 1 -#define PHY_POLARITY_RXD_INVERT 2 -#define PHY_POLARITY_ALL_INVERT \ - (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT \ + (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)

#define UTMI_PHY_TO_USB3_HOST0 0 #define UTMI_PHY_TO_USB3_HOST1 1

From: Omri Itach omrii@marvell.com

UTMI should be initialized only for enabled device tree nodes.

This fix overrides current internal configuration array entry with the next DT entry data if error is detected during the current DT entry parsing or the current port is disabled.

This way the internal configuration structure will only contain valid ports information obtained from the DT.

Signed-off-by: Omri Itach omrii@marvell.com Signed-off-by: Ken Ma make@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_cp110.c | 51 +++++++++++++++--------------- 1 file changed, 26 insertions(+), 25 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index e4ab90121c74..82d869368858 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -715,7 +715,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, * the init split in 3 parts: * 1. Power down transceiver and PLL * 2. UTMI PHY configure - * 3. Powe up transceiver and PLL + * 3. Power up transceiver and PLL * Note: - Power down/up should be once for both UTMI PHYs * - comphy_dedicated_phys_init call this function if at least there is * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is @@ -782,45 +782,47 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count, void comphy_dedicated_phys_init(void) { struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; - int node; - int i; + int node = -1; + int node_idx;

debug_enter(); debug("Initialize USB UTMI PHYs\n");

- /* Find the UTMI phy node in device tree and go over them */ - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, - "marvell,mvebu-utmi-2.6.0"); + for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) { + /* Find the UTMI phy node in device tree */ + node = fdt_node_offset_by_compatible(gd->fdt_blob, node, + "marvell,mvebu-utmi-2.6.0"); + if (node <= 0) + break; + + /* check if node is enabled */ + if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) + continue;

- i = 0; - while (node > 0) { /* get base address of UTMI phy */ - cp110_utmi_data[i].utmi_base_addr = + cp110_utmi_data[node_idx].utmi_base_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( gd->fdt_blob, node, "reg", 0, NULL, true); - if (cp110_utmi_data[i].utmi_base_addr == NULL) { + if (!cp110_utmi_data[node_idx].utmi_base_addr) { pr_err("UTMI PHY base address is invalid\n"); - i++; continue; }

/* get usb config address */ - cp110_utmi_data[i].usb_cfg_addr = + cp110_utmi_data[node_idx].usb_cfg_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( gd->fdt_blob, node, "reg", 1, NULL, true); - if (cp110_utmi_data[i].usb_cfg_addr == NULL) { + if (!cp110_utmi_data[node_idx].usb_cfg_addr) { pr_err("UTMI PHY base address is invalid\n"); - i++; continue; }

/* get UTMI config address */ - cp110_utmi_data[i].utmi_cfg_addr = + cp110_utmi_data[node_idx].utmi_cfg_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( gd->fdt_blob, node, "reg", 2, NULL, true); - if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { + if (!cp110_utmi_data[node_idx].utmi_cfg_addr) { pr_err("UTMI PHY base address is invalid\n"); - i++; continue; }

@@ -828,21 +830,20 @@ void comphy_dedicated_phys_init(void) * get the port number (to check if the utmi connected to * host/device) */ - cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( + cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int( gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); - if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { + if (cp110_utmi_data[node_idx].utmi_phy_port == + UTMI_PHY_INVALID) { pr_err("UTMI PHY port type is invalid\n"); - i++; continue; }

- node = fdt_node_offset_by_compatible( - gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); - i++; + /* count valid UTMI unit */ + node_idx++; }

- if (i > 0) - comphy_utmi_phy_init(i, cp110_utmi_data); + if (node_idx > 0) + comphy_utmi_phy_init(node_idx, cp110_utmi_data);

debug_exit(); }

From: Igal Liberman igall@marvell.com

If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID Move the error print if phy-type is invalid Add continue to the probe loop (in a case of invalid phy) Cosmetic changes

Signed-off-by: Igal Liberman igall@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_core.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 835fc2e907f2..d3c89c97747e 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -136,21 +136,30 @@ static int comphy_probe(struct udevice *dev) if (!fdtdec_get_is_enabled(blob, subnode)) continue;

- comphy_map_data[lane].speed = fdtdec_get_int( - blob, subnode, "phy-speed", COMPHY_TYPE_INVALID); - comphy_map_data[lane].type = fdtdec_get_int( - blob, subnode, "phy-type", COMPHY_SPEED_INVALID); - comphy_map_data[lane].invert = fdtdec_get_int( - blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT); - comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, - "clk-src"); - comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, - "end_point"); + comphy_map_data[lane].type = + fdtdec_get_int(blob, subnode, "phy-type", + COMPHY_TYPE_INVALID); + if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); + continue; }

+ comphy_map_data[lane].speed = + fdtdec_get_int(blob, subnode, "phy-speed", + COMPHY_SPEED_INVALID); + + comphy_map_data[lane].invert = + fdtdec_get_int(blob, subnode, "phy-invert", + COMPHY_POLARITY_NO_INVERT); + + comphy_map_data[lane].clk_src = + fdtdec_get_bool(blob, subnode, "clk-src"); + + comphy_map_data[lane].end_point = + fdtdec_get_bool(blob, subnode, "end_point"); + lane++; }

From: Igal Liberman igall@marvell.com

This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id>

RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration.

Signed-off-by: Igal Liberman igall@marvell.com Signed-off-by: Marcin Wojtas mw@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---

cmd/mvebu/Kconfig | 7 + cmd/mvebu/Makefile | 2 +- cmd/mvebu/rx_training.c | 57 +++++++++ configs/mvebu_db_armada8k_defconfig | 1 + drivers/phy/marvell/comphy_core.c | 18 ++- drivers/phy/marvell/comphy_core.h | 14 ++ drivers/phy/marvell/comphy_cp110.c | 190 ++++++++++++++++++++++++++++ drivers/phy/marvell/comphy_hpipe.h | 62 ++++++++- include/mvebu/comphy.h | 2 +- 9 files changed, 348 insertions(+), 5 deletions(-) create mode 100644 cmd/mvebu/rx_training.c

diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index f1eb00614dd6..f0e4f884d703 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -49,4 +49,11 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted

+config CMD_MVEBU_RX_TRAINING + bool "rx_training" + depends on TARGET_MVEBU_ARMADA_8K + default n + help + Perform RX training sequence + endmenu diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile index 96829c48ebdc..79299b0814f4 100644 --- a/cmd/mvebu/Makefile +++ b/cmd/mvebu/Makefile @@ -4,5 +4,5 @@ # # https://spdx.org/licenses

- obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o +obj-$(CONFIG_CMD_MVEBU_RX_TRAINING) += rx_training.o diff --git a/cmd/mvebu/rx_training.c b/cmd/mvebu/rx_training.c new file mode 100644 index 000000000000..4bae7653aca3 --- /dev/null +++ b/cmd/mvebu/rx_training.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <command.h> +#include <console.h> +#include <dm.h> +#include <fdtdec.h> +#include <dm/device-internal.h> +#include <mvebu/comphy.h> + +int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *dev; + struct uclass *uc; + int ret, cp_index, comphy_index, i = 0; + + if (argc != 3) { + printf("missing arguments\n"); + return -1; + } + + cp_index = simple_strtoul(argv[1], NULL, 16); + comphy_index = simple_strtoul(argv[2], NULL, 16); + + ret = uclass_get(UCLASS_MISC, &uc); + if (ret) { + printf("Couldn't find UCLASS_MISC\n"); + return ret; + } + + uclass_foreach_dev(dev, uc) { + if (!(memcmp(dev->name, "comphy", 5))) { + if (i == cp_index) { + comphy_rx_training(dev, comphy_index); + return 0; + } + + i++; + } + } + + printf("Coudn't find comphy %d\n", cp_index); + + return 0; +} + +U_BOOT_CMD( + rx_training, 3, 0, rx_training_cmd, + "rx_training <cp id> <comphy id>\n", + "\n\tRun RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)" +); diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index ffe8e029050f..96baea76fc1c 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_MVEBU_RX_TRAINING=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index d8df7ac949a3..b29decd82693 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -71,6 +71,16 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg, } }

+int comphy_rx_training(struct udevice *dev, u32 lane) +{ + struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev); + + if (chip_cfg->rx_training) + return chip_cfg->rx_training(chip_cfg, lane); + + return 0; +} + __weak int comphy_update_map(struct comphy_map *serdes_map, int count) { return 0; @@ -114,11 +124,15 @@ static int comphy_probe(struct udevice *dev) fdtdec_locate_array(blob, node, "mux-lane-order", chip_cfg->comphy_lanes_count);

- if (device_is_compatible(dev, "marvell,comphy-armada-3700")) + if (device_is_compatible(dev, "marvell,comphy-armada-3700")) { chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; + chip_cfg->rx_training = NULL; + }

- if (device_is_compatible(dev, "marvell,comphy-cp110")) + if (device_is_compatible(dev, "marvell,comphy-cp110")) { chip_cfg->ptr_comphy_chip_init = comphy_cp110_init; + chip_cfg->rx_training = comphy_cp110_sfi_rx_training; + }

/* * Bail out if no chip_init function is defined, e.g. no diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h index c08677e56d2e..32895dc4aa3d 100644 --- a/drivers/phy/marvell/comphy_core.h +++ b/drivers/phy/marvell/comphy_core.h @@ -84,6 +84,7 @@ struct chip_serdes_phy_config { struct comphy_mux_data *mux_data; int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *, struct comphy_map *); + int (*rx_training)(struct chip_serdes_phy_config *, u32); void __iomem *comphy_base_addr; void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; @@ -151,6 +152,8 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg, #ifdef CONFIG_ARMADA_8K int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map); +int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane); #else static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map) @@ -161,6 +164,17 @@ static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, */ return -1; } + +static inline int comphy_cp110_sfi_rx_training( + struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane) +{ + /* + * This function should never be called in this configuration, so + * lets return an error here. + */ + return -1; +} #endif

void comphy_dedicated_phys_init(void); diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 72563f8bc1c5..11dc46b28a63 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -133,6 +133,196 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val, return 0; }

+/* This function performs RX training for single FFE value. + * The result of the RX training is located in: + * Saved DFE values Register[10:15]. + * + * The result is returned to the caller using *result + * + * Return '1' on succsess. + * Return '0' on failure. + */ +static int comphy_cp110_test_single_ffe( + struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane, u32 ffe, u32 *result) +{ + u32 mask, data, timeout; + void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; + void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane); + void __iomem *sd_ip_addr = SD_ADDR(hpipe_base_addr, lane); + + /* Configure PRBS counters */ + mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK; + data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + mask = HPIPE_PHY_TEST_DATA_MASK; + data = 0x64 << HPIPE_PHY_TEST_DATA_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask); + + mask = HPIPE_PHY_TEST_EN_MASK; + data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + mdelay(50); + + /* Set the FFE value */ + mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; + data = ffe << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + + /* Start RX training */ + mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK; + data = 1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET; + reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask); + + /* Check the result of RX training */ + timeout = RX_TRAINING_TIMEOUT; + while (timeout) { + data = readl(sd_ip_addr + SD_EXTERNAL_STATUS1_REG); + if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK) + break; + mdelay(1); + timeout--; + } + + if (timeout == 0) + return 0; + + if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK) + return 0; + + /* Stop RX training */ + mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK; + data = 0 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET; + reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask); + + /* Read the result */ + data = readl(hpipe_addr + HPIPE_SAVED_DFE_VALUES_REG); + data &= HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK; + data >>= HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET; + *result = data; + + printf("FFE = %d, result = 0x%x\n", ffe, *result); + + /* Clear the PRBS counters */ + mask = HPIPE_PHY_TEST_RESET_MASK; + data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET; + mask |= HPIPE_PHY_TEST_EN_MASK; + data |= 0x0 << HPIPE_PHY_TEST_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + mask = HPIPE_PHY_TEST_RESET_MASK; + data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + return 1; +} + +/* This function performs RX training for all FFE possible values. + * We get the result for each FFE and eventually the best FFE will + * be used and set to the HW. + * + * Return '1' on succsess. + * Return '0' on failure. + */ +int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane) +{ + u32 mask, data, i, rx_train_result; + u32 max_rx_train = 0, max_rx_train_index = 0; + void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; + void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane); + int ret; + + debug_enter(); + + if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) { + pr_err("Comphy %d isn't configured to SFI\n", lane); + return 0; + } + + /* Configure SQ threshold and CDR lock */ + mask = HPIPE_SQUELCH_THRESH_IN_MASK; + data = 0xc << HPIPE_SQUELCH_THRESH_IN_OFFSET; + reg_set(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG, data, mask); + + mask = HPIPE_SQ_DEGLITCH_WIDTH_P_MASK; + data = 0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET; + mask |= HPIPE_SQ_DEGLITCH_WIDTH_N_MASK; + data |= 0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET; + mask |= HPIPE_SQ_DEGLITCH_EN_MASK; + data |= 0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_SQ_GLITCH_FILTER_CTRL, data, mask); + + mask = HPIPE_CDR_LOCK_DET_EN_MASK; + data = 0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); + + udelay(100); + + /* Determine if we have a cable attached to this comphy, if not, + * we can't perform RX training. + */ + data = readl(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG); + if (data & HPIPE_SQUELCH_DETECTED_MASK) { + pr_err("Squelsh is not detected, can't perform RX training\n"); + return 0; + } + + data = readl(hpipe_addr + HPIPE_LOOPBACK_REG); + if (!(data & HPIPE_CDR_LOCK_MASK)) { + pr_err("CDR is not locked, can't perform RX training\n"); + return 0; + } + + /* Do preparations for RX training */ + mask = HPIPE_DFE_RES_FORCE_MASK; + data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); + + mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; + data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; + data |= 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + + /* Performs RX training for all possible FFE (Feed Forward + * Equalization, possible values are 0-7). + * We update the best value reached and the FFE which gave this value. + */ + for (i = 0; i < MAX_NUM_OF_FFE; i++) { + rx_train_result = 0; + ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane, + i, &rx_train_result); + + if (ret && (rx_train_result > max_rx_train)) { + max_rx_train = rx_train_result; + max_rx_train_index = i; + } + } + + /* If we were able to determine which FFE gives the best value, + * now we need to set it and run RX training again (only for this + * FFE). + */ + if (max_rx_train) { + ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane, + max_rx_train_index, + &rx_train_result); + if (ret == 1) + printf("RX Training passed(FFE = %d, result = 0x%x)\n", + max_rx_train_index, rx_train_result); + } else { + pr_err("RX training failed\n"); + ret = 0; + } + + debug_exit(); + + return ret; +} + static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, void __iomem *comphy_base) { diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index a692035c9417..cf2f986281ea 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -6,6 +6,9 @@ #ifndef _COMPHY_HPIPE_H_ #define _COMPHY_HPIPE_H_

+#define MAX_NUM_OF_FFE 8 +#define RX_TRAINING_TIMEOUT 500 + /* SerDes IP register */ #define SD_EXTERNAL_CONFIG0_REG 0 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 @@ -52,6 +55,11 @@ #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)

+#define SD_EXTERNAL_STATUS_REG 0xc +#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7 +#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \ + (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) + #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ @@ -66,6 +74,14 @@ #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)

+#define SD_EXTERNAL_STATUS1_REG 0x1c +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET 0 +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK \ + (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET) +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET 1 +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK \ + (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET) + /* HPIPE register */ #define HPIPE_PWR_PLL_REG 0x4 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 @@ -88,7 +104,13 @@ #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)

-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 +#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8 +#define HPIPE_SQUELCH_THRESH_IN_MASK \ + (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) +#define HPIPE_SQUELCH_DETECTED_OFFSET 14 +#define HPIPE_SQUELCH_DETECTED_MASK \ + (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET)

#define HPIPE_DFE_REG0 0x01C #define HPIPE_DFE_RES_FORCE_OFFSET 15 @@ -215,10 +237,32 @@ #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)

+#define HPIPE_PHY_TEST_CONTROL_REG 0x54 +#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4 +#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \ + (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) +#define HPIPE_PHY_TEST_RESET_OFFSET 14 +#define HPIPE_PHY_TEST_RESET_MASK \ + (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) +#define HPIPE_PHY_TEST_EN_OFFSET 15 +#define HPIPE_PHY_TEST_EN_MASK \ + (0x1 << HPIPE_PHY_TEST_EN_OFFSET) + +#define HPIPE_PHY_TEST_DATA_REG 0x6c +#define HPIPE_PHY_TEST_DATA_OFFSET 0 +#define HPIPE_PHY_TEST_DATA_MASK \ + (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) + #define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 #define HPIPE_LOOPBACK_SEL_MASK \ (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) +#define HPIPE_CDR_LOCK_OFFSET 7 +#define HPIPE_CDR_LOCK_MASK \ + (0x1 << HPIPE_CDR_LOCK_OFFSET) +#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8 +#define HPIPE_CDR_LOCK_DET_EN_MASK \ + (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)

#define HPIPE_SYNC_PATTERN_REG 0x090 #define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10 @@ -382,6 +426,17 @@ #define HPIPE_OS_PH_VALID_MASK \ (0x1 << HPIPE_OS_PH_VALID_OFFSET)

+#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8 +#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0 +#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) +#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4 +#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) +#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8 +#define HPIPE_SQ_DEGLITCH_EN_MASK \ + (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) + #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 #define HPIPE_TRAIN_PAT_NUM_MASK \ @@ -452,6 +507,11 @@ #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)

+#define HPIPE_SAVED_DFE_VALUES_REG 0x328 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \ + (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) + #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ diff --git a/include/mvebu/comphy.h b/include/mvebu/comphy.h index cde7a022af1c..4d1b70393b20 100644 --- a/include/mvebu/comphy.h +++ b/include/mvebu/comphy.h @@ -16,7 +16,7 @@ struct comphy_map { bool end_point; };

+int comphy_rx_training(struct udevice *dev, u32 lane); int comphy_update_map(struct comphy_map *serdes_map, int count);

#endif /* _MVEBU_COMPHY_H_ */ -

From: Marcin Wojtas mw@semihalf.com

Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it.

This patch removes unused definitions.

Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

arch/arm/dts/armada-8040-mcbin.dts | 2 +- drivers/phy/marvell/comphy_core.c | 14 +++---- drivers/phy/marvell/comphy_cp110.c | 3 -- include/dt-bindings/comphy/comphy_data.h | 50 ++++++++++-------------- 4 files changed, 27 insertions(+), 42 deletions(-)

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 98a582df26fe..a6ef40138da3 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -302,7 +302,7 @@ phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <COMPHY_TYPE_SGMII3>; + phy-type = <COMPHY_TYPE_SGMII2>; phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 45dba738662c..929360792630 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -24,9 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; static const char *get_speed_string(u32 speed) { static const char * const speed_strings[] = { - "1.25 Gbps", "1.5 Gbps", "2.5 Gbps", - "3.0 Gbps", "3.125 Gbps", "5 Gbps", - "5.125 Gpbs", "6 Gbps", "6.25 Gbps", + "1.25 Gbps", "2.5 Gbps", "3.125 Gbps", + "5 Gbps", "5.125 Gpbs", "6 Gbps", "10.3125 Gbps" };

@@ -40,11 +39,10 @@ static const char *get_type_string(u32 type) { static const char * const type_strings[] = { "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", - "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", - "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3" - "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", - "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "SFI", "IGNORE" + "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2", + "USB3", "USB3_HOST0", "USB3_HOST1", + "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP", + "IGNORE" };

if (type < 0 || type > COMPHY_TYPE_MAX) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 11dc46b28a63..620a749bb1f8 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1130,8 +1130,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - case COMPHY_TYPE_SATA2: - case COMPHY_TYPE_SATA3: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, @@ -1166,7 +1164,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, mode); break; case COMPHY_TYPE_SGMII2: - case COMPHY_TYPE_SGMII3: if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 7d62dcf7fa51..8e9270598924 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -7,16 +7,13 @@ #define _COMPHY_DATA_H_

#define COMPHY_SPEED_1_25G 0 -#define COMPHY_SPEED_1_5G 1 -#define COMPHY_SPEED_2_5G 2 -#define COMPHY_SPEED_3G 3 -#define COMPHY_SPEED_3_125G 4 -#define COMPHY_SPEED_5G 5 -#define COMPHY_SPEED_5_15625G 6 -#define COMPHY_SPEED_6G 7 -#define COMPHY_SPEED_6_25G 8 -#define COMPHY_SPEED_10_3125G 9 -#define COMPHY_SPEED_MAX 10 +#define COMPHY_SPEED_2_5G 1 +#define COMPHY_SPEED_3_125G 2 +#define COMPHY_SPEED_5G 3 +#define COMPHY_SPEED_5_15625G 4 +#define COMPHY_SPEED_6G 5 +#define COMPHY_SPEED_10_3125G 6 +#define COMPHY_SPEED_MAX 7 #define COMPHY_SPEED_INVALID 0xff

#define COMPHY_TYPE_UNCONNECTED 0 @@ -26,26 +23,19 @@ #define COMPHY_TYPE_PEX3 4 #define COMPHY_TYPE_SATA0 5 #define COMPHY_TYPE_SATA1 6 -#define COMPHY_TYPE_SATA2 7 -#define COMPHY_TYPE_SATA3 8 -#define COMPHY_TYPE_SGMII0 9 -#define COMPHY_TYPE_SGMII1 10 -#define COMPHY_TYPE_SGMII2 11 -#define COMPHY_TYPE_SGMII3 12 -#define COMPHY_TYPE_QSGMII 13 -#define COMPHY_TYPE_USB3 14 -#define COMPHY_TYPE_USB3_HOST0 15 -#define COMPHY_TYPE_USB3_HOST1 16 -#define COMPHY_TYPE_USB3_DEVICE 17 -#define COMPHY_TYPE_XAUI0 18 -#define COMPHY_TYPE_XAUI1 19 -#define COMPHY_TYPE_XAUI2 20 -#define COMPHY_TYPE_XAUI3 21 -#define COMPHY_TYPE_RXAUI0 22 -#define COMPHY_TYPE_RXAUI1 23 -#define COMPHY_TYPE_SFI 24 -#define COMPHY_TYPE_IGNORE 25 -#define COMPHY_TYPE_MAX 26 +#define COMPHY_TYPE_SGMII0 7 +#define COMPHY_TYPE_SGMII1 8 +#define COMPHY_TYPE_SGMII2 9 +#define COMPHY_TYPE_USB3 10 +#define COMPHY_TYPE_USB3_HOST0 11 +#define COMPHY_TYPE_USB3_HOST1 12 +#define COMPHY_TYPE_USB3_DEVICE 13 +#define COMPHY_TYPE_RXAUI0 14 +#define COMPHY_TYPE_RXAUI1 15 +#define COMPHY_TYPE_SFI 16 +#define COMPHY_TYPE_AP 17 +#define COMPHY_TYPE_IGNORE 18 +#define COMPHY_TYPE_MAX 19 #define COMPHY_TYPE_INVALID 0xff

#define COMPHY_POLARITY_NO_INVERT 0

From: Grzegorz Jaszczyk jaz@semihalf.com

Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration.

Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_cp110.c | 133 ++--------------------------- 1 file changed, 9 insertions(+), 124 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 9f80a3fda4b1..cbfc89cb0c36 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -323,128 +323,6 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, return ret; }

-static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - - debug_enter(); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - mask |= COMMON_PHY_PHY_MODE_MASK; - data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* release from hard reset */ - mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* Set PIPE soft reset */ - mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - /* Set PHY datapath width mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - /* Set Data bus width USB mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - /* Set CORE_CLK output frequency for 250Mhz */ - mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); - /* Set PLL ready delay for 0x2 */ - reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); - /* Set reference clock to come from group 1 - 25Mhz */ - reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - /* Set reference frequcency select - 0x2 */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - /* Set PHY mode to USB - 0x5 */ - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Set the amount of time spent in the LoZ state - set for 0x7 */ - reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - /* Set max PHY generation setting - 5Gbps */ - reg_set(hpipe_addr + HPIPE_INTERFACE_REG, - 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, - HPIPE_INTERFACE_GEN_MAX_MASK); - /* Set select data width 20Bit (SEL_BITS[2:0]) */ - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, - HPIPE_LOOPBACK_SEL_MASK); - /* select de-emphasize 3.5db */ - reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, - 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, - HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); - /* override tx margining from the MAC */ - reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, - 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, - HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); - - /* Start analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); - /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ - mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; - data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; - /* Set Override PHY DFE control pins for 0x1 */ - mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; - data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; - /* Set Spread Spectrum Clock Enable fot 0x1 */ - mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; - data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); - /* End of analog parameters */ - - debug("stage: Comphy power up\n"); - /* Release from PIPE soft reset */ - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* wait 15ms - for comphy calibration done */ - debug("stage: Check PLL\n"); - /* Read lane status */ - addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; - data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - hpipe_addr + HPIPE_LANE_STATUS1_REG, data); - pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); - ret = 0; - } - - debug_exit(); - return ret; -} - static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, u32 lane, u32 mode) { @@ -960,9 +838,16 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: + mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); + break; case COMPHY_TYPE_USB3_DEVICE: - ret = comphy_usb3_power_up(lane, hpipe_base_addr, - comphy_base_addr); + mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); break; case COMPHY_TYPE_SGMII0: case COMPHY_TYPE_SGMII1:

From: Grzegorz Jaszczyk jaz@semihalf.com

Now the comphy configuration is handled in atf, therefore there is no need to configure phy or pipe selector in u-boot, it is configured by atf for each particular pair: lane and mode.

Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Reviewed-by: Igal Liberman igall@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_cp110.c | 94 ------------------------------ 1 file changed, 94 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index e71b70428464..195b455241fa 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -66,58 +66,6 @@ struct utmi_phy_data { u32 utmi_phy_port; };

-/* - * For CP-110 we have 2 Selector registers "PHY Selectors", - * and "PIPE Selectors". - * PIPE selector include USB and PCIe options. - * PHY selector include the Ethernet and SATA options, every Ethernet - * option has different options, for example: serdes lane2 had option - * Eth_port_0 that include (SGMII0, RXAUI0, SFI) - */ -struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - /* Lane 0 */ - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, - {COMPHY_TYPE_SATA1, 0x4} } }, - /* Lane 1 */ - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, - {COMPHY_TYPE_SATA0, 0x4} } }, - /* Lane 2 */ - {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, - {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, - {COMPHY_TYPE_SATA0, 0x4} } }, - /* Lane 3 */ - {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, - {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, - /* Lane 4 */ - {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, - {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, - {COMPHY_TYPE_SGMII1, 0x1} } }, - /* Lane 5 */ - {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, - {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, -}; - -struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { - /* Lane 0 */ - {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } }, - /* Lane 1 */ - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, - {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2}, - {COMPHY_TYPE_PEX0, 0x4} } }, - /* Lane 2 */ - {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, - {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, - /* Lane 3 */ - {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, - {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, - /* Lane 4 */ - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, - {COMPHY_TYPE_USB3_HOST1, 0x1}, - {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } }, - /* Lane 5 */ - {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } }, -}; - static u32 polling_with_timeout(void __iomem *addr, u32 val, u32 mask, unsigned long usec_timout) { @@ -574,45 +522,6 @@ void comphy_dedicated_phys_init(void) debug_exit(); }

-static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, - struct comphy_map *serdes_map) -{ - void __iomem *comphy_base_addr; - struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; - struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; - u32 lane, comphy_max_count; - - comphy_max_count = ptr_chip_cfg->comphy_lanes_count; - comphy_base_addr = ptr_chip_cfg->comphy_base_addr; - - /* - * Copy the SerDes map configuration for PIPE map and PHY map - * the comphy_mux_init modify the type of the lane if the type - * is not valid because we have 2 selectores run the - * comphy_mux_init twice and after that update the original - * serdes_map - */ - for (lane = 0; lane < comphy_max_count; lane++) { - comphy_map_pipe_data[lane].type = serdes_map[lane].type; - comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; - comphy_map_phy_data[lane].type = serdes_map[lane].type; - comphy_map_phy_data[lane].speed = serdes_map[lane].speed; - } - ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; - comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, - comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); - - ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; - comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, - comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); - /* Fix the type after check the PHY and PIPE configuration */ - for (lane = 0; lane < comphy_max_count; lane++) { - if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) && - (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED)) - serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED; - } -} - int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map) { @@ -628,9 +537,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, comphy_base_addr = ptr_chip_cfg->comphy_base_addr; hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;

- /* Config Comphy mux configuration */ - comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); - /* Check if the first 4 lanes configured as By-4 */ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; lane++, ptr_comphy_map++) {

From: Igal Liberman igall@marvell.com

Currently, we don't pass id for SGMII 0/1. A bug in comphy selector configuration was found (in comphy firmware), after fixing it, SGMII0/1 have different configuration, so we need to pass the ID the firmware.

Signed-off-by: Igal Liberman igall@marvell.com Reviewed-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_cp110.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 2a22a67a4656..55202888194d 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -522,7 +522,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, { struct comphy_map *ptr_comphy_map; void __iomem *comphy_base_addr, *hpipe_base_addr; - u32 comphy_max_count, lane, ret = 0; + u32 comphy_max_count, lane, id, ret = 0; u32 pcie_width = 0; u32 mode;

@@ -591,34 +591,17 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_SGMII0: case COMPHY_TYPE_SGMII1: - if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { - debug("Warning: "); - debug("SGMII PHY speed in lane %d is invalid,", - lane); - debug(" set PHY speed to 1.25G\n"); - ptr_comphy_map->speed = COMPHY_SPEED_1_25G; - } - - /* - * UINIT_ID not relevant for SGMII0 and SGMII1 - will be - * ignored by firmware - */ - mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, - COMPHY_UNIT_ID0, - ptr_comphy_map->speed); - ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, - ptr_chip_cfg->comphy_base_addr, lane, - mode); - break; case COMPHY_TYPE_SGMII2: + /* Calculate SGMII ID */ + id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0; + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); ptr_comphy_map->speed = COMPHY_SPEED_1_25G; }

- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, - COMPHY_UNIT_ID2, + mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id, ptr_comphy_map->speed); ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, ptr_chip_cfg->comphy_base_addr, lane,

From: Igal Liberman igall@marvell.com

It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly

Signed-off-by: Igal Liberman igall@marvell.com Reviewed-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_cp110.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index d9a94f9d0d09..489a17c76f42 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -553,10 +553,10 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, } switch (ptr_comphy_map->type) { case COMPHY_TYPE_UNCONNECTED: + mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT; ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF, ptr_chip_cfg->comphy_base_addr, - lane, - ptr_comphy_map->type); + lane, mode); case COMPHY_TYPE_IGNORE: continue; break;

From: Grzegorz Jaszczyk jaz@semihalf.com

According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used.

This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change.

This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization.

Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---

arch/arm/dts/armada-cp110.dtsi | 36 +++++++++++++++++------------- drivers/phy/marvell/comphy_cp110.c | 35 ++++++++++++++++++++++------- drivers/phy/marvell/utmi_phy.h | 10 ++++----- 3 files changed, 53 insertions(+), 28 deletions(-)

diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi index d9c445601266..e9440a3368cd 100644 --- a/arch/arm/dts/armada-cp110.dtsi +++ b/arch/arm/dts/armada-cp110.dtsi @@ -192,22 +192,28 @@ max-lanes = <6>; };

- CP110_LABEL(utmi0): utmi@580000 { - compatible = "marvell,mvebu-utmi-2.6.0"; - reg = <0x580000 0x1000>, /* utmi-unit */ - <0x440420 0x4>, /* usb-cfg */ - <0x440440 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB3_HOST0>; - status = "disabled"; - }; + CP110_LABEL(utmi): utmi@580000 { + compatible = "marvell,mvebu-utmi"; + reg = <0x580000 0xc>; /* utmi-common-pll */ + #address-cells = <1>; + #size-cells = <1>; + CP110_LABEL(utmi0): utmi@58000c { + compatible = "marvell,mvebu-utmi-2.6.0"; + reg = <0x58000c 0x100>,/* utmi-unit */ + <0x440420 0x4>, /* usb-cfg */ + <0x440440 0x4>; /* utmi-cfg */ + utmi-port = <UTMI_PHY_TO_USB3_HOST0>; + status = "disabled"; + };

- CP110_LABEL(utmi1): utmi@581000 { - compatible = "marvell,mvebu-utmi-2.6.0"; - reg = <0x581000 0x1000>, /* utmi-unit */ - <0x440420 0x4>, /* usb-cfg */ - <0x440444 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB3_HOST1>; - status = "disabled"; + CP110_LABEL(utmi1): utmi@58100c { + compatible = "marvell,mvebu-utmi-2.6.0"; + reg = <0x58100c 0x100>,/* utmi-unit */ + <0x440420 0x4>, /* usb-cfg */ + <0x440444 0x4>; /* utmi-cfg */ + utmi-port = <UTMI_PHY_TO_USB3_HOST1>; + status = "disabled"; + }; };

CP110_LABEL(sdhci0): sdhci@780000 { diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 489a17c76f42..349109b6dc08 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -55,6 +55,7 @@ DECLARE_GLOBAL_DATA_PTR; #define COMPHY_UNIT_ID3 3

struct utmi_phy_data { + void __iomem *utmi_pll_addr; void __iomem *utmi_base_addr; void __iomem *usb_cfg_addr; void __iomem *utmi_cfg_addr; @@ -264,7 +265,8 @@ static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, return; }

-static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, +static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr, + void __iomem *utmi_base_addr, void __iomem *usb_cfg_addr, void __iomem *utmi_cfg_addr, u32 utmi_phy_port) @@ -282,10 +284,10 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; - reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); + reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);

/* Impedance Calibration Threshold Setting */ - reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, + reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);

@@ -322,7 +324,8 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, return; }

-static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, +static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr, + void __iomem *utmi_base_addr, void __iomem *usb_cfg_addr, void __iomem *utmi_cfg_addr, u32 utmi_phy_port) { @@ -341,7 +344,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, UTMI_CTRL_STATUS0_TEST_SEL_MASK);

debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); - addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; + addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG; data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; mask = data; data = polling_with_timeout(addr, data, mask, 100); @@ -360,7 +363,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, ret = 0; }

- addr = utmi_base_addr + UTMI_PLL_CTRL_REG; + addr = utmi_pll_addr + UTMI_PLL_CTRL_REG; data = UTMI_PLL_CTRL_PLL_RDY_MASK; mask = data; data = polling_with_timeout(addr, data, mask, 100); @@ -411,14 +414,16 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count, } /* UTMI configure */ for (i = 0; i < utmi_phy_count; i++) { - comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, + comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr, + cp110_utmi_data[i].utmi_base_addr, cp110_utmi_data[i].usb_cfg_addr, cp110_utmi_data[i].utmi_cfg_addr, cp110_utmi_data[i].utmi_phy_port); } /* UTMI Power up */ for (i = 0; i < utmi_phy_count; i++) { - if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, + if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr, + cp110_utmi_data[i].utmi_base_addr, cp110_utmi_data[i].usb_cfg_addr, cp110_utmi_data[i].utmi_cfg_addr, cp110_utmi_data[i].utmi_phy_port)) { @@ -453,6 +458,7 @@ void comphy_dedicated_phys_init(void) struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; int node = -1; int node_idx; + int parent = -1;

debug_enter(); debug("Initialize USB UTMI PHYs\n"); @@ -468,6 +474,19 @@ void comphy_dedicated_phys_init(void) if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) continue;

+ parent = fdt_parent_offset(gd->fdt_blob, node); + if (parent <= 0) + break; + + /* get base address of UTMI PLL */ + cp110_utmi_data[node_idx].utmi_pll_addr = + (void __iomem *)fdtdec_get_addr_size_auto_noparent( + gd->fdt_blob, parent, "reg", 0, NULL, true); + if (!cp110_utmi_data[node_idx].utmi_pll_addr) { + pr_err("UTMI PHY PLL address is invalid\n"); + continue; + } + /* get base address of UTMI phy */ cp110_utmi_data[node_idx].utmi_base_addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h index fa6bf3c9141e..d1cad07cf50f 100644 --- a/drivers/phy/marvell/utmi_phy.h +++ b/drivers/phy/marvell/utmi_phy.h @@ -45,7 +45,7 @@ #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \ (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)

-#define UTMI_TX_CH_CTRL_REG 0xC +#define UTMI_TX_CH_CTRL_REG 0x0 #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12 #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \ (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) @@ -56,7 +56,7 @@ #define UTMI_TX_CH_CTRL_AMP_MASK \ (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)

-#define UTMI_RX_CH_CTRL0_REG 0x14 +#define UTMI_RX_CH_CTRL0_REG 0x8 #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 #define UTMI_RX_CH_CTRL0_SQ_DET_MASK \ (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) @@ -64,7 +64,7 @@ #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \ (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)

-#define UTMI_RX_CH_CTRL1_REG 0x18 +#define UTMI_RX_CH_CTRL1_REG 0xc #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \ (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) @@ -72,7 +72,7 @@ #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \ (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)

-#define UTMI_CTRL_STATUS0_REG 0x24 +#define UTMI_CTRL_STATUS0_REG 0x18 #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22 #define UTMI_CTRL_STATUS0_SUSPENDM_MASK \ (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET) @@ -80,7 +80,7 @@ #define UTMI_CTRL_STATUS0_TEST_SEL_MASK \ (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)

-#define UTMI_CHGDTC_CTRL_REG 0x38 +#define UTMI_CHGDTC_CTRL_REG 0x2c #define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8 #define UTMI_CHGDTC_CTRL_VDAT_MASK \ (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)

From: Grzegorz Jaszczyk jaz@semihalf.com

- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values.

Signed-off-by: Grzegorz Jaszczyk jaz@semihalf.com Signed-off-by: Stefan Roese sr@denx.de ---

drivers/phy/marvell/comphy_cp110.c | 23 ++++++++++++++++++----- drivers/phy/marvell/utmi_phy.h | 9 +++++++++ 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 576538feb706..418318d12f6b 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -288,21 +288,34 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr, reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);

/* Impedance Calibration Threshold Setting */ - reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, - 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, - UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); + mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; + data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; + reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask); + + /* Start Impedance and PLL Calibration */ + mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; + data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); + mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; + data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); + reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);

/* Set LS TX driver strength coarse control */ mask = UTMI_TX_CH_CTRL_AMP_MASK; data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; + mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; + data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; + mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; + data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);

/* Enable SQ */ mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; - data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; + data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; /* Enable analog squelch detect */ mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; - data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; + data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);

/* Set External squelch calibration number */ diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h index d1cad07cf50f..8a570bae7390 100644 --- a/drivers/phy/marvell/utmi_phy.h +++ b/drivers/phy/marvell/utmi_phy.h @@ -38,6 +38,12 @@ #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \ (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \ + (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \ + (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \ (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) @@ -57,6 +63,9 @@ (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)

#define UTMI_RX_CH_CTRL0_REG 0x8 +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \ + (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 #define UTMI_RX_CH_CTRL0_SQ_DET_MASK \ (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)