[U-Boot] [PATCH 1/2] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers accordingly, no functional change. The S10 enables the WDT only in SPL, but does not enable it in U-Boot itself, hence disable it in the config again.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com --- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 7 +++++++ include/configs/socfpga_common.h | 3 --- include/configs/socfpga_stratix10_socdk.h | 8 ++++---- scripts/config_whitelist.txt | 1 - 6 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index ad83f50032..462082b67b 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -56,3 +56,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 96f806ab5f..03c43fa8b9 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -91,3 +91,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index a66a9bcbe2..6fd9b0a177 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,6 +36,13 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
+config DESIGNWARE_WATCHDOG + bool "Designware watchdog timer support" + select HW_WATCHDOG + help + Enable this to support Designware Watchdog Timer IP, present e.g. + on Altera SoCFPGA SoCs. + config WDT bool "Enable driver model for watchdog timer drivers" depends on DM diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b11fe021a7..32b9131be0 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -104,12 +104,9 @@ /* * L4 Watchdog */ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 -#endif
/* * MMC Driver diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 7b55dd14da..17f6e14790 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -160,16 +160,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * L4 Watchdog */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG +#ifndef CONFIG_SPL_BUILD +#undef CONFIG_HW_WATCHDOG +#undef CONFIG_DESIGNWARE_WATCHDOG +#endif #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) #endif #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 -#endif
/* * SPL memory layout diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b18eab1707..839eda8c0f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -320,7 +320,6 @@ CONFIG_DEFAULT_IMMR CONFIG_DEF_HWCONFIG CONFIG_DELAY_ENVIRONMENT CONFIG_DESIGNWARE_ETH -CONFIG_DESIGNWARE_WATCHDOG CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST CONFIG_DFU_ALT
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com --- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 462082b67b..cc5f49a536 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -56,4 +56,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_WDT=y CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 03c43fa8b9..def7a3eca7 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WDT=y CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG - bool "Designware watchdog timer support" - select HW_WATCHDOG - help - Enable this to support Designware Watchdog Timer IP, present e.g. - on Altera SoCFPGA SoCs. - config WDT bool "Enable driver model for watchdog timer drivers" depends on DM @@ -54,6 +47,13 @@ config WDT What exactly happens when the timer expires is up to a particular device/driver.
+config DESIGNWARE_WATCHDOG + bool "Designware watchdog timer support" + depends on WDT + help + Enable this to support Designware Watchdog Timer IP, present e.g. + on Altera SoCFPGA SoCs. + config WDT_ARMADA_37XX bool "Marvell Armada 37xx watchdog timer support" depends on WDT && ARMADA_3700 diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index c668567c66..f2b9175345 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -4,7 +4,8 @@ */
#include <common.h> -#include <watchdog.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/utils.h>
@@ -17,57 +18,95 @@ #define DW_WDT_CR_RMOD_VAL 0x00 #define DW_WDT_CRR_RESTART_VAL 0x76
+struct designware_wdt_priv { + void __iomem *base; +}; + /* * Set the watchdog time interval. * Counter is 32 bit. */ -static int designware_wdt_settimeout(unsigned int timeout) +static int designware_wdt_settimeout(struct udevice *dev, unsigned int timeout) { + struct designware_wdt_priv *priv = dev_get_priv(dev); signed int i;
/* calculate the timeout range value */ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16; - if (i > 15) - i = 15; - if (i < 0) - i = 0; + i = clamp(i, 0, 15); + + writel(i | (i << 4), priv->base + DW_WDT_TORR);
- writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR)); return 0; }
-static void designware_wdt_enable(void) +static unsigned int designware_wdt_is_enabled(struct udevice *dev) { - writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | - (0x1 << DW_WDT_CR_EN_OFFSET)), - (CONFIG_DW_WDT_BASE + DW_WDT_CR)); -} + struct designware_wdt_priv *priv = dev_get_priv(dev);
-static unsigned int designware_wdt_is_enabled(void) -{ - unsigned long val; - val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR)); - return val & 0x1; + return readl(priv->base + DW_WDT_CR) & BIT(0); }
-#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) +static int designware_wdt_reset(struct udevice *dev) { - if (designware_wdt_is_enabled()) + struct designware_wdt_priv *priv = dev_get_priv(dev); + + if (designware_wdt_is_enabled(dev)) /* restart the watchdog counter */ - writel(DW_WDT_CRR_RESTART_VAL, - (CONFIG_DW_WDT_BASE + DW_WDT_CRR)); + writel(DW_WDT_CRR_RESTART_VAL, priv->base + DW_WDT_CRR); + + return 0; }
-void hw_watchdog_init(void) +static int designware_wdt_stop(struct udevice *dev) { /* reset to disable the watchdog */ - hw_watchdog_reset(); + designware_wdt_reset(dev); + return 0; +} + +static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct designware_wdt_priv *priv = dev_get_priv(dev); + + designware_wdt_stop(dev); + /* set timer in miliseconds */ - designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); - /* enable the watchdog */ - designware_wdt_enable(); + designware_wdt_settimeout(dev, timeout); + + writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | + BIT(DW_WDT_CR_EN_OFFSET), + priv->base + DW_WDT_CR); + /* reset the watchdog */ - hw_watchdog_reset(); + designware_wdt_reset(dev); + return 0; +} + +static int designware_wdt_probe(struct udevice *dev) +{ + /* reset to disable the watchdog */ + designware_wdt_reset(dev); + return 0; } -#endif + +static const struct wdt_ops designware_wdt_ops = { + .start = designware_wdt_start, + .reset = designware_wdt_reset, + .stop = designware_wdt_stop, +}; + +static const struct udevice_id designware_wdt_ids[] = { + { .compatible = "snps,dw-wdt"}, + {} +}; + +U_BOOT_DRIVER(designware_wdt) = { + .name = "designware_wdt", + .id = UCLASS_WDT, + .of_match = designware_wdt_ids, + .priv_auto_alloc_size = sizeof(struct designware_wdt_priv), + .probe = designware_wdt_probe, + .ops = &designware_wdt_ops, + .flags = DM_FLAG_PRE_RELOC, +};
On Thu, Oct 3, 2019 at 6:56 AM Marek Vasut marex@denx.de wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 462082b67b..cc5f49a536 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -56,4 +56,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_WDT=y CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 03c43fa8b9..def7a3eca7 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WDT=y CONFIG_DESIGNWARE_WATCHDOG=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOG
CONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
helpEnable this to support Designware Watchdog Timer IP, present e.g.on Altera SoCFPGA SoCs.config WDT bool "Enable driver model for watchdog timer drivers" depends on DM @@ -54,6 +47,13 @@ config WDT What exactly happens when the timer expires is up to a particular device/driver.
+config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"depends on WDThelpEnable this to support Designware Watchdog Timer IP, present e.g.on Altera SoCFPGA SoCs.config WDT_ARMADA_37XX bool "Marvell Armada 37xx watchdog timer support" depends on WDT && ARMADA_3700 diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index c668567c66..f2b9175345 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -4,7 +4,8 @@ */
#include <common.h> -#include <watchdog.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/utils.h>
@@ -17,57 +18,95 @@ #define DW_WDT_CR_RMOD_VAL 0x00 #define DW_WDT_CRR_RESTART_VAL 0x76
+struct designware_wdt_priv {
void __iomem *base;+};
/*
- Set the watchdog time interval.
- Counter is 32 bit.
*/ -static int designware_wdt_settimeout(unsigned int timeout) +static int designware_wdt_settimeout(struct udevice *dev, unsigned int timeout) {
struct designware_wdt_priv *priv = dev_get_priv(dev); signed int i; /* calculate the timeout range value */ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
if (i > 15)i = 15;if (i < 0)i = 0;
i = clamp(i, 0, 15);writel(i | (i << 4), priv->base + DW_WDT_TORR);
writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR)); return 0;}
-static void designware_wdt_enable(void) +static unsigned int designware_wdt_is_enabled(struct udevice *dev) {
writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |(0x1 << DW_WDT_CR_EN_OFFSET)),(CONFIG_DW_WDT_BASE + DW_WDT_CR));-}
struct designware_wdt_priv *priv = dev_get_priv(dev);-static unsigned int designware_wdt_is_enabled(void) -{
unsigned long val;val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));return val & 0x1;
return readl(priv->base + DW_WDT_CR) & BIT(0);}
-#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) +static int designware_wdt_reset(struct udevice *dev) {
if (designware_wdt_is_enabled())
struct designware_wdt_priv *priv = dev_get_priv(dev);if (designware_wdt_is_enabled(dev)) /* restart the watchdog counter */
writel(DW_WDT_CRR_RESTART_VAL,(CONFIG_DW_WDT_BASE + DW_WDT_CRR));
writel(DW_WDT_CRR_RESTART_VAL, priv->base + DW_WDT_CRR);return 0;}
-void hw_watchdog_init(void) +static int designware_wdt_stop(struct udevice *dev) { /* reset to disable the watchdog */
hw_watchdog_reset();
designware_wdt_reset(dev);
Need to clear BIT(DW_WDT_CR_EN_OFFSET) in CR register to disable watchdog.
return 0;+}
+static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{
struct designware_wdt_priv *priv = dev_get_priv(dev);designware_wdt_stop(dev);/* set timer in miliseconds */
designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);/* enable the watchdog */designware_wdt_enable();
designware_wdt_settimeout(dev, timeout);writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |BIT(DW_WDT_CR_EN_OFFSET),priv->base + DW_WDT_CR);/* reset the watchdog */
hw_watchdog_reset();
designware_wdt_reset(dev);
Need move to before enable CR_EN bit if we add clear CR_EN bit in designware_wdt_reset().
return 0;+}
+static int designware_wdt_probe(struct udevice *dev) +{
Need to de-assert reset for watchdog in probe using reset framework.
/* reset to disable the watchdog */designware_wdt_reset(dev);
designware_wdt_reset() only reset watchdog counter, but doesn't disable the watchdog. Can change call to designware_wdt_stop() if _stop() add clear CR_EN bit.
return 0;} -#endif
+static const struct wdt_ops designware_wdt_ops = {
.start = designware_wdt_start,.reset = designware_wdt_reset,.stop = designware_wdt_stop,+};
+static const struct udevice_id designware_wdt_ids[] = {
{ .compatible = "snps,dw-wdt"},{}+};
+U_BOOT_DRIVER(designware_wdt) = {
.name = "designware_wdt",.id = UCLASS_WDT,.of_match = designware_wdt_ids,.priv_auto_alloc_size = sizeof(struct designware_wdt_priv),.probe = designware_wdt_probe,.ops = &designware_wdt_ops,.flags = DM_FLAG_PRE_RELOC,+};
2.23.0
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOGCONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM structures are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
[...]
-void hw_watchdog_init(void) +static int designware_wdt_stop(struct udevice *dev) { /* reset to disable the watchdog */
hw_watchdog_reset();
designware_wdt_reset(dev);Need to clear BIT(DW_WDT_CR_EN_OFFSET) in CR register to disable watchdog.
Fixed
return 0;+}
+static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{
struct designware_wdt_priv *priv = dev_get_priv(dev);designware_wdt_stop(dev);/* set timer in miliseconds */
designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);/* enable the watchdog */designware_wdt_enable();
designware_wdt_settimeout(dev, timeout);writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |BIT(DW_WDT_CR_EN_OFFSET),priv->base + DW_WDT_CR);/* reset the watchdog */
hw_watchdog_reset();
designware_wdt_reset(dev);Need move to before enable CR_EN bit if we add clear CR_EN bit in designware_wdt_reset().
I think if someone needs to clear CR_EN, they should call designware_wdt_stop(), which should clear the CR_EN.
return 0;+}
+static int designware_wdt_probe(struct udevice *dev) +{
Need to de-assert reset for watchdog in probe using reset framework.
/* reset to disable the watchdog */designware_wdt_reset(dev);designware_wdt_reset() only reset watchdog counter, but doesn't disable the watchdog. Can change call to designware_wdt_stop() if _stop() add clear CR_EN bit.
Yep, fixed, thanks.
[...]
Marek Vasut marex@denx.de schrieb am Do., 3. Okt. 2019, 09:22:
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOGCONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM structures are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I get a message that WDT is not found. I haven't sent a patch to fix that yet, since the message is the only thing that happens, works normally otherwise.
But if you're working on that, you might check side effects of that setting (which is new for this release).
Regards, Simon
[...]
-void hw_watchdog_init(void) +static int designware_wdt_stop(struct udevice *dev) { /* reset to disable the watchdog */
hw_watchdog_reset();
designware_wdt_reset(dev);Need to clear BIT(DW_WDT_CR_EN_OFFSET) in CR register to disable
watchdog.
Fixed
return 0;+}
+static int designware_wdt_start(struct udevice *dev, u64 timeout,
ulong flags)
+{
struct designware_wdt_priv *priv = dev_get_priv(dev);designware_wdt_stop(dev);/* set timer in miliseconds */
designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);/* enable the watchdog */designware_wdt_enable();
designware_wdt_settimeout(dev, timeout);writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |BIT(DW_WDT_CR_EN_OFFSET),priv->base + DW_WDT_CR);/* reset the watchdog */
hw_watchdog_reset();
designware_wdt_reset(dev);Need move to before enable CR_EN bit if we add clear CR_EN bit in designware_wdt_reset().
I think if someone needs to clear CR_EN, they should call designware_wdt_stop(), which should clear the CR_EN.
return 0;+}
+static int designware_wdt_probe(struct udevice *dev) +{
Need to de-assert reset for watchdog in probe using reset framework.
/* reset to disable the watchdog */designware_wdt_reset(dev);designware_wdt_reset() only reset watchdog counter, but doesn't disable the watchdog. Can change call to designware_wdt_stop() if _stop() add clear CR_EN bit.
Yep, fixed, thanks.
[...]
-- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 10/3/19 8:06 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 09:22:
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOGCONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM structures are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I get a message that WDT is not found. I haven't sent a patch to fix that yet, since the message is the only thing that happens, works normally otherwise.
But if you're working on that, you might check side effects of that setting (which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
[...]
Marek Vasut marex@denx.de schrieb am Do., 3. Okt. 2019, 20:09:
On 10/3/19 8:06 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 09:22:
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOGCONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM structures are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I
get
a message that WDT is not found. I haven't sent a patch to fix that yet, since the message is the only thing that happens, works normally
otherwise.
But if you're working on that, you might check side effects of that
setting
(which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
Hmm, it probably is. I'm not using a watchdog right now, so I couldn't really tell... It'll be a week or so until I'll find the time for u-boot again :-(
Regards, Simon
On 10/3/19 8:11 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 20:09:
On 10/3/19 8:06 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 09:22:
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOGCONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM structures are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I
get
a message that WDT is not found. I haven't sent a patch to fix that yet, since the message is the only thing that happens, works normally
otherwise.
But if you're working on that, you might check side effects of that
setting
(which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
Hmm, it probably is. I'm not using a watchdog right now, so I couldn't really tell... It'll be a week or so until I'll find the time for u-boot again :-(
We probably should fix that before the release though.
Marek Vasut marex@denx.de schrieb am Do., 3. Okt. 2019, 20:13:
On 10/3/19 8:11 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 20:09:
On 10/3/19 8:06 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 09:22:
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 6fd9b0a177..ec34993664 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -36,13 +36,6 @@ config ULP_WATCHDOG > help > Say Y here to enable i.MX7ULP watchdog driver. > > -config DESIGNWARE_WATCHDOG > - bool "Designware watchdog timer support" > - select HW_WATCHDOG CONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM
structures
are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I
get
a message that WDT is not found. I haven't sent a patch to fix that
yet,
since the message is the only thing that happens, works normally
otherwise.
But if you're working on that, you might check side effects of that
setting
(which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
Hmm, it probably is. I'm not using a watchdog right now, so I couldn't really tell... It'll be a week or so until I'll find the time for u-boot again :-(
We probably should fix that before the release though.
If it's a problem, then yes, we should. Let me see if I can squeeze it in tomorrow...
Regards, Simon
[...]
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I
get
a message that WDT is not found. I haven't sent a patch to fix that
yet,
since the message is the only thing that happens, works normally
otherwise.
But if you're working on that, you might check side effects of that
setting
(which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
Hmm, it probably is. I'm not using a watchdog right now, so I couldn't really tell... It'll be a week or so until I'll find the time for u-boot again :-(
We probably should fix that before the release though.
If it's a problem, then yes, we should. Let me see if I can squeeze it in tomorrow...
Thanks
I almost suspect it's one of my WDT DM conversion patches which caused this.
Am 03.10.2019 um 21:12 schrieb Marek Vasut:
[...]
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I
get
a message that WDT is not found. I haven't sent a patch to fix that
yet,
since the message is the only thing that happens, works normally
otherwise.
But if you're working on that, you might check side effects of that
setting
(which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
Hmm, it probably is. I'm not using a watchdog right now, so I couldn't really tell... It'll be a week or so until I'll find the time for u-boot again :-(
We probably should fix that before the release though.
If it's a problem, then yes, we should. Let me see if I can squeeze it in tomorrow...
Thanks
I almost suspect it's one of my WDT DM conversion patches which caused this.
Hehe, a fast blame on github shows me you're right :-)
The problem is that SPL_WATCHDOG_SUPPORT (which is selected by ARCH_SOCFPGA) implies SPL_WDT if !HW_WATCHDOG. Now for my board, HW_WATCHDOG is obviously disabled. I'd have to check the mainline gen5 boards though...
I'll try to check socfpga_socrates tomorrow and check the other boards by comparing the defconfigs.
Regards, Simon
On 10/3/19 9:18 PM, Simon Goldschmidt wrote:
Am 03.10.2019 um 21:12 schrieb Marek Vasut:
[...]
> Are you aware that DM WDT is enabled in SPL by default for gen5 > now? I get > a message that WDT is not found. I haven't sent a patch to fix that
yet,
> since the message is the only thing that happens, works normally otherwise. > > But if you're working on that, you might check side effects of that setting > (which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
Hmm, it probably is. I'm not using a watchdog right now, so I couldn't really tell... It'll be a week or so until I'll find the time for u-boot again :-(
We probably should fix that before the release though.
If it's a problem, then yes, we should. Let me see if I can squeeze it in tomorrow...
Thanks
I almost suspect it's one of my WDT DM conversion patches which caused this.
Hehe, a fast blame on github shows me you're right :-)
The problem is that SPL_WATCHDOG_SUPPORT (which is selected by ARCH_SOCFPGA) implies SPL_WDT if !HW_WATCHDOG. Now for my board, HW_WATCHDOG is obviously disabled. I'd have to check the mainline gen5 boards though...
I'll try to check socfpga_socrates tomorrow and check the other boards by comparing the defconfigs.
Thanks
On 10/3/19 8:06 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 09:22:
On 10/3/19 3:57 AM, Ley Foon Tan wrote:
[...]
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6fd9b0a177..ec34993664 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -36,13 +36,6 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver.
-config DESIGNWARE_WATCHDOG
bool "Designware watchdog timer support"select HW_WATCHDOGCONFIG_HW_WATCHDOG is disabled now. Few areas of code in arm/mach-socfpga/ still using this CONFIG and call to hw_watchdog_init(). They need to remove too. Do we need call to uclass_get_device(UCLASS_WDT, 0, &dev) in SPL to probe watchdog and call to wdt_start() to start watchdog? Can't find place that start watchdog.
You're right, and the WDT is enabled early on, before the DM structures are available.
I wonder whether we should do what we did on iMX -- have a non-DM WDT driver for SPL and DM-one for U-Boot proper.
Are you aware that DM WDT is enabled in SPL by default for gen5 now? I get a message that WDT is not found. I haven't sent a patch to fix that yet, since the message is the only thing that happens, works normally otherwise.
But if you're working on that, you might check side effects of that setting (which is new for this release).
That doesn't sound right, the SoCFPGA core code uses HW_WATCHDOG in some places as Ley pointed out, so if DM WDT is enabled in SPL, that code in HW_WATCHDOG ifdefs isn't used. And I think that will trigger some weird problems. So in the end, enabling DM watchdog in SoCFPGA SPL right now is a bug ?
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut marex@denx.de wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need one which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
On 10/3/19 1:40 PM, Marek Vasut wrote:
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need one which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
Oh, and the clock/reset stuff should be optional, since at least DM clock are not present on socfpga gen5 yet.
Marek Vasut marex@denx.de schrieb am Do., 3. Okt. 2019, 14:19:
On 10/3/19 1:40 PM, Marek Vasut wrote:
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need one which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
Oh, and the clock/reset stuff should be optional, since at least DM clock are not present on socfpga gen5 yet.
I'm working on that. Sadly, I haven't fou,d the time to finish it up since mid August, but I'm planning to do it in the upcoming merge window.
Regards, Simon
On 10/3/19 8:03 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 14:19:
On 10/3/19 1:40 PM, Marek Vasut wrote:
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97 +++++++++++++++++++-------- 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need one which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
Oh, and the clock/reset stuff should be optional, since at least DM clock are not present on socfpga gen5 yet.
I'm working on that. Sadly, I haven't fou,d the time to finish it up since mid August, but I'm planning to do it in the upcoming merge window.
Great!
Note that if you build a board without DM watchdog today, it complains about removal until 2019.10, so that's one issue here. The other is that I don't think we can do DM watchdog in SPL on Gen5, can we ?
Marek Vasut marex@denx.de schrieb am Do., 3. Okt. 2019, 20:06:
On 10/3/19 8:03 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 14:19:
On 10/3/19 1:40 PM, Marek Vasut wrote:
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote:
Convert the designware watchdog timer driver to DM and add DT probing support. Perform minor coding style clean up, like drop superfluous braces. These ought to be no functional change.
configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + drivers/watchdog/Kconfig | 14 ++-- drivers/watchdog/designware_wdt.c | 97
+++++++++++++++++++--------
4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need
one
which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
Oh, and the clock/reset stuff should be optional, since at least DM clock are not present on socfpga gen5 yet.
I'm working on that. Sadly, I haven't fou,d the time to finish it up
since
mid August, but I'm planning to do it in the upcoming merge window.
Great!
Note that if you build a board without DM watchdog today, it complains about removal until 2019.10, so that's one issue here. The other is that I don't think we can do DM watchdog in SPL on Gen5, can we ?
If I'm not using watchdog at all, will it complain???
I think we should be able to get that running. We'll need an idea to shrink DM SPL anyway... :-)
Regards, Simon
On 10/3/19 8:08 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 20:06:
On 10/3/19 8:03 PM, Simon Goldschmidt wrote:
Marek Vasut schrieb am Do., 3. Okt. 2019, 14:19:
On 10/3/19 1:40 PM, Marek Vasut wrote:
On 10/3/19 9:55 AM, Jagan Teki wrote:
On Thu, Oct 3, 2019 at 4:26 AM Marek Vasut wrote: > > Convert the designware watchdog timer driver to DM and add DT probing > support. Perform minor coding style clean up, like drop superfluous > braces. These ought to be no functional change. > --- > configs/socfpga_stratix10_defconfig | 1 + > configs/socfpga_vining_fpga_defconfig | 1 + > drivers/watchdog/Kconfig | 14 ++-- > drivers/watchdog/designware_wdt.c | 97
+++++++++++++++++++--------
> 4 files changed, 77 insertions(+), 36 deletions(-)
fyi: this is already in ML [1] and yet to pick for next MW. let me know if you have any questions?
It's a pity I wasn't CCed on that patch.
That patch won't work for SoCFPGA, see my reply to Ley. We will need
one
which can do non-DM WDT in SPL, so I will be sending a V2 of this one which retains the common code and still supports HW_WATCHDOG in SPL and DM-WDT in U-Boot proper.
Oh, and the clock/reset stuff should be optional, since at least DM clock are not present on socfpga gen5 yet.
I'm working on that. Sadly, I haven't fou,d the time to finish it up
since
mid August, but I'm planning to do it in the upcoming merge window.
Great!
Note that if you build a board without DM watchdog today, it complains about removal until 2019.10, so that's one issue here. The other is that I don't think we can do DM watchdog in SPL on Gen5, can we ?
If I'm not using watchdog at all, will it complain???
It only complains about non-DM watchdog in U-Boot proper.
I think we should be able to get that running. We'll need an idea to shrink DM SPL anyway... :-)
Using DM watchdog in SPL won't help in that direction.
There are a few boards which enable WDT early in SPL that depend on HW_WATCHDOG to enable it real early.
participants (4)
-
Jagan Teki -
Ley Foon Tan -
Marek Vasut -
Simon Goldschmidt