Remove not needed code in the spl board code.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mm/spl.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 64f0780f6e65..d54145ef995c 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -12,8 +12,6 @@ #include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> -#include <dm/device.h> -#include <dm/uclass.h> #include <hang.h> #include <init.h> #include <log.h> @@ -39,7 +37,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) } }

-void spl_dram_init(void) +static void spl_dram_init(void) { ddr_init(&dram_timing); } @@ -54,15 +52,10 @@ void spl_board_init(void) puts("Normal Boot\n"); }

-#ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - return 0; } -#endif

#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) @@ -91,7 +84,6 @@ int board_early_init_f(void)

void board_init_f(ulong dummy) { - struct udevice *dev; int ret;

arch_cpu_init(); @@ -100,8 +92,6 @@ void board_init_f(ulong dummy)

board_early_init_f();

- timer_init(); - preloader_console_init();

/* Clear the BSS. */ @@ -113,13 +103,6 @@ void board_init_f(ulong dummy) hang(); }

- ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", &dev); - if (ret < 0) { - printf("Failed to find clock node. Check device tree\n"); - hang(); - } - enable_tzc380();

/* DDR initialization */

Remove ip address and server ip from board config as they should not be added hardcoded.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- include/configs/phycore_imx8mm.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 8d1fd153f62f..aa879122e844 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -37,10 +37,7 @@ "console=ttymxc2,115200\0" \ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ipaddr=192.168.3.11\0" \ - "serverip=192.168.3.10\0" \ - "netmask=255.225.255.0\0" \ - "ip_dyn=no\0" \ + "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=2\0" \

Remove obsolet defines in phycore_imx8mm.h.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- include/configs/phycore_imx8mm.h | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index aa879122e844..b13787bc2471 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -98,23 +98,14 @@ #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR

/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) + /* USDHC */ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1

-/* ENET1 */ -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC -#define IMX_FEC_BASE 0x30BE0000 - #endif /* __PHYCORE_IMX8MM_H */

Do not use size macros for addesses. So convert PHYS_SDRAM to address. No functional change.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- include/configs/phycore_imx8mm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index b13787bc2471..e74f2b27954f 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -91,7 +91,7 @@

#define CONFIG_SYS_SDRAM_BASE 0x40000000

-#define PHYS_SDRAM SZ_1G +#define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */

/* UART */

Add missing pinctrl entry in spl.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/phycore-imx8mm-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi index 91515b8df9a0..7c2dfb4a273c 100644 --- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi +++ b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi @@ -30,6 +30,10 @@ u-boot,dm-spl; };

+&pinctrl_wdog { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; };

Fix misspelled property "stdout-path".

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/phycore-imx8mm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts index c46d3c72ced9..a4332619e5f7 100644 --- a/arch/arm/dts/phycore-imx8mm.dts +++ b/arch/arm/dts/phycore-imx8mm.dts @@ -14,7 +14,7 @@ compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";

chosen { - stdout-patch = &uart3; + stdout-path = &uart3; };

reg_usdhc2_vmmc: regulator-usdhc2 {

Adds SPI-NOR flash support to erase, read and write in bootloader.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/phycore-imx8mm.dts | 28 ++++++++++++++++++++++++++++ configs/phycore-imx8mm_defconfig | 19 +++++++++++++++++++ 2 files changed, 47 insertions(+)

diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts index a4332619e5f7..e57dfd368d6b 100644 --- a/arch/arm/dts/phycore-imx8mm.dts +++ b/arch/arm/dts/phycore-imx8mm.dts @@ -54,6 +54,23 @@ }; };

+/* SPI nor flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: norflash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + /* i2c eeprom */ &i2c1 { clock-frequency = <400000>; @@ -140,6 +157,17 @@ >; };

+ pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 91360b7d1a5c..6cb2d368552e 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " @@ -44,6 +45,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -78,6 +80,20 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=3 +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_TI_DP83867=y CONFIG_DM_ETH=y @@ -91,6 +107,9 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y

Enable clk command to dump clock tree.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- configs/phycore-imx8mm_defconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 6cb2d368552e..1897cb398ffd 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_SIZE=4096 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y

Use binman for image creation.

Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/phycore-imx8mm-u-boot.dtsi | 122 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + board/phytec/phycore_imx8mm/Kconfig | 2 +- .../phytec/phycore_imx8mm/imximage-8mm-sd.cfg | 9 ++ configs/phycore-imx8mm_defconfig | 2 +- 5 files changed, 134 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg

diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi index 7c2dfb4a273c..f842e02c771b 100644 --- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi +++ b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi @@ -7,6 +7,10 @@ #include "imx8mm-u-boot.dtsi"

/ { + binman: binman { + multiple-images; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -69,3 +73,121 @@ &wdog1 { u-boot,dm-spl; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + }; + + uboot: blob-ext@2 { + filename = "u-boot.itb"; + offset = <0x57c00>; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index ccaf106be5d8..269d9774b558 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -121,6 +121,7 @@ config TARGET_IMX8MN_BEACON

config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" + select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig index 9868e984875e..25e4bf2f8367 100644 --- a/board/phytec/phycore_imx8mm/Kconfig +++ b/board/phytec/phycore_imx8mm/Kconfig @@ -10,6 +10,6 @@ config SYS_CONFIG_NAME default "phycore_imx8mm"

config IMX_CONFIG - default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"

endif diff --git a/board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg b/board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg new file mode 100644 index 000000000000..ea74fb7e590f --- /dev/null +++ b/board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Phytec Messtechnik GmbH + */ + +#define __ASSEMBLY__ + +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 1897cb398ffd..c22139874768 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y