[U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0), + MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0), - MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0), + MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
The mx6sx has two ENET controllers, some board like mx6sxsabreauto uses the ENET2 for ethernet. So add ENET2 support to soc level, including: ENET2 clock enable and MAC address fuse for ENET2.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/cpu/armv7/mx6/clock.c | 9 ++++++++- arch/arm/cpu/armv7/mx6/soc.c | 25 ++++++++++++++++++++++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 7 +++++++ 3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 055f44e..fd57f22 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -498,7 +498,11 @@ int enable_fec_anatop_clock(enum enet_freq freq)
reg = readl(&anatop->pll_enet); reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; - reg |= freq; + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); +#ifdef CONFIG_MX6SX + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); +#endif
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -514,6 +518,9 @@ int enable_fec_anatop_clock(enum enet_freq freq)
/* Enable FEC clock */ reg |= BM_ANADIG_PLL_ENET_ENABLE; +#ifdef CONFIG_MX6SX + reg |= BM_ANADIG_PLL_ENET2_ENABLE; +#endif reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5f5f497..4994eab 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -337,6 +337,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs;
+#ifdef CONFIG_MX6SX + if (0 == dev_id) { + u32 value = readl(&fuse->mac_addr_high); + mac[0] = (value >> 8); + mac[1] = value ; + + value = readl(&fuse->mac_addr_low); + mac[2] = value >> 24 ; + mac[3] = value >> 16 ; + mac[4] = value >> 8 ; + mac[5] = value ; + } else { + u32 value = readl(&fuse->mac_addr2); + mac[0] = value >> 24 ; + mac[1] = value >> 16 ; + mac[2] = value >> 8 ; + mac[3] = value ; + + value = readl(&fuse->mac_addr_high); + mac[4] = value >> 24 ; + mac[5] = value >> 16 ; + } +#else u32 value = readl(&fuse->mac_addr_high); mac[0] = (value >> 8); mac[1] = value ; @@ -346,7 +369,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[3] = value >> 16 ; mac[4] = value >> 8 ; mac[5] = value ; - +#endif } #endif
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 39f3c07..eec03cf 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1012,6 +1012,13 @@ struct mxc_ccm_reg { #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +#ifdef CONFIG_MX6SX +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 + +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) +#endif
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
The mx6sx has two ENET controllers, some board like mx6sxsabreauto uses the ENET2 for ethernet. So add ENET2 support to soc level, including: ENET2 clock enable and MAC address fuse for ENET2.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/cpu/armv7/mx6/clock.c | 9 ++++++++- arch/arm/cpu/armv7/mx6/soc.c | 25 ++++++++++++++++++++++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 7 +++++++ 3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 055f44e..fd57f22 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -498,7 +498,11 @@ int enable_fec_anatop_clock(enum enet_freq freq)
reg = readl(&anatop->pll_enet); reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= freq;
- reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+#ifdef CONFIG_MX6SX
- reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
- reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+#endif
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -514,6 +518,9 @@ int enable_fec_anatop_clock(enum enet_freq freq)
/* Enable FEC clock */ reg |= BM_ANADIG_PLL_ENET_ENABLE; +#ifdef CONFIG_MX6SX
- reg |= BM_ANADIG_PLL_ENET2_ENABLE;
+#endif reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5f5f497..4994eab 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -337,6 +337,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs;
+#ifdef CONFIG_MX6SX
- if (0 == dev_id) {
u32 value = readl(&fuse->mac_addr_high);mac[0] = (value >> 8);mac[1] = value ;value = readl(&fuse->mac_addr_low);mac[2] = value >> 24 ;
^---
Checkpatch complains about extra spaces.
mac[3] = value >> 16 ;mac[4] = value >> 8 ;mac[5] = value ;- } else {
u32 value = readl(&fuse->mac_addr2);mac[0] = value >> 24 ;mac[1] = value >> 16 ;mac[2] = value >> 8 ;mac[3] = value ;value = readl(&fuse->mac_addr_high);mac[4] = value >> 24 ;mac[5] = value >> 16 ;
Is it desired that the layout is different between the two mac addresses ? As far as I know, MAC_ADDR in fuses is reserved to customers, and it makes sense they have the same layout. Is there some reason (that I do not know, obviously) to have them different ?
- }
+#else u32 value = readl(&fuse->mac_addr_high); mac[0] = (value >> 8); mac[1] = value ; @@ -346,7 +369,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[3] = value >> 16 ; mac[4] = value >> 8 ; mac[5] = value ;
+#endif } #endif
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 39f3c07..eec03cf 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1012,6 +1012,13 @@ struct mxc_ccm_reg { #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +#ifdef CONFIG_MX6SX +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
- (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+#endif
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
Best regards, Stefano Babic
Hi Stefano,
On 2/10/2015 6:22 PM, Stefano Babic wrote:
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
The mx6sx has two ENET controllers, some board like mx6sxsabreauto uses the ENET2 for ethernet. So add ENET2 support to soc level, including: ENET2 clock enable and MAC address fuse for ENET2.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/cpu/armv7/mx6/clock.c | 9 ++++++++- arch/arm/cpu/armv7/mx6/soc.c | 25 ++++++++++++++++++++++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 7 +++++++ 3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 055f44e..fd57f22 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -498,7 +498,11 @@ int enable_fec_anatop_clock(enum enet_freq freq)
reg = readl(&anatop->pll_enet); reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= freq;
- reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+#ifdef CONFIG_MX6SX
- reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
- reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+#endif
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -514,6 +518,9 @@ int enable_fec_anatop_clock(enum enet_freq freq)
/* Enable FEC clock */ reg |= BM_ANADIG_PLL_ENET_ENABLE; +#ifdef CONFIG_MX6SX
- reg |= BM_ANADIG_PLL_ENET2_ENABLE;
+#endif reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5f5f497..4994eab 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -337,6 +337,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs;
+#ifdef CONFIG_MX6SX
- if (0 == dev_id) {
u32 value = readl(&fuse->mac_addr_high);mac[0] = (value >> 8);mac[1] = value ;value = readl(&fuse->mac_addr_low);mac[2] = value >> 24 ;^---Checkpatch complains about extra spaces.
I will fix this problem.
mac[3] = value >> 16 ;mac[4] = value >> 8 ;mac[5] = value ;- } else {
u32 value = readl(&fuse->mac_addr2);mac[0] = value >> 24 ;mac[1] = value >> 16 ;mac[2] = value >> 8 ;mac[3] = value ;value = readl(&fuse->mac_addr_high);mac[4] = value >> 24 ;mac[5] = value >> 16 ;Is it desired that the layout is different between the two mac addresses ? As far as I know, MAC_ADDR in fuses is reserved to customers, and it makes sense they have the same layout. Is there some reason (that I do not know, obviously) to have them different ?
I think the reason is to save one fuse. If the enet2 has same mac fuse layout as enet1, obviously we have to use one more fuse than current layout. Additional, the layout is determined by IC, software just follows it.
- }
+#else u32 value = readl(&fuse->mac_addr_high); mac[0] = (value >> 8); mac[1] = value ; @@ -346,7 +369,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[3] = value >> 16 ; mac[4] = value >> 8 ; mac[5] = value ;
+#endif } #endif
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 39f3c07..eec03cf 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1012,6 +1012,13 @@ struct mxc_ccm_reg { #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +#ifdef CONFIG_MX6SX +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
- (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+#endif
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
Best regards, Stefano Babic
Hi Ye,
On 11/02/2015 03:42, Li Ye-B37916 wrote:
Checkpatch complains about extra spaces.
I will fix this problem.
mac[3] = value >> 16 ;mac[4] = value >> 8 ;mac[5] = value ;- } else {
u32 value = readl(&fuse->mac_addr2);mac[0] = value >> 24 ;mac[1] = value >> 16 ;mac[2] = value >> 8 ;mac[3] = value ;value = readl(&fuse->mac_addr_high);mac[4] = value >> 24 ;mac[5] = value >> 16 ;Is it desired that the layout is different between the two mac addresses ? As far as I know, MAC_ADDR in fuses is reserved to customers, and it makes sense they have the same layout. Is there some reason (that I do not know, obviously) to have them different ?
I think the reason is to save one fuse. If the enet2 has same mac fuse layout as enet1, obviously we have to use one more fuse than current layout.
Additional, the layout is determined by IC, software just follows it.
Of course, but I have not the fuse map for SX. Does it mean that SX has 3 fuses defined for customer's use ?
Reason is also because you are defined a rule how to use it. In many systems with more as one ethernet, the rule is defined by the customer, for example using consecutives MAC addresses starting from the first one stored in SOC or on another storage. In this case, we have a mix between independent MAC addresses (it will be if MAC addresses are completely stored) and a dependency (MSB is in common). I find better if this hidden rule is better explained, adding comments for that.
Best regards, Stefano Babic
On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fd57f22..ce7f0f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#if defined(CONFIG_MX6SX) + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr, @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg) cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); +#endif setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
Hi Ye,
On 12/01/2015 09:46, Ye.Li wrote:
On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fd57f22..ce7f0f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#if defined(CONFIG_MX6SX)
- clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
- clrsetbits_le32(&imx_ccm->cs2cdr,
MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,cfg);- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#els
If I have well understood, this code is protected by CONFIG_NAND_MXS, and that conflicts with what you are willing to do (setting clocks for QSPI). I suggest to split setup_gpmi_io_clk() function, that at the moment is ony for NAND, having something like:
void setup_gpmi_io_clk() { #ifdef CONFIG_NAND_MXS
...setup nand #endif
...setup qspi
}
Best regards, Stefano Babic
Hi Stefano,
On 2/10/2015 6:26 PM, Stefano Babic wrote:
Hi Ye,
On 12/01/2015 09:46, Ye.Li wrote:
On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fd57f22..ce7f0f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#if defined(CONFIG_MX6SX)
- clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
- clrsetbits_le32(&imx_ccm->cs2cdr,
MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,cfg);- setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#els
If I have well understood, this code is protected by CONFIG_NAND_MXS, and that conflicts with what you are willing to do (setting clocks for QSPI). I suggest to split setup_gpmi_io_clk() function, that at the moment is ony for NAND, having something like:
void setup_gpmi_io_clk() { #ifdef CONFIG_NAND_MXS
...setup nand #endif
...setup qspi
}
Best regards, Stefano Babic
I feel you misunderstand the patch. On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout. The patch is used to fix the gap.
Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work, there is no conflict.
Best regards, Ye Li
Hi Ye.Li,
On 11/02/2015 04:14, Li Ye-B37916 wrote:
I feel you misunderstand the patch.
Thanks for clarifications.
On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout. The patch is used to fix the gap.
Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work, there is no conflict.
Ok, understood - then it is fine with me.
Best regards, Stefano Babic
Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/Kconfig | 5 + board/freescale/mx6sxsabreauto/Kconfig | 15 + board/freescale/mx6sxsabreauto/MAINTAINERS | 6 + board/freescale/mx6sxsabreauto/Makefile | 6 + board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 498 +++++++++++++++++++++++ configs/mx6sxsabreauto_defconfig | 3 + include/configs/mx6sxsabreauto.h | 275 +++++++++++++ 8 files changed, 944 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx6sxsabreauto/Kconfig create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS create mode 100644 board/freescale/mx6sxsabreauto/Makefile create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c create mode 100644 configs/mx6sxsabreauto_defconfig create mode 100644 include/configs/mx6sxsabreauto.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03..9c54914 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -638,6 +638,10 @@ config TARGET_MX6SXSABRESD bool "Support mx6sxsabresd" select CPU_V7
+config TARGET_MX6SXSABREAUTO + bool "Support mx6sxsabreauto" + select CPU_V7 + config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7 @@ -916,6 +920,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig new file mode 100644 index 0000000..b0f5167 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABREAUTO + +config SYS_BOARD + default "mx6sxsabreauto" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6sxsabreauto" + +endif diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS new file mode 100644 index 0000000..dd3ae41 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABREAUTO BOARD +M: Ye Li Ye.Li@freescale.com +S: Maintained +F: board/freescale/mx6sxsabreauto/ +F: include/configs/mx6sxsabreauto.h +F: configs/mx6sxsabreauto_defconfig diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile new file mode 100644 index 0000000..f0cd1ce --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sxsabreauto.o diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg new file mode 100644 index 0000000..529e555 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* Clock */ +DATA 4 0x020e032c 0x00000030 + +/* Address */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 + +/* Control */ +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 + +/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 + +/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003 + +/* Write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A + +DATA 4 0x021b08c0 0x2492244A + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000 + +/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c new file mode 100644 index 0000000..a406a1d --- /dev/null +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Author: Ye Li Ye.Li@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <usb.h> +#include <usb/ehci-fsl.h> +#include <pca953x.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define I2C_PMIC 1 + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \ + ((chip << 5) + pin) + +/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \ + (gpio_nr >> 5) + +/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \ + (gpio_nr & 0x1f) + +#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4) +#define STEER_ENET PORTEXP_IO_NR(0x32, 2) + +static int port_exp_direction_output(unsigned gpio, int value) +{ + int ret; + + i2c_set_bus_num(2); + ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio)); + if (ret) + return ret; + + ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (value << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); + + return enable_fec_anatop_clock(ENET_125MHZ); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); + setup_fec(); + + ret = fecmxc_initialize_multi(bis, 1, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", 1, __func__); + + return ret; +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; + +/* I2C3 for IO Expander */ +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC, + .gp = IMX_GPIO_NR(2, 14), + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC, + .gp = IMX_GPIO_NR(2, 19), + }, +}; + +int power_init_board(void) +{ + struct pmic *p; + + p = pfuze_common_init(I2C_PMIC); + if (!p) + return -ENODEV; + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10) +#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC3 + * mmc1 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + + /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/ + gpio_direction_output(USDHC3_RST_GPIO, 0); + udelay(1000); /* need 1ms at least */ + gpio_direction_output(USDHC3_RST_GPIO, 1); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#ifdef CONFIG_FSL_QSPI + +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); +#endif + + /* Reset CPU_PER_RST_B signal for enet phy and PCIE */ + port_exp_direction_output(CPU_PER_RST_B, 0); + udelay(500); + port_exp_direction_output(CPU_PER_RST_B, 1); + + /* Set steering signal to L for selecting B0 */ + port_exp_direction_output(STEER_ENET, 0); + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SX SABRE AUTO\n"); + + return 0; +} diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig new file mode 100644 index 0000000..ca5ff27 --- /dev/null +++ b/configs/mx6sxsabreauto_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX" +CONFIG_ARM=y +CONFIG_TARGET_MX6SXSABREAUTO=y diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h new file mode 100644 index 0000000..082abaf --- /dev/null +++ b/include/configs/mx6sxsabreauto.h @@ -0,0 +1,275 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX Sabreauto board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sx-sabreauto.dtb\0" \ + "fdt_addr=0x88000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII + +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL + +#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif + +#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ +#endif + +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + +#endif /* __CONFIG_H */
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/Kconfig | 5 + board/freescale/mx6sxsabreauto/Kconfig | 15 + board/freescale/mx6sxsabreauto/MAINTAINERS | 6 + board/freescale/mx6sxsabreauto/Makefile | 6 + board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 498 +++++++++++++++++++++++ configs/mx6sxsabreauto_defconfig | 3 + include/configs/mx6sxsabreauto.h | 275 +++++++++++++ 8 files changed, 944 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx6sxsabreauto/Kconfig create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS create mode 100644 board/freescale/mx6sxsabreauto/Makefile create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c create mode 100644 configs/mx6sxsabreauto_defconfig create mode 100644 include/configs/mx6sxsabreauto.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03..9c54914 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -638,6 +638,10 @@ config TARGET_MX6SXSABRESD bool "Support mx6sxsabresd" select CPU_V7
+config TARGET_MX6SXSABREAUTO
- bool "Support mx6sxsabreauto"
- select CPU_V7
config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7 @@ -916,6 +920,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig new file mode 100644 index 0000000..b0f5167 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABREAUTO
+config SYS_BOARD
- default "mx6sxsabreauto"
+config SYS_VENDOR
- default "freescale"
+config SYS_SOC
- default "mx6"
+config SYS_CONFIG_NAME
- default "mx6sxsabreauto"
+endif diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS new file mode 100644 index 0000000..dd3ae41 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABREAUTO BOARD +M: Ye Li Ye.Li@freescale.com +S: Maintained +F: board/freescale/mx6sxsabreauto/ +F: include/configs/mx6sxsabreauto.h +F: configs/mx6sxsabreauto_defconfig diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile new file mode 100644 index 0000000..f0cd1ce --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := mx6sxsabreauto.o diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg new file mode 100644 index 0000000..529e555 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -0,0 +1,136 @@ +/*
- Copyright (C) 2014 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#define __ASSEMBLY__ +#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+/*
- Boot Device : one of
- spi/sd/nand/onenand, qspi/nor
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff
I will not block the patch for this: you are the maintainer and you can test and check if this ok.
I would only to point to the discussion with Peng regarding the same issue for the mx6sxsabresd. Peng confirmed that he would send a following patch for enabling only the clocks are needed. Mybe you can synchronize wit him.
+/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000
+/* Clock */ +DATA 4 0x020e032c 0x00000030
+/* Address */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030
+/* Control */ +DATA 4 0x020e0340 0x00000030
+DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030
+/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030
+/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030
+/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003
+/* Write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046
+/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C
+/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A
+DATA 4 0x021b08c0 0x2492244A
+/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333
+/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000
+/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040
+/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000
ok, I admit that diggering into the DCD table requires too much effort. What about to move to SPL code ? I have expected that new i.MX6 boards will be moved to support SPL, but it looks like that most patches still stick with DCD tables. A couple of Freescale's boards were already ported to SPL and merged. Have you considered to use SPL ? If yes, which are the reason to not support it ?
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c new file mode 100644 index 0000000..a406a1d --- /dev/null +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -0,0 +1,498 @@ +/*
- Copyright (C) 2014 Freescale Semiconductor, Inc.
- Author: Ye Li Ye.Li@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <usb.h> +#include <usb/ehci-fsl.h> +#include <pca953x.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
+#define I2C_PMIC 1
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
+/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
+/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
+#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4) +#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
+static int port_exp_direction_output(unsigned gpio, int value) +{
- int ret;
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
Is it required to call every time i2c_probe() ? Should be called only once ?
- if (ret)
return ret;- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));- if (ret)
return ret;- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),(value << PORTEXP_IO_TO_PIN(gpio)));- if (ret)
return ret;- return 0;
+}
+int dram_init(void) +{
- gd->ram_size = PHYS_SDRAM_SIZE;
- return 0;
+}
+static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RST_B, used for power reset cycle */
- MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+static void setup_iomux_uart(void) +{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+static int setup_fec(void) +{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
- return enable_fec_anatop_clock(ENET_125MHZ);
+}
+int board_eth_init(bd_t *bis) +{
- int ret;
- imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
- setup_fec();
- ret = fecmxc_initialize_multi(bis, 1,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);- if (ret)
printf("FEC%d MXC: %s:failed\n", 1, __func__);- return ret;
+}
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,.gp = IMX_GPIO_NR(1, 2),- },
- .sda = {
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,.gp = IMX_GPIO_NR(1, 3),- },
+};
+/* I2C3 for IO Expander */ +struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,.gp = IMX_GPIO_NR(2, 14),- },
- .sda = {
.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,.gp = IMX_GPIO_NR(2, 19),- },
+};
+int power_init_board(void) +{
- struct pmic *p;
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
return -ENODEV;- return 0;
+}
+#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9)
+static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OGT1 */
- MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+static void setup_usb(void) +{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));+}
+int board_usb_phy_mode(int port) +{
- if (port == 1)
return USB_INIT_HOST;- else
return usb_phy_mode(port);+}
+int board_ehci_hcd_init(int port) +{
- u32 *usbnc_usb_ctrl;
- if (port > 1)
return -EINVAL;- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
- return 0;
+} +#endif
+int board_phy_config(struct phy_device *phydev) +{
- /*
* Enable 1.8V(SEL_1P5_1P8_POS_REG) on* Phy control debug reg 0*/- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
- /* rgmii tx clock delay enable */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
- if (phydev->drv->config)
phydev->drv->config(phydev);- return 0;
+}
+int board_early_init_f(void) +{
- setup_iomux_uart();
+#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
Why USB here and not in board_init ? It is not a problem because you set only the pinmux, but if setup_usb() will be changed in future, it is easy to forget that it is called before relocation.
+#endif
- return 0;
+}
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
+};
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10) +#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
+int board_mmc_getcd(struct mmc *mmc) +{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
- switch (cfg->esdhc_base) {
- case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);break;- case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);break;- }
- return ret;
+}
+int board_mmc_init(bd_t *bis) +{
- int i, ret;
- /*
* According to the board_mmc_init() the following map is done:* (U-boot device node) (Physical Port)* mmc0 USDHC3* mmc1 USDHC4*/- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {case 0:imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));gpio_direction_input(USDHC3_CD_GPIO);/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/gpio_direction_output(USDHC3_RST_GPIO, 0);udelay(1000); /* need 1ms at least */gpio_direction_output(USDHC3_RST_GPIO, 1);usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);break;case 1:imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));gpio_direction_input(USDHC4_CD_GPIO);usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);break;default:printf("Warning: you configured more USDHC controllers""(%d) than supported by the board\n", i + 1);return -EINVAL;}ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);if (ret) {printf("Warning: failed to initialize mmc dev %d\n", i);
There was a clean-up patchset by Fabio - fsl_esdhc_initialize() prints already a warning, you do not need a second one here.
return ret;}- }
- return 0;
+}
+#ifdef CONFIG_FSL_QSPI
+#define QSPI_PAD_CTRL1 \
- (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)+static iomux_v3_cfg_t const quadspi_pads[] = {
- MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+int board_qspi_init(void) +{
- /* Set the iomux */
- imx_iomux_v3_setup_multiple_pads(quadspi_pads,
ARRAY_SIZE(quadspi_pads));- /* Set the clock */
- enable_qspi_clk(0);
- return 0;
+} +#endif
+#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = {
- MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+static void setup_gpmi_nand(void) +{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
- setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+} +#endif
+int board_init(void) +{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#endif
- /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
- port_exp_direction_output(CPU_PER_RST_B, 0);
- udelay(500);
- port_exp_direction_output(CPU_PER_RST_B, 1);
- /* Set steering signal to L for selecting B0 */
- port_exp_direction_output(STEER_ENET, 0);
+#ifdef CONFIG_FSL_QSPI
- board_qspi_init();
+#endif
+#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
+#endif
- return 0;
+}
+int board_late_init(void) +{
- return 0;
+}
Drop it if you do not use it.
+int checkboard(void) +{
- puts("Board: MX6SX SABRE AUTO\n");
- return 0;
+} diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig new file mode 100644 index 0000000..ca5ff27 --- /dev/null +++ b/configs/mx6sxsabreauto_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX" +CONFIG_ARM=y +CONFIG_TARGET_MX6SXSABREAUTO=y diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h new file mode 100644 index 0000000..082abaf --- /dev/null +++ b/include/configs/mx6sxsabreauto.h @@ -0,0 +1,275 @@ +/*
- Copyright 2014 Freescale Semiconductor, Inc.
- Configuration settings for the Freescale i.MX6SX Sabreauto board.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h"
+#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200
+/* Command definition */ +#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=imx6sx-sabreauto.dtb\0" \
- "fdt_addr=0x88000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \- "loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \- "bootscript=echo Running bootscript from mmc ...; " \
"source\0" \- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if run loadfdt; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootz; " \"fi;\0" \- "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${image}; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootz; " \"fi;\0"+#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \"else run netboot; fi"+/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024
+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K
+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_2G
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION
+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000
+/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS
+/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8
+/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII
+#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS
+#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif
+#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL
+#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif
+/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif
+#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ
+#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ +#endif
+#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#endif /* __CONFIG_H */
Best regards, Stefano Babic
Hi,
On 2/10/2015 6:51 PM, Stefano Babic wrote:
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/Kconfig | 5 + board/freescale/mx6sxsabreauto/Kconfig | 15 + board/freescale/mx6sxsabreauto/MAINTAINERS | 6 + board/freescale/mx6sxsabreauto/Makefile | 6 + board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 498 +++++++++++++++++++++++ configs/mx6sxsabreauto_defconfig | 3 + include/configs/mx6sxsabreauto.h | 275 +++++++++++++ 8 files changed, 944 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx6sxsabreauto/Kconfig create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS create mode 100644 board/freescale/mx6sxsabreauto/Makefile create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c create mode 100644 configs/mx6sxsabreauto_defconfig create mode 100644 include/configs/mx6sxsabreauto.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03..9c54914 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -638,6 +638,10 @@ config TARGET_MX6SXSABRESD bool "Support mx6sxsabresd" select CPU_V7
+config TARGET_MX6SXSABREAUTO
- bool "Support mx6sxsabreauto"
- select CPU_V7
config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7 @@ -916,6 +920,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig new file mode 100644 index 0000000..b0f5167 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABREAUTO
+config SYS_BOARD
- default "mx6sxsabreauto"
+config SYS_VENDOR
- default "freescale"
+config SYS_SOC
- default "mx6"
+config SYS_CONFIG_NAME
- default "mx6sxsabreauto"
+endif diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS new file mode 100644 index 0000000..dd3ae41 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABREAUTO BOARD +M: Ye Li Ye.Li@freescale.com +S: Maintained +F: board/freescale/mx6sxsabreauto/ +F: include/configs/mx6sxsabreauto.h +F: configs/mx6sxsabreauto_defconfig diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile new file mode 100644 index 0000000..f0cd1ce --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := mx6sxsabreauto.o diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg new file mode 100644 index 0000000..529e555 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -0,0 +1,136 @@ +/*
- Copyright (C) 2014 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#define __ASSEMBLY__ +#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+/*
- Boot Device : one of
- spi/sd/nand/onenand, qspi/nor
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff
I will not block the patch for this: you are the maintainer and you can test and check if this ok.
I would only to point to the discussion with Peng regarding the same issue for the mx6sxsabresd. Peng confirmed that he would send a following patch for enabling only the clocks are needed. Mybe you can synchronize wit him.
Ungating all clocks won't have functional problem, but consume more power at booting. For mx6 platforms, we won't change it any more, but on following mx7, we will use a new function to initialize needed clocks.
+/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000
+/* Clock */ +DATA 4 0x020e032c 0x00000030
+/* Address */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030
+/* Control */ +DATA 4 0x020e0340 0x00000030
+DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030
+/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030
+/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030
+/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003
+/* Write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046
+/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C
+/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A
+DATA 4 0x021b08c0 0x2492244A
+/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333
+/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000
+/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040
+/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000
ok, I admit that diggering into the DCD table requires too much effort. What about to move to SPL code ? I have expected that new i.MX6 boards will be moved to support SPL, but it looks like that most patches still stick with DCD tables. A couple of Freescale's boards were already ported to SPL and merged. Have you considered to use SPL ? If yes, which are the reason to not support it ?
I think the DCD script "imximage.cfg" is not conflict with SPL. Because for non-SPL case, this file is needed. They are not exclusive. At default Freescale release, we use DCD and plugin. But actually, DCD, SPL and plugin can exist with each others. This provides options for customer to choose.
As a initial BSP version, we only support DCD here, neither SPL and Plugin. But we could consider to add in future.
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c new file mode 100644 index 0000000..a406a1d --- /dev/null +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -0,0 +1,498 @@ +/*
- Copyright (C) 2014 Freescale Semiconductor, Inc.
- Author: Ye Li Ye.Li@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <usb.h> +#include <usb/ehci-fsl.h> +#include <pca953x.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
+#define I2C_PMIC 1
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
+/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
+/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
+#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4) +#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
+static int port_exp_direction_output(unsigned gpio, int value) +{
- int ret;
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
Is it required to call every time i2c_probe() ? Should be called only once ?
The i2c_probe is needed only call once. Since it is a light weight encapsulation for using pca953x, I don't want to add more variables nor functions. I will remove the i2c_probe in next version, it is not necessary.
- if (ret)
return ret;- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));- if (ret)
return ret;- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),(value << PORTEXP_IO_TO_PIN(gpio)));- if (ret)
return ret;- return 0;
+}
+int dram_init(void) +{
- gd->ram_size = PHYS_SDRAM_SIZE;
- return 0;
+}
+static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RST_B, used for power reset cycle */
- MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+static void setup_iomux_uart(void) +{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+static int setup_fec(void) +{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
- return enable_fec_anatop_clock(ENET_125MHZ);
+}
+int board_eth_init(bd_t *bis) +{
- int ret;
- imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
- setup_fec();
- ret = fecmxc_initialize_multi(bis, 1,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);- if (ret)
printf("FEC%d MXC: %s:failed\n", 1, __func__);- return ret;
+}
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,.gp = IMX_GPIO_NR(1, 2),- },
- .sda = {
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,.gp = IMX_GPIO_NR(1, 3),- },
+};
+/* I2C3 for IO Expander */ +struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,.gp = IMX_GPIO_NR(2, 14),- },
- .sda = {
.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,.gp = IMX_GPIO_NR(2, 19),- },
+};
+int power_init_board(void) +{
- struct pmic *p;
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
return -ENODEV;- return 0;
+}
+#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9)
+static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OGT1 */
- MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+static void setup_usb(void) +{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));+}
+int board_usb_phy_mode(int port) +{
- if (port == 1)
return USB_INIT_HOST;- else
return usb_phy_mode(port);+}
+int board_ehci_hcd_init(int port) +{
- u32 *usbnc_usb_ctrl;
- if (port > 1)
return -EINVAL;- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
- return 0;
+} +#endif
+int board_phy_config(struct phy_device *phydev) +{
- /*
* Enable 1.8V(SEL_1P5_1P8_POS_REG) on* Phy control debug reg 0*/- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
- /* rgmii tx clock delay enable */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
- if (phydev->drv->config)
phydev->drv->config(phydev);- return 0;
+}
+int board_early_init_f(void) +{
- setup_iomux_uart();
+#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
Why USB here and not in board_init ? It is not a problem because you set only the pinmux, but if setup_usb() will be changed in future, it is easy to forget that it is called before relocation.
This is copy from mx6sxsabresd. Will move it to board_init.
+#endif
- return 0;
+}
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
+};
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10) +#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
+int board_mmc_getcd(struct mmc *mmc) +{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
- switch (cfg->esdhc_base) {
- case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);break;- case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);break;- }
- return ret;
+}
+int board_mmc_init(bd_t *bis) +{
- int i, ret;
- /*
* According to the board_mmc_init() the following map is done:* (U-boot device node) (Physical Port)* mmc0 USDHC3* mmc1 USDHC4*/- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {case 0:imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));gpio_direction_input(USDHC3_CD_GPIO);/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/gpio_direction_output(USDHC3_RST_GPIO, 0);udelay(1000); /* need 1ms at least */gpio_direction_output(USDHC3_RST_GPIO, 1);usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);break;case 1:imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));gpio_direction_input(USDHC4_CD_GPIO);usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);break;default:printf("Warning: you configured more USDHC controllers""(%d) than supported by the board\n", i + 1);return -EINVAL;}ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);if (ret) {printf("Warning: failed to initialize mmc dev %d\n", i);There was a clean-up patchset by Fabio - fsl_esdhc_initialize() prints already a warning, you do not need a second one here.
Ok, will remove it.
return ret;}- }
- return 0;
+}
+#ifdef CONFIG_FSL_QSPI
+#define QSPI_PAD_CTRL1 \
- (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)+static iomux_v3_cfg_t const quadspi_pads[] = {
- MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+int board_qspi_init(void) +{
- /* Set the iomux */
- imx_iomux_v3_setup_multiple_pads(quadspi_pads,
ARRAY_SIZE(quadspi_pads));- /* Set the clock */
- enable_qspi_clk(0);
- return 0;
+} +#endif
+#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = {
- MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+static void setup_gpmi_nand(void) +{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
- setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+} +#endif
+int board_init(void) +{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#endif
- /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
- port_exp_direction_output(CPU_PER_RST_B, 0);
- udelay(500);
- port_exp_direction_output(CPU_PER_RST_B, 1);
- /* Set steering signal to L for selecting B0 */
- port_exp_direction_output(STEER_ENET, 0);
+#ifdef CONFIG_FSL_QSPI
- board_qspi_init();
+#endif
+#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
+#endif
- return 0;
+}
+int board_late_init(void) +{
- return 0;
+}
Drop it if you do not use it.
Accept.
+int checkboard(void) +{
- puts("Board: MX6SX SABRE AUTO\n");
- return 0;
+} diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig new file mode 100644 index 0000000..ca5ff27 --- /dev/null +++ b/configs/mx6sxsabreauto_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX" +CONFIG_ARM=y +CONFIG_TARGET_MX6SXSABREAUTO=y diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h new file mode 100644 index 0000000..082abaf --- /dev/null +++ b/include/configs/mx6sxsabreauto.h @@ -0,0 +1,275 @@ +/*
- Copyright 2014 Freescale Semiconductor, Inc.
- Configuration settings for the Freescale i.MX6SX Sabreauto board.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h"
+#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200
+/* Command definition */ +#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=imx6sx-sabreauto.dtb\0" \
- "fdt_addr=0x88000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \- "loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \- "bootscript=echo Running bootscript from mmc ...; " \
"source\0" \- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if run loadfdt; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootz; " \"fi;\0" \- "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${image}; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootz; " \"fi;\0"+#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \"else run netboot; fi"+/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024
+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K
+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_2G
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION
+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000
+/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS
+/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8
+/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII
+#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS
+#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif
+#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL
+#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif
+/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif
+#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ
+#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ +#endif
+#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#endif /* __CONFIG_H */
Best regards, Stefano Babic
Best regards, Ye Li
Hi,
On 2/11/2015 5:43 PM, Li Ye-B37916 wrote:
Hi,
On 2/10/2015 6:51 PM, Stefano Babic wrote:
Hi,
On 12/01/2015 09:46, Ye.Li wrote:
Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/Kconfig | 5 + board/freescale/mx6sxsabreauto/Kconfig | 15 + board/freescale/mx6sxsabreauto/MAINTAINERS | 6 + board/freescale/mx6sxsabreauto/Makefile | 6 + board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 498 +++++++++++++++++++++++ configs/mx6sxsabreauto_defconfig | 3 + include/configs/mx6sxsabreauto.h | 275 +++++++++++++ 8 files changed, 944 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx6sxsabreauto/Kconfig create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS create mode 100644 board/freescale/mx6sxsabreauto/Makefile create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c create mode 100644 configs/mx6sxsabreauto_defconfig create mode 100644 include/configs/mx6sxsabreauto.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03..9c54914 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -638,6 +638,10 @@ config TARGET_MX6SXSABRESD bool "Support mx6sxsabresd" select CPU_V7
+config TARGET_MX6SXSABREAUTO
- bool "Support mx6sxsabreauto"
- select CPU_V7
- config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7
@@ -916,6 +920,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig new file mode 100644 index 0000000..b0f5167 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABREAUTO
+config SYS_BOARD
- default "mx6sxsabreauto"
+config SYS_VENDOR
- default "freescale"
+config SYS_SOC
- default "mx6"
+config SYS_CONFIG_NAME
- default "mx6sxsabreauto"
+endif diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS new file mode 100644 index 0000000..dd3ae41 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABREAUTO BOARD +M: Ye Li Ye.Li@freescale.com +S: Maintained +F: board/freescale/mx6sxsabreauto/ +F: include/configs/mx6sxsabreauto.h +F: configs/mx6sxsabreauto_defconfig diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile new file mode 100644 index 0000000..f0cd1ce --- /dev/null +++ b/board/freescale/mx6sxsabreauto/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := mx6sxsabreauto.o diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg new file mode 100644 index 0000000..529e555 --- /dev/null +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -0,0 +1,136 @@ +/*
- Copyright (C) 2014 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#define __ASSEMBLY__ +#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+/*
- Boot Device : one of
- spi/sd/nand/onenand, qspi/nor
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff
I will not block the patch for this: you are the maintainer and you can test and check if this ok.
I would only to point to the discussion with Peng regarding the same issue for the mx6sxsabresd. Peng confirmed that he would send a following patch for enabling only the clocks are needed. Mybe you can synchronize wit him.
Ungating all clocks won't have functional problem, but consume more power at booting. For mx6 platforms, we won't change it any more, but on following mx7, we will use a new function to initialize needed clocks.
+/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000
+/* Clock */ +DATA 4 0x020e032c 0x00000030
+/* Address */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030
+/* Control */ +DATA 4 0x020e0340 0x00000030
+DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030
+/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030
+/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030
+/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003
+/* Write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046
+/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C
+/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A
+DATA 4 0x021b08c0 0x2492244A
+/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333
+/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000
+/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040
+/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000
ok, I admit that diggering into the DCD table requires too much effort. What about to move to SPL code ? I have expected that new i.MX6 boards will be moved to support SPL, but it looks like that most patches still stick with DCD tables. A couple of Freescale's boards were already ported to SPL and merged. Have you considered to use SPL ? If yes, which are the reason to not support it ?
I think the DCD script "imximage.cfg" is not conflict with SPL. Because for non-SPL case, this file is needed. They are not exclusive. At default Freescale release, we use DCD and plugin. But actually, DCD, SPL and plugin can exist with each others. This provides options for customer to choose.
As a initial BSP version, we only support DCD here, neither SPL and Plugin. But we could consider to add in future.
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c new file mode 100644 index 0000000..a406a1d --- /dev/null +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -0,0 +1,498 @@ +/*
- Copyright (C) 2014 Freescale Semiconductor, Inc.
- Author: Ye Li Ye.Li@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" +#include <usb.h> +#include <usb/ehci-fsl.h> +#include <pca953x.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
+#define I2C_PMIC 1
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
+/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
+/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
+#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4) +#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
+static int port_exp_direction_output(unsigned gpio, int value) +{
- int ret;
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
Is it required to call every time i2c_probe() ? Should be called only once ?
The i2c_probe is needed only call once. Since it is a light weight encapsulation for using pca953x, I don't want to add more variables nor functions. I will remove the i2c_probe in next version, it is not necessary.
- if (ret)
return ret;- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));- if (ret)
return ret;- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),(value << PORTEXP_IO_TO_PIN(gpio)));- if (ret)
return ret;- return 0;
+}
+int dram_init(void) +{
- gd->ram_size = PHYS_SDRAM_SIZE;
- return 0;
+}
+static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RST_B, used for power reset cycle */
- MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+static void setup_iomux_uart(void) +{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+static int setup_fec(void) +{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
- return enable_fec_anatop_clock(ENET_125MHZ);
+}
+int board_eth_init(bd_t *bis) +{
- int ret;
- imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
- setup_fec();
- ret = fecmxc_initialize_multi(bis, 1,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);- if (ret)
printf("FEC%d MXC: %s:failed\n", 1, __func__);- return ret;
+}
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,.gp = IMX_GPIO_NR(1, 2),- },
- .sda = {
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,.gp = IMX_GPIO_NR(1, 3),- },
+};
+/* I2C3 for IO Expander */ +struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,.gp = IMX_GPIO_NR(2, 14),- },
- .sda = {
.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,.gp = IMX_GPIO_NR(2, 19),- },
+};
+int power_init_board(void) +{
- struct pmic *p;
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
return -ENODEV;- return 0;
+}
+#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9)
+static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OGT1 */
- MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+static void setup_usb(void) +{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));+}
+int board_usb_phy_mode(int port) +{
- if (port == 1)
return USB_INIT_HOST;- else
return usb_phy_mode(port);+}
+int board_ehci_hcd_init(int port) +{
- u32 *usbnc_usb_ctrl;
- if (port > 1)
return -EINVAL;- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
- return 0;
+} +#endif
+int board_phy_config(struct phy_device *phydev) +{
- /*
* Enable 1.8V(SEL_1P5_1P8_POS_REG) on* Phy control debug reg 0*/- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
- /* rgmii tx clock delay enable */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
- if (phydev->drv->config)
phydev->drv->config(phydev);- return 0;
+}
+int board_early_init_f(void) +{
- setup_iomux_uart();
+#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
Why USB here and not in board_init ? It is not a problem because you set only the pinmux, but if setup_usb() will be changed in future, it is easy to forget that it is called before relocation.
This is copy from mx6sxsabresd. Will move it to board_init.
The usb support patch for mx6sxsabresd which was applied is this one, http://lists.denx.de/pipermail/u-boot/2014-November/194870.html. setup_usb in this patch is called in board_init, but I have no idea why it went into board_early_init_f.
+#endif
- return 0;
+}
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
+};
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10) +#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
+int board_mmc_getcd(struct mmc *mmc) +{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
- switch (cfg->esdhc_base) {
- case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);break;- case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);break;- }
- return ret;
+}
+int board_mmc_init(bd_t *bis) +{
- int i, ret;
- /*
* According to the board_mmc_init() the following map is done:* (U-boot device node) (Physical Port)* mmc0 USDHC3* mmc1 USDHC4*/- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {case 0:imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));gpio_direction_input(USDHC3_CD_GPIO);/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/gpio_direction_output(USDHC3_RST_GPIO, 0);udelay(1000); /* need 1ms at least */gpio_direction_output(USDHC3_RST_GPIO, 1);usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);break;case 1:imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));gpio_direction_input(USDHC4_CD_GPIO);usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);break;default:printf("Warning: you configured more USDHC controllers""(%d) than supported by the board\n", i + 1);return -EINVAL;}ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);if (ret) {printf("Warning: failed to initialize mmc dev %d\n", i);There was a clean-up patchset by Fabio - fsl_esdhc_initialize() prints already a warning, you do not need a second one here.
Ok, will remove it.
return ret;}- }
- return 0;
+}
+#ifdef CONFIG_FSL_QSPI
+#define QSPI_PAD_CTRL1 \
- (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)+static iomux_v3_cfg_t const quadspi_pads[] = {
- MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
- MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+int board_qspi_init(void) +{
- /* Set the iomux */
- imx_iomux_v3_setup_multiple_pads(quadspi_pads,
ARRAY_SIZE(quadspi_pads));- /* Set the clock */
- enable_qspi_clk(0);
- return 0;
+} +#endif
+#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = {
- MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+static void setup_gpmi_nand(void) +{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
- setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+} +#endif
+int board_init(void) +{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#endif
- /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
- port_exp_direction_output(CPU_PER_RST_B, 0);
- udelay(500);
- port_exp_direction_output(CPU_PER_RST_B, 1);
- /* Set steering signal to L for selecting B0 */
- port_exp_direction_output(STEER_ENET, 0);
+#ifdef CONFIG_FSL_QSPI
- board_qspi_init();
+#endif
+#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
+#endif
- return 0;
+}
+int board_late_init(void) +{
- return 0;
+}
Drop it if you do not use it.
Accept.
+int checkboard(void) +{
- puts("Board: MX6SX SABRE AUTO\n");
- return 0;
+} diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig new file mode 100644 index 0000000..ca5ff27 --- /dev/null +++ b/configs/mx6sxsabreauto_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX" +CONFIG_ARM=y +CONFIG_TARGET_MX6SXSABREAUTO=y diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h new file mode 100644 index 0000000..082abaf --- /dev/null +++ b/include/configs/mx6sxsabreauto.h @@ -0,0 +1,275 @@ +/*
- Copyright 2014 Freescale Semiconductor, Inc.
- Configuration settings for the Freescale i.MX6SX Sabreauto board.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h"
+#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200
+/* Command definition */ +#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=imx6sx-sabreauto.dtb\0" \
- "fdt_addr=0x88000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \- "loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \- "bootscript=echo Running bootscript from mmc ...; " \
"source\0" \- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if run loadfdt; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootz; " \"fi;\0" \- "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${image}; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \"bootz ${loadaddr} - ${fdt_addr}; " \"else " \"if test ${boot_fdt} = try; then " \"bootz; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"fi; " \"else " \"bootz; " \"fi;\0"+#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \"else run netboot; fi"+/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024
+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K
+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_2G
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION
+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000
+/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+/* NAND flash command */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS
+/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8
+/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII
+#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS
+#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif
+#define CONFIG_DM +#define CONFIG_DM_THERMAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_IMX6_THERMAL
+#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif
+/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_FSL_QSPI_LE +#define FSL_QSPI_FLASH_SIZE SZ_16M +#define FSL_QSPI_FLASH_NUM 2 +#endif
+#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ
+#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ +#endif
+#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#endif /* __CONFIG_H */
Best regards, Stefano Babic
Best regards, Ye Li
Regards, Peng.
Hi Ye.Li,
On 01/12/2015 10:46 AM, Ye.Li wrote:
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0),@@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0),
Usually the SCL is output-only, driven by the I2C master. Why do you need to enable SION bit on SCL, if the pin will be used as output-only?
Kind regards, Nikolay
Hi,
On 12/01/2015 11:37, Nikolay Dimitrov wrote:
Hi Ye.Li,
On 01/12/2015 10:46 AM, Ye.Li wrote:
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 =IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 =IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
Usually the SCL is output-only, driven by the I2C master. Why do you need to enable SION bit on SCL, if the pin will be used as output-only?
Right - I do not see why SION should be set.
Regards, Stefano Babic
Hi Stefano, Nikolay,
On 1/30/2015 1:54 AM, Stefano Babic wrote:
Hi,
On 12/01/2015 11:37, Nikolay Dimitrov wrote:
Hi Ye.Li,
On 01/12/2015 10:46 AM, Ye.Li wrote:
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 =IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 =IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
Usually the SCL is output-only, driven by the I2C master. Why do you need to enable SION bit on SCL, if the pin will be used as output-only?
Right - I do not see why SION should be set.
Regards, Stefano Babic
Setting SION to both SDA and SCL is required by i.MX6 reference manual. You can find the information below from i2c chapter.
34.2 External Signals This section discusses I2C signals that connect off-chip. For I2C compliance, all devices connected to the I2Cn_SCL and I2Cn_SDA signals must have open-drain or open-collector outputs. The logic AND function is implemented on both lines with external pull-up resistors. Inputs of I2Cn_SCL and I2Cn_SDA also need to be manually enabled by setting the SION bit in the IOMUX after the corresponding PADs are selected as I2C function.
Best regards, Ye Li
Hi,
On 09/02/2015 14:27, Li Ye-B37916 wrote:
Hi Stefano, Nikolay,
On 1/30/2015 1:54 AM, Stefano Babic wrote:
Hi,
On 12/01/2015 11:37, Nikolay Dimitrov wrote:
Hi Ye.Li,
On 01/12/2015 10:46 AM, Ye.Li wrote:
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 =IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 =IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
Usually the SCL is output-only, driven by the I2C master. Why do you need to enable SION bit on SCL, if the pin will be used as output-only?
Right - I do not see why SION should be set.
Regards, Stefano Babic
Setting SION to both SDA and SCL is required by i.MX6 reference manual. You can find the information below from i2c chapter.
34.2 External Signals This section discusses I2C signals that connect off-chip. For I2C compliance, all devices connected to the I2Cn_SCL and I2Cn_SDA signals must have open-drain or open-collector outputs. The logic AND function is implemented on both lines with external pull-up resistors. Inputs of I2Cn_SCL and I2Cn_SDA also need to be manually enabled by setting the SION bit in the IOMUX after the corresponding PADs are selected as I2C function.
Checked in manual, thanks for link. However, I have still a couple of questions. The controller can work as slave or as master, and according to the manual, the slave is the default after a reset. I understand that putting the controller into slave mode must require the SION bit set. Anyway, you are using I2C3 as master in your patch 4/4. Is it still mandatory even in this case to set the SION bit ? The manual states that to use the signal as input the SION bit must be set, but as far as I see in the patchset SCL is output only.
Best regards, Stefano Babic
Hi guys,
On 02/10/2015 12:18 PM, Stefano Babic wrote:
Hi,
On 09/02/2015 14:27, Li Ye-B37916 wrote:
Hi Stefano, Nikolay,
On 1/30/2015 1:54 AM, Stefano Babic wrote:
Hi,
On 12/01/2015 11:37, Nikolay Dimitrov wrote:
Hi Ye.Li,
On 01/12/2015 10:46 AM, Ye.Li wrote:
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li B37916@freescale.com
arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 =IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__I2C3_SCL =IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 =IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__I2C3_SDA =IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
Usually the SCL is output-only, driven by the I2C master. Why do you need to enable SION bit on SCL, if the pin will be used as output-only?
Right - I do not see why SION should be set.
Regards, Stefano Babic
Setting SION to both SDA and SCL is required by i.MX6 reference manual. You can find the information below from i2c chapter.
34.2 External Signals This section discusses I2C signals that connect off-chip. For I2C compliance, all devices connected to the I2Cn_SCL and I2Cn_SDA signals must have open-drain or open-collector outputs. The logic AND function is implemented on both lines with external pull-up resistors. Inputs of I2Cn_SCL and I2Cn_SDA also need to be manually enabled by setting the SION bit in the IOMUX after the corresponding PADs are selected as I2C function.
Checked in manual, thanks for link. However, I have still a couple of questions. The controller can work as slave or as master, and according to the manual, the slave is the default after a reset. I understand that putting the controller into slave mode must require the SION bit set. Anyway, you are using I2C3 as master in your patch 4/4. Is it still mandatory even in this case to set the SION bit ? The manual states that to use the signal as input the SION bit must be set, but as far as I see in the patchset SCL is output only.
Just tested the behavior of SION bit on imx6sl (riotboard), as I don't have imx6sx hardware.
For the test I used I2C4, located on expansion connector J13. I verified that the SION bits are enabled after boot:
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018
I also verified that the I2C interface works as expected (by observing I2C transactions on a digital scope):
i2cdetect -y 3
This works so far. Then I disabled the SION bits for both iomuxes:
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x08 IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018 IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 == 0x00000018...0x00000008
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x08 IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018 IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c == 0x00000018...0x00000008
Now interface I2C4 doesn't work anymore. Instead of complete I2C transactions, I see just a single pulses on both clock/data lines, repeated on each 500ms. At the same time i2cdetect scans the address space much more slowly than usual, and it looks like it timeouts on each single address check for the same amount of time (500ms).
Restoring the SION bits for clock & data restores the I2C4 functionality. All the time the port was in master mode.
I don't have experience with imx6sx, but if the I2C IP core was reused for imx6sx (which is very likely), then I tend to agree with Ye Li that the SION bits will have to be enabled.
Hope this helps. Regards, Nikolay
Hi everybody,
On 15/02/2015 16:11, Nikolay Dimitrov wrote:
Checked in manual, thanks for link. However, I have still a couple of questions. The controller can work as slave or as master, and according to the manual, the slave is the default after a reset. I understand that putting the controller into slave mode must require the SION bit set. Anyway, you are using I2C3 as master in your patch 4/4. Is it still mandatory even in this case to set the SION bit ? The manual states that to use the signal as input the SION bit must be set, but as far as I see in the patchset SCL is output only.
Just tested the behavior of SION bit on imx6sl (riotboard), as I don't have imx6sx hardware.
For the test I used I2C4, located on expansion connector J13. I verified that the SION bits are enabled after boot:
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018
I also verified that the I2C interface works as expected (by observing I2C transactions on a digital scope):
i2cdetect -y 3
This works so far. Then I disabled the SION bits for both iomuxes:
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x08 IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 =0x00000018 IOMUXC_SW_MUX_CTL_PAD_GPIO07:0x020e0238 == 0x00000018...0x00000008
# devregs IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x08 IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c =0x00000018 IOMUXC_SW_MUX_CTL_PAD_GPIO08:0x020e023c == 0x00000018...0x00000008
Now interface I2C4 doesn't work anymore. Instead of complete I2C transactions, I see just a single pulses on both clock/data lines, repeated on each 500ms. At the same time i2cdetect scans the address space much more slowly than usual, and it looks like it timeouts on each single address check for the same amount of time (500ms).
Restoring the SION bits for clock & data restores the I2C4 functionality. All the time the port was in master mode.
I don't have experience with imx6sx, but if the I2C IP core was reused for imx6sx (which is very likely), then I tend to agree with Ye Li that the SION bits will have to be enabled.
Thanks for testing and to share your experience. I will merge Li's patch now.
Thanks again, Stefano Babic
participants (5)
-
Li Ye-B37916 -
Nikolay Dimitrov -
Peng Fan -
Stefano Babic -
Ye.Li