From: Harald Krapfenbauer Harald.Krapfenbauer@bluetechnix.at

The tinyboards like to run at a little lower voltage than the default, and they prefer to boot over the network. For the latter, extend the common code a little to make this easier.

Also fix the cm-bf527 env sector size while we're in here to reflect the flash that is actually in use.

Signed-off-by: Harald Krapfenbauer Harald.Krapfenbauer@bluetechnix.at Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/configs/bfin_adi_common.h | 5 ++++- include/configs/cm-bf527.h | 7 ++++++- include/configs/cm-bf533.h | 5 +++++ include/configs/cm-bf537e.h | 5 +++++ include/configs/cm-bf537u.h | 11 ++--------- include/configs/cm-bf548.h | 5 +++++ include/configs/cm-bf561.h | 7 ++++++- include/configs/tcm-bf537.h | 5 +++++ 8 files changed, 38 insertions(+), 12 deletions(-)

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 0fbd8f4..3fc0fa0 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -127,6 +127,9 @@ #ifndef CONFIG_BOOTARGS_ROOT # define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" #endif +#ifndef FLASHBOOT_ENV_SETTINGS +# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0" +#endif #define CONFIG_BOOTARGS \ "root=" CONFIG_BOOTARGS_ROOT " " \ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ @@ -211,7 +214,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ NAND_ENV_SETTINGS \ NETWORK_ENV_SETTINGS \ - "flashboot=bootm 0x20100000\0" + FLASHBOOT_ENV_SETTINGS

/* * Network Settings diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index 3d41bd1..eb0bc3f 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4

+/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000) +

/* * Memory Settings @@ -105,7 +108,7 @@ #define CONFIG_ENV_ADDR 0x20008000 #define CONFIG_ENV_OFFSET 0x8000 #define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x8000 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR

@@ -125,6 +128,8 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=flread 20040000 1000000 300000; bootm 0x1000000\0"

/* diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index 06eb288..7515296 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5

+/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) +

/* * Memory Settings @@ -93,6 +96,8 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"

/* diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index b243e1a..f51fa9c 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4

+/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) +

/* * Memory Settings @@ -127,6 +130,8 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=flread 20040000 1000000 300000; bootm 0x1000000\0"

/* diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 0ed5960..6937225 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -131,6 +131,8 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0"

/* @@ -138,13 +140,4 @@ */ #include <configs/bfin_adi_common.h>

-#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "run flashboot" - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - NAND_ENV_SETTINGS \ - NETWORK_ENV_SETTINGS \ - "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0" - #endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 9630f7d..93c4c8d 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4

+/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) +

/* * Memory Settings @@ -115,6 +118,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"

#ifndef __ADSPBF542__ /* Don't waste time transferring a logo over the UART */ diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 4a77435..1741ed4 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -30,7 +30,7 @@ #define CONFIG_PLL_BYPASS 0 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ /* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 22 +#define CONFIG_VCO_MULT 20 /* CCLK_DIV controls the core clock divider */ /* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1 @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5

+/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) +

/* * Memory Settings @@ -98,6 +101,8 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"

/* diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 9615ced..f2ac6cd 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -38,6 +38,9 @@ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 4

+/* Decrease core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000) +

/* * Memory Settings @@ -128,6 +131,8 @@ #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define FLASHBOOT_ENV_SETTINGS "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0"

/*

Very little additional code overhead, and only works when the user sets an env var ahead of time, so default to on makes sense.

Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/configs/bfin_adi_common.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 3fc0fa0..42f4cbc 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -96,6 +96,7 @@ #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_LOADS_ECHO 1 #define CONFIG_JTAG_CONSOLE +#define CONFIG_SILENT_CONSOLE #ifndef CONFIG_BAUDRATE # define CONFIG_BAUDRATE 57600 #endif

The length of the sections is fixed at link time, so let the linker do the calculation rather than doing it ourselves at runtime.

Signed-off-by: Mike Frysinger vapier@gentoo.org --- cpu/blackfin/cpu.c | 11 +++++------ cpu/blackfin/start.S | 18 ++++++++---------- lib_blackfin/u-boot.lds.S | 24 +++++++++++++++++------- 3 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c index 9bb6407..2c8fd86 100644 --- a/cpu/blackfin/cpu.c +++ b/cpu/blackfin/cpu.c @@ -25,13 +25,12 @@ ulong bfin_poweron_retx; __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { - extern char _stext_l1; #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1 /* Build a NOP slide over the LDR jump block. Whee! */ char nops[0xC]; serial_early_puts("NOP Slide\n"); memset(nops, 0x00, sizeof(nops)); - memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops)); + memcpy((void *)L1_INST_SRAM, nops, sizeof(nops)); #endif

if (!loaded_from_ldr) { @@ -40,10 +39,10 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) * checking at build time. */ serial_early_puts("L1 Relocate\n"); - extern char _stext_l1, _etext_l1, _stext_l1_lma; - memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1)); - extern char _sdata_l1, _edata_l1, _sdata_l1_lma; - memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1)); + extern char _stext_l1[], _text_l1_lma[], _text_l1_len[]; + memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len); + extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[]; + memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len); } #if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) /* The BF537 bootrom will reset the EBIU_AMGCTL register on us diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S index 7cbd632..44e2725 100644 --- a/cpu/blackfin/start.S +++ b/cpu/blackfin/start.S @@ -139,11 +139,10 @@ ENTRY(_start) .Ldma_and_reprogram: r0.l = LO(L1_INST_SRAM); r0.h = HI(L1_INST_SRAM); - r1.l = __initcode_start; - r1.h = __initcode_start; - r2.l = __initcode_end; - r2.h = __initcode_end; - r2 = r2 - r1; /* convert r2 into length of initcode */ + r1.l = __initcode_lma; + r1.h = __initcode_lma; + r2.l = __initcode_len; + r2.h = __initcode_len; r1 = r1 - r4; /* convert r1 from load address of initcode ... */ r1 = r1 + r5; /* ... to current (not load) address of initcode */ p3 = r0; @@ -173,12 +172,11 @@ ENTRY(_start) * takes care of clearing things for us. */ serial_early_puts("Zero BSS"); - r0.l = __bss_start; - r0.h = __bss_start; + r0.l = __bss_vma; + r0.h = __bss_vma; r1 = 0 (x); - r2.l = __bss_end; - r2.h = __bss_end; - r2 = r2 - r0; + r2.l = __bss_len; + r2.h = __bss_len; call _memset;

.Lnorelocate: diff --git a/lib_blackfin/u-boot.lds.S b/lib_blackfin/u-boot.lds.S index 3604b78..8a9e8b1 100644 --- a/lib_blackfin/u-boot.lds.S +++ b/lib_blackfin/u-boot.lds.S @@ -65,16 +65,22 @@ MEMORY ENTRY(_start) SECTIONS { - .text : + .text.pre : { cpu/blackfin/start.o (.text .text.*)

LDS_BOARD_TEXT + } >ram_code

- __initcode_start = .; + .text.init : + { cpu/blackfin/initcode.o (.text .text.*) - __initcode_end = .; + } >ram_code + __initcode_lma = LOADADDR(.text.init); + __initcode_len = SIZEOF(.text.init);

+ .text : + { *(.text .text.*) } >ram

@@ -113,7 +119,9 @@ SECTIONS . = ALIGN(4); __etext_l1 = .; } >l1_code AT>ram - __stext_l1_lma = LOADADDR(.text_l1); + __text_l1_lma = LOADADDR(.text_l1); + __text_l1_len = SIZEOF(.text_l1); + ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")

.data_l1 : { @@ -124,16 +132,18 @@ SECTIONS . = ALIGN(4); __edata_l1 = .; } >l1_data AT>ram - __sdata_l1_lma = LOADADDR(.data_l1); + __data_l1_lma = LOADADDR(.data_l1); + __data_l1_len = SIZEOF(.data_l1); + ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!")

.bss : { . = ALIGN(4); - __bss_start = .; *(.sbss) *(.scommon) *(.dynbss) *(.bss .bss.*) *(COMMON) - __bss_end = .; } >ram + __bss_vma = ADDR(.bss); + __bss_len = SIZEOF(.bss); }

While the initdram() function makes sense on some arches, it doesn't for Blackfin systems as it's always implemented the same way.

Signed-off-by: Mike Frysinger vapier@gentoo.org --- board/bf518f-ezbrd/bf518f-ezbrd.c | 7 ------- board/bf526-ezbrd/bf526-ezbrd.c | 7 ------- board/bf527-ezkit/bf527-ezkit.c | 7 ------- board/bf533-ezkit/bf533-ezkit.c | 7 ------- board/bf533-stamp/bf533-stamp.c | 7 ------- board/bf537-minotaur/bf537-minotaur.c | 7 ------- board/bf537-pnav/bf537-pnav.c | 7 ------- board/bf537-srv1/bf537-srv1.c | 7 ------- board/bf537-stamp/bf537-stamp.c | 7 ------- board/bf538f-ezkit/bf538f-ezkit.c | 7 ------- board/bf548-ezkit/bf548-ezkit.c | 7 ------- board/bf561-acvilon/bf561-acvilon.c | 7 ------- board/bf561-ezkit/bf561-ezkit.c | 7 ------- board/blackstamp/blackstamp.c | 7 ------- board/cm-bf527/cm-bf527.c | 7 ------- board/cm-bf533/cm-bf533.c | 7 ------- board/cm-bf537e/cm-bf537e.c | 7 ------- board/cm-bf537u/cm-bf537u.c | 7 ------- board/cm-bf548/cm-bf548.c | 7 ------- board/cm-bf561/cm-bf561.c | 7 ------- board/ibf-dsp561/ibf-dsp561.c | 7 ------- board/tcm-bf537/tcm-bf537.c | 7 ------- lib_blackfin/board.c | 4 +++- 23 files changed, 3 insertions(+), 155 deletions(-)

diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 63be7cf..279c55c 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -25,13 +25,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #if defined(CONFIG_BFIN_MAC) static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c index 1666bf6..52d82cd 100644 --- a/board/bf526-ezbrd/bf526-ezbrd.c +++ b/board/bf526-ezbrd/bf526-ezbrd.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index 2cbfa8d..a880066 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 8727dee..b1aa7b7 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -39,13 +39,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - /* miscellaneous platform dependent initialisations */ int misc_init_r(void) { diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index a226910..7a63c52 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -39,13 +39,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - /* PF0 and PF1 are used to switch between the ethernet and flash: * PF0 PF1 * flash: 0 0 diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c index 71b452a..920429c 100644 --- a/board/bf537-minotaur/bf537-minotaur.c +++ b/board/bf537-minotaur/bf537-minotaur.c @@ -23,13 +23,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c index 12cfefa..c512528 100644 --- a/board/bf537-pnav/bf537-pnav.c +++ b/board/bf537-pnav/bf537-pnav.c @@ -23,13 +23,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c index 5ad39cc..04d3891 100644 --- a/board/bf537-srv1/bf537-srv1.c +++ b/board/bf537-srv1/bf537-srv1.c @@ -23,13 +23,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 28597c9..3911be6 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -43,13 +43,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - void board_reset(void) { /* workaround for weak pull ups on ssel */ diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c index 15916fa..49d30e7 100644 --- a/board/bf538f-ezkit/bf538f-ezkit.c +++ b/board/bf538f-ezkit/bf538f-ezkit.c @@ -20,13 +20,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 88a0cd4..29c2e92 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -21,13 +21,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - int board_early_init_f(void) { /* Port H: PH8 - PH13 == A4 - A9 diff --git a/board/bf561-acvilon/bf561-acvilon.c b/board/bf561-acvilon/bf561-acvilon.c index 3129f05..2f6aa09 100644 --- a/board/bf561-acvilon/bf561-acvilon.c +++ b/board/bf561-acvilon/bf561-acvilon.c @@ -44,13 +44,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC911X int board_eth_init(bd_t *bis) { diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index e5d7eb3..b2411b6 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -38,13 +38,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index f55ab97..6355c10 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef SHARED_RESOURCES void swap_to(int device_id) { diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index db1cf90..b6815b1 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c index ab0bf3b..a863195 100644 --- a/board/cm-bf533/cm-bf533.c +++ b/board/cm-bf533/cm-bf533.c @@ -18,13 +18,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c index d1ca0a4..1e350dc 100644 --- a/board/cm-bf537e/cm-bf537e.c +++ b/board/cm-bf537e/cm-bf537e.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 9628e0f..92fa5a0 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c index 796263d..3627586 100644 --- a/board/cm-bf548/cm-bf548.c +++ b/board/cm-bf548/cm-bf548.c @@ -21,13 +21,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - int board_early_init_f(void) { /* Port H: PH8 - PH13 == A4 - A9 diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c index f21a015..80cfff7 100644 --- a/board/cm-bf561/cm-bf561.c +++ b/board/cm-bf561/cm-bf561.c @@ -18,13 +18,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c index 551fc29..b5bebd4 100644 --- a/board/ibf-dsp561/ibf-dsp561.c +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -16,10 +16,3 @@ int checkboard(void) printf(" Support: http://www.i-syst.com/%5Cn"); return 0; } - -phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 573387d..60742df 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -24,13 +24,6 @@ int checkboard(void) return 0; }

-phys_size_t initdram(int board_type) -{ - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return gd->bd->bi_memsize; -} - #ifdef CONFIG_BFIN_MAC static void board_init_enetaddr(uchar *mac_addr) { diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 1c3b461..f6ff89b 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -241,6 +241,8 @@ void board_init_f(ulong bootflag) bd->bi_vco = get_vco(); bd->bi_cclk = get_cclk(); bd->bi_sclk = get_sclk(); + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;

/* Initialize */ serial_early_puts("IRQ init\n"); @@ -264,7 +266,7 @@ void board_init_f(ulong bootflag) printf("System: %s MHz\n", strmhz(buf, get_sclk()));

printf("RAM: "); - print_size(initdram(0), "\n"); + print_size(bd->bi_memsize, "\n"); #if defined(CONFIG_POST) post_init_f(); post_bootmode_init();

The single initcode function was growing unwieldy, so split it up the distinct steps into their own function. This should making digesting the result much easier on people.

Signed-off-by: Mike Frysinger vapier@gentoo.org --- cpu/blackfin/initcode.c | 221 ++++++++++++++++++++++++++++++++++++----------- 1 files changed, 169 insertions(+), 52 deletions(-)

diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 90a5fc3..9b0cfbc 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -9,6 +9,8 @@ * Licensed under the GPL-2 or later. */

+#define BFIN_IN_INITCODE + #include <config.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/bootrom.h> @@ -17,7 +19,6 @@ #include <asm/mach-common/bits/pll.h> #include <asm/mach-common/bits/uart.h>

-#define BFIN_IN_INITCODE #include "serial.h"

__attribute__((always_inline)) @@ -216,6 +217,7 @@ static inline void serial_putc(char c) # define CONFIG_HAS_VR 1 #endif

+#if CONFIG_MEM_SIZE #ifndef EBIU_RSTCTL /* Blackfin with SDRAM */ #ifndef CONFIG_EBIU_SDBCTL_VAL @@ -248,6 +250,7 @@ static inline void serial_putc(char c) # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE) #endif #endif +#endif

/* Conflicting Column Address Widths Causes SDRAM Errors: * EB2CAW and EB3CAW must be the same @@ -258,28 +261,21 @@ static inline void serial_putc(char c) # endif #endif

-BOOTROM_CALLED_FUNC_ATTR -void initcode(ADI_BOOT_DATA *bootstruct) +__attribute__((always_inline)) static inline void +program_early_devices(ADI_BOOT_DATA *bootstruct, uint *sdivB, uint *divB, uint *vcoB) { - ADI_BOOT_DATA bootstruct_scratch; + serial_putc('a');

/* Save the clock pieces that are used in baud rate calculation */ - unsigned int sdivB, divB, vcoB; - serial_init(); if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { - sdivB = bfin_read_PLL_DIV() & 0xf; - vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; - divB = serial_early_get_div(); + serial_putc('b'); + *sdivB = bfin_read_PLL_DIV() & 0xf; + *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; + *divB = serial_early_get_div(); + serial_putc('c'); }

- serial_putc('A'); - - /* If the bootstruct is NULL, then it's because we're loading - * dynamically and not via LDR (bootrom). So set the struct to - * some scratch space. - */ - if (!bootstruct) - bootstruct = &bootstruct_scratch; + serial_putc('d');

#ifdef CONFIG_HW_WATCHDOG # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE @@ -292,41 +288,69 @@ void initcode(ADI_BOOT_DATA *bootstruct) * timeout, so don't clobber that. */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { + serial_putc('e'); bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); bfin_write_WDOG_CTL(0); + serial_putc('f'); } #endif

- serial_putc('B'); + serial_putc('g'); + + /* Blackfin bootroms use the SPI slow read opcode instead of the SPI + * fast read, so we need to slow down the SPI clock a lot more during + * boot. Once we switch over to u-boot's SPI flash driver, we'll + * increase the speed appropriately. + */ + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { + serial_putc('h'); + if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) + bootstruct->dFlags |= BFLAG_FASTREAD; + bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); + serial_putc('i'); + } + + serial_putc('j'); +} + +__attribute__((always_inline)) static inline bool +maybe_self_refresh(ADI_BOOT_DATA *bootstruct) +{ + serial_putc('a'); + + if (!CONFIG_MEM_SIZE) + return false;

/* If external memory is enabled, put it into self refresh first. */ - bool put_into_srfs = false; #ifdef EBIU_RSTCTL if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { + serial_putc('b'); bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); - put_into_srfs = true; + return true; } #else if (bfin_read_EBIU_SDBCTL() & EBE) { + serial_putc('b'); bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); - put_into_srfs = true; + return true; } #endif

- serial_putc('C'); + serial_putc('c');

- /* Blackfin bootroms use the SPI slow read opcode instead of the SPI - * fast read, so we need to slow down the SPI clock a lot more during - * boot. Once we switch over to u-boot's SPI flash driver, we'll - * increase the speed appropriately. - */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { - if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) - bootstruct->dFlags |= BFLAG_FASTREAD; - bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); - } + return false; +}

- serial_putc('D'); +__attribute__((always_inline)) static inline u16 +program_clocks(ADI_BOOT_DATA *bootstruct, bool put_into_srfs) +{ + u16 vr_ctl; + + serial_putc('a'); + + vr_ctl = bfin_read_VR_CTL(); + + serial_putc('b');

/* If we're entering self refresh, make sure it has happened. */ if (put_into_srfs) @@ -337,15 +361,14 @@ void initcode(ADI_BOOT_DATA *bootstruct) #endif continue;

- serial_putc('E'); + serial_putc('c');

/* With newer bootroms, we use the helper function to set up * the memory controller. Older bootroms lacks such helpers * so we do it ourselves. */ - uint16_t vr_ctl = bfin_read_VR_CTL(); if (!ANOMALY_05000386) { - serial_putc('F'); + serial_putc('d');

/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ ADI_SYSCTRL_VALUES memory_settings; @@ -365,7 +388,9 @@ void initcode(ADI_BOOT_DATA *bootstruct) #if ANOMALY_05000432 bfin_write_SIC_IWR1(0); #endif + serial_putc('e'); bfrom_SysControl(actions, &memory_settings, NULL); + serial_putc('f'); #if ANOMALY_05000432 bfin_write_SIC_IWR1(-1); #endif @@ -373,8 +398,9 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_SICA_IWR0(-1); bfin_write_SICA_IWR1(-1); #endif + serial_putc('g'); } else { - serial_putc('G'); + serial_putc('h');

/* Disable all peripheral wakeups except for the PLL event. */ #ifdef SIC_IWR0 @@ -390,38 +416,40 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_SIC_IWR(1); #endif

- serial_putc('H'); + serial_putc('i');

/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);

- serial_putc('I'); + serial_putc('j');

/* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ if (vr_ctl != CONFIG_VR_CTL_VAL) { - serial_putc('!'); + serial_putc('?'); bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); asm("idle;"); + serial_putc('!'); }

- serial_putc('J'); + serial_putc('k');

bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);

- serial_putc('K'); + serial_putc('l');

/* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { - serial_putc('!'); + serial_putc('?'); bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); asm("idle;"); + serial_putc('!'); }

- serial_putc('L'); + serial_putc('m');

/* Restore all peripheral wakeups. */ #ifdef SIC_IWR0 @@ -436,9 +464,19 @@ void initcode(ADI_BOOT_DATA *bootstruct) #else bfin_write_SIC_IWR(-1); #endif + + serial_putc('n'); }

- serial_putc('M'); + serial_putc('o'); + + return vr_ctl; +} + +__attribute__((always_inline)) static inline void +update_serial_clocks(ADI_BOOT_DATA *bootstruct, uint sdivB, uint divB, uint vcoB) +{ + serial_putc('a');

/* Since we've changed the SCLK above, we may need to update * the UART divisors (UART baud rates are based on SCLK). @@ -446,6 +484,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) * for dividing which means we'd generate a libgcc reference. */ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + serial_putc('b'); unsigned int sdivR, vcoR; sdivR = bfin_read_PLL_DIV() & 0xf; vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; @@ -455,20 +494,38 @@ void initcode(ADI_BOOT_DATA *bootstruct) for (quotient = 0; dividend > 0; ++quotient) dividend -= divisor; serial_early_put_div(quotient - ANOMALY_05000230); + serial_putc('c'); }

- serial_putc('N'); + serial_putc('d'); +} + +__attribute__((always_inline)) static inline void +program_memory_controller(ADI_BOOT_DATA *bootstruct, bool put_into_srfs) +{ + serial_putc('a'); + + if (!CONFIG_MEM_SIZE) + return; + + serial_putc('b');

/* Program the external memory controller before we come out of * self-refresh. This only works with our SDRAM controller. */ #ifndef EBIU_RSTCTL +# ifdef CONFIG_EBIU_SDRRC_VAL bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); +# endif +# ifdef CONFIG_EBIU_SDBCTL_VAL bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL); +# endif +# ifdef CONFIG_EBIU_SDGCTL_VAL bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL); +# endif #endif

- serial_putc('O'); + serial_putc('c');

/* Now that we've reprogrammed, take things out of self refresh. */ if (put_into_srfs) @@ -478,7 +535,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS)); #endif

- serial_putc('P'); + serial_putc('d');

/* Our DDR controller sucks and cannot be programmed while in * self-refresh. So we have to pull it out before programming. @@ -497,7 +554,18 @@ void initcode(ADI_BOOT_DATA *bootstruct) # endif #endif

- serial_putc('Q'); + serial_putc('e'); +} + +__attribute__((always_inline)) static inline void +check_hibernation(ADI_BOOT_DATA *bootstruct, u16 vr_ctl, bool put_into_srfs) +{ + serial_putc('a'); + + if (!CONFIG_MEM_SIZE) + return; + + serial_putc('b');

/* Are we coming out of hibernate (suspend to memory) ? * The memory layout is: @@ -511,7 +579,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) uint32_t *hibernate_magic = 0; __builtin_bfin_ssync(); /* make sure memory controller is done */ if (hibernate_magic[0] == 0xDEADBEEF) { - serial_putc('R'); + serial_putc('c'); bfin_write_EVT15(hibernate_magic[1]); bfin_write_IMASK(EVT_IVG15); __asm__ __volatile__ ( @@ -528,15 +596,24 @@ void initcode(ADI_BOOT_DATA *bootstruct) : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */) ); } + serial_putc('d'); }

- serial_putc('S'); + serial_putc('e'); +} + +__attribute__((always_inline)) static inline void +program_async_controller(ADI_BOOT_DATA *bootstruct) +{ + serial_putc('a');

/* Program the async banks controller. */ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);

+ serial_putc('b'); + #ifdef EBIU_MODE /* Not all parts have these additional MMRs. */ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); @@ -544,9 +621,49 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); #endif

- serial_putc('T'); + serial_putc('c'); +} + +BOOTROM_CALLED_FUNC_ATTR +void initcode(ADI_BOOT_DATA *bootstruct) +{ + ADI_BOOT_DATA bootstruct_scratch; + + serial_init(); + + serial_putc('A'); + + /* If the bootstruct is NULL, then it's because we're loading + * dynamically and not via LDR (bootrom). So set the struct to + * some scratch space. + */ + if (!bootstruct) + bootstruct = &bootstruct_scratch; + + serial_putc('B'); + bool put_into_srfs = maybe_self_refresh(bootstruct); + + serial_putc('C'); + uint sdivB, divB, vcoB; + program_early_devices(bootstruct, &sdivB, &divB, &vcoB); + + serial_putc('D'); + u16 vr_ctl = program_clocks(bootstruct, put_into_srfs); + + serial_putc('E'); + update_serial_clocks(bootstruct, sdivB, divB, vcoB); + + serial_putc('F'); + program_memory_controller(bootstruct, put_into_srfs); + + serial_putc('G'); + check_hibernation(bootstruct, vr_ctl, put_into_srfs); + + serial_putc('H'); + program_async_controller(bootstruct);

#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 + serial_putc('I'); /* tell the bootrom where our entry point is */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);

Unify the duplicated macros at the same time.

Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/asm-blackfin/blackfin_local.h | 2 ++ include/asm-blackfin/mach-bf527/BF522_def.h | 15 --------------- include/asm-blackfin/mach-bf527/BF523_def.h | 15 --------------- include/asm-blackfin/mach-bf527/BF524_def.h | 15 --------------- include/asm-blackfin/mach-bf527/BF525_def.h | 15 --------------- include/asm-blackfin/mach-bf527/BF526_def.h | 15 --------------- include/asm-blackfin/mach-bf527/BF527_def.h | 15 --------------- include/asm-blackfin/mach-bf527/def_local.h | 1 + include/asm-blackfin/mach-bf527/mem_map.h | 21 +++++++++++++++++++++ include/asm-blackfin/mach-bf548/BF542_def.h | 15 --------------- include/asm-blackfin/mach-bf548/BF544_def.h | 15 --------------- include/asm-blackfin/mach-bf548/BF547_def.h | 9 --------- include/asm-blackfin/mach-bf548/BF548_def.h | 15 --------------- include/asm-blackfin/mach-bf548/BF549_def.h | 15 --------------- include/asm-blackfin/mach-bf548/def_local.h | 1 + include/asm-blackfin/mach-bf548/mem_map.h | 21 +++++++++++++++++++++ include/asm-blackfin/mem_map.h | 26 ++++++++++++++++++++++++++ 17 files changed, 72 insertions(+), 159 deletions(-) create mode 100644 include/asm-blackfin/mach-bf527/mem_map.h create mode 100644 include/asm-blackfin/mach-bf548/mem_map.h create mode 100644 include/asm-blackfin/mem_map.h

diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index 8ec7928..308014a 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -25,6 +25,8 @@ #ifndef __BLACKFIN_LOCAL_H__ #define __BLACKFIN_LOCAL_H__

+#include <asm/mem_map.h> + #define LO(con32) ((con32) & 0xFFFF) #define lo(con32) ((con32) & 0xFFFF) #define HI(con32) (((con32) >> 16) & 0xFFFF) diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h index 44143ba..bc05029 100644 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ b/include/asm-blackfin/mach-bf527/BF522_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h index 02675a9..c27fd64 100644 --- a/include/asm-blackfin/mach-bf527/BF523_def.h +++ b/include/asm-blackfin/mach-bf527/BF523_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h index 10793e8..bd6aa8f 100644 --- a/include/asm-blackfin/mach-bf527/BF524_def.h +++ b/include/asm-blackfin/mach-bf527/BF524_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF524_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h index c4c2f2f..5e88b3b 100644 --- a/include/asm-blackfin/mach-bf527/BF525_def.h +++ b/include/asm-blackfin/mach-bf527/BF525_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF525_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h index 04db6c7..2644abf 100644 --- a/include/asm-blackfin/mach-bf527/BF526_def.h +++ b/include/asm-blackfin/mach-bf527/BF526_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF526_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h index c1e1aab..c46c2b0 100644 --- a/include/asm-blackfin/mach-bf527/BF527_def.h +++ b/include/asm-blackfin/mach-bf527/BF527_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF527_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/def_local.h b/include/asm-blackfin/mach-bf527/def_local.h index 14c111f..81eca83 100644 --- a/include/asm-blackfin/mach-bf527/def_local.h +++ b/include/asm-blackfin/mach-bf527/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h new file mode 100644 index 0000000..8386b4b --- /dev/null +++ b/include/asm-blackfin/mach-bf527/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF52X_MEM_MAP_H__ +#define __BF52X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h index 40fe555..1324a13 100644 --- a/include/asm-blackfin/mach-bf548/BF542_def.h +++ b/include/asm-blackfin/mach-bf548/BF542_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF542_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h index 042e2ac..aef6e48 100644 --- a/include/asm-blackfin/mach-bf548/BF544_def.h +++ b/include/asm-blackfin/mach-bf548/BF544_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF544_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h index 1cb3381..ce7c880 100644 --- a/include/asm-blackfin/mach-bf548/BF547_def.h +++ b/include/asm-blackfin/mach-bf548/BF547_def.h @@ -113,14 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF547_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h index 950ce43..e02e843 100644 --- a/include/asm-blackfin/mach-bf548/BF548_def.h +++ b/include/asm-blackfin/mach-bf548/BF548_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF548_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h index 55b0a29..a16ff5a 100644 --- a/include/asm-blackfin/mach-bf548/BF549_def.h +++ b/include/asm-blackfin/mach-bf548/BF549_def.h @@ -113,20 +113,5 @@ #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ #define TBUF 0xFFE06100 /* Trace Buffer */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)

#endif /* __BFIN_DEF_ADSP_BF549_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/def_local.h b/include/asm-blackfin/mach-bf548/def_local.h index 14c111f..81eca83 100644 --- a/include/asm-blackfin/mach-bf548/def_local.h +++ b/include/asm-blackfin/mach-bf548/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h new file mode 100644 index 0000000..4f94397 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF54X_MEM_MAP_H__ +#define __BF54X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h new file mode 100644 index 0000000..3e361d6 --- /dev/null +++ b/include/asm-blackfin/mem_map.h @@ -0,0 +1,26 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MEM_MAP_H__ +#define __BFIN_MEM_MAP_H__ + +/* Every Blackfin so far has MMRs like this */ +#ifndef COREMMR_BASE +# define COREMMR_BASE 0xFFE00000 +#endif +#ifndef SYSMMR_BASE +# define SYSMMR_BASE 0xFFC00000 +#endif + +/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ +#ifndef L1_SRAM_SCRATCH +# define L1_SRAM_SCRATCH 0xFFB00000 +# define L1_SRAM_SCRATCH_SIZE 0x1000 +# define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) +#endif + +#endif

Signed-off-by: Mike Frysinger vapier@gentoo.org --- cpu/blackfin/initcode.c | 10 ++-- cpu/blackfin/interrupts.c | 12 ++-- cpu/blackfin/serial.c | 20 ++--- cpu/blackfin/serial.h | 119 +++++++++++++++++--------------- include/asm-blackfin/blackfin_local.h | 2 +- 5 files changed, 83 insertions(+), 80 deletions(-)

diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index b99f70c..a97664c 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -34,7 +34,7 @@ static inline void serial_init(void) size_t i;

/* force RTS rather than relying on auto RTS */ - bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL); + bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);

/* Wait for the line to clear up. We cannot rely on UART * registers as none of them reflect the status of the RSR. @@ -64,7 +64,7 @@ static inline void serial_init(void) #endif

if (BFIN_DEBUG_EARLY_SERIAL) { - int ucen = *pUART_GCTL & UCEN; + int ucen = bfin_read16(&pUART->gctl) & UCEN; serial_early_init();

#ifndef CONFIG_BAUDRATE @@ -84,7 +84,7 @@ static inline void serial_deinit(void) #ifdef __ADSPBF54x__ if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { /* clear forced RTS rather than relying on auto RTS */ - bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL); + bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); } #endif } @@ -98,9 +98,9 @@ static inline void serial_putc(char c) if (c == '\n') serial_putc('\r');

- *pUART_THR = c; + bfin_write16(&pUART->thr, c);

- while (!(*pUART_LSR & TEMT)) + while (!(bfin_read16(&pUART->lsr) & TEMT)) continue; }

diff --git a/cpu/blackfin/interrupts.c b/cpu/blackfin/interrupts.c index 921bfe0..54a67b4 100644 --- a/cpu/blackfin/interrupts.c +++ b/cpu/blackfin/interrupts.c @@ -97,12 +97,12 @@ void __udelay(unsigned long usec) #define MAX_TIM_LOAD 0xFFFFFFFF int timer_init(void) { - *pTCNTL = 0x1; + bfin_write_TCNTL(0x1); CSYNC(); - *pTSCALE = 0x0; - *pTCOUNT = MAX_TIM_LOAD; - *pTPERIOD = MAX_TIM_LOAD; - *pTCNTL = 0x7; + bfin_write_TSCALE(0x0); + bfin_write_TCOUNT(MAX_TIM_LOAD); + bfin_write_TPERIOD(MAX_TIM_LOAD); + bfin_write_TCNTL(0x7); CSYNC();

timestamp = 0; @@ -130,7 +130,7 @@ ulong get_timer(ulong base) ulong milisec;

/* Number of clocks elapsed */ - ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT)); + ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT());

/* * Find if the TCOUNT is reset diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 2abda18..db12a5a 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -44,10 +44,6 @@

#ifdef CONFIG_UART_CONSOLE

-#if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0) -# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART -#endif - #include "serial.h"

#ifdef CONFIG_DEBUG_SERIAL @@ -63,7 +59,7 @@ size_t cache_count; static uint16_t uart_lsr_save; static uint16_t uart_lsr_read(void) { - uint16_t lsr = *pUART_LSR; + uint16_t lsr = bfin_read16(&pUART->lsr); uart_lsr_save |= (lsr & (OE|PE|FE|BI)); return lsr | uart_lsr_save; } @@ -71,15 +67,15 @@ static uint16_t uart_lsr_read(void) static void uart_lsr_clear(void) { uart_lsr_save = 0; - *pUART_LSR |= -1; + bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); } #else /* When debugging is disabled, we only care about the DR bit, so if other * bits get set/cleared, we don't really care since we don't read them * anyways (and thus anomaly 05000099 is irrelevant). */ -static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; } -static inline void uart_lsr_clear(void) { *pUART_LSR = -1; } +static uint16_t uart_lsr_read(void) { return bfin_read16(&pUART->lsr); } +static void uart_lsr_clear(void) { bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); } #endif

/* Symbol for our assembly to call. */ @@ -130,7 +126,7 @@ void serial_putc(const char c) continue;

/* queue the character for transmission */ - *pUART_THR = c; + bfin_write16(&pUART->thr, c); SSYNC();

WATCHDOG_RESET(); @@ -151,7 +147,7 @@ int serial_getc(void) continue;

/* grab the new byte */ - uart_rbr_val = *pUART_RBR; + uart_rbr_val = bfin_read16(&pUART->rbr);

#ifdef CONFIG_DEBUG_SERIAL /* grab & clear the LSR */ @@ -165,8 +161,8 @@ int serial_getc(void) uint16_t dll, dlh; printf("\n[SERIAL ERROR]\n"); ACCESS_LATCH(); - dll = *pUART_DLL; - dlh = *pUART_DLH; + dll = bfin_read16(&pUART->dll); + dlh = bfin_read16(&pUART->dlh); ACCESS_PORT_IER(); printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh); do { diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index 6cbc564..8aa9cca 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -24,71 +24,78 @@ # define BFIN_DEBUG_EARLY_SERIAL 0 #endif

+#ifndef __ASSEMBLY__ + #define LOB(x) ((x) & 0xFF) #define HIB(x) (((x) >> 8) & 0xFF)

+/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m +struct bfin_mmr_serial { +#ifdef __ADSPBF54x__ + __BFP(dll); + __BFP(dlh); + __BFP(gctl); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + __BFP(ier_set); + __BFP(ier_clear); + __BFP(thr); + __BFP(rbr); +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __spad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __spad1; + const __BFP(iir); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + const u32 __spad2; + __BFP(gctl); +#endif +}; +#undef __BFP + #ifndef UART_LSR # if (CONFIG_UART_CONSOLE == 3) -# define pUART_DLH pUART3_DLH -# define pUART_DLL pUART3_DLL -# define pUART_GCTL pUART3_GCTL -# define pUART_IER pUART3_IER -# define pUART_IERC pUART3_IER_CLEAR -# define pUART_LCR pUART3_LCR -# define pUART_LSR pUART3_LSR -# define pUART_RBR pUART3_RBR -# define pUART_THR pUART3_THR -# define UART_THR UART3_THR -# define UART_LSR UART3_LSR +# define UART_BASE UART3_DLL # elif (CONFIG_UART_CONSOLE == 2) -# define pUART_DLH pUART2_DLH -# define pUART_DLL pUART2_DLL -# define pUART_GCTL pUART2_GCTL -# define pUART_IER pUART2_IER -# define pUART_IERC pUART2_IER_CLEAR -# define pUART_LCR pUART2_LCR -# define pUART_LSR pUART2_LSR -# define pUART_RBR pUART2_RBR -# define pUART_THR pUART2_THR -# define UART_THR UART2_THR -# define UART_LSR UART2_LSR +# define UART_BASE UART2_DLL # elif (CONFIG_UART_CONSOLE == 1) -# define pUART_DLH pUART1_DLH -# define pUART_DLL pUART1_DLL -# define pUART_GCTL pUART1_GCTL -# define pUART_IER pUART1_IER -# define pUART_IERC pUART1_IER_CLEAR -# define pUART_LCR pUART1_LCR -# define pUART_LSR pUART1_LSR -# define pUART_RBR pUART1_RBR -# define pUART_THR pUART1_THR -# define UART_THR UART1_THR -# define UART_LSR UART1_LSR +# define UART_BASE UART1_DLL # elif (CONFIG_UART_CONSOLE == 0) -# define pUART_DLH pUART0_DLH -# define pUART_DLL pUART0_DLL -# define pUART_GCTL pUART0_GCTL -# define pUART_IER pUART0_IER -# define pUART_IERC pUART0_IER_CLEAR -# define pUART_LCR pUART0_LCR -# define pUART_LSR pUART0_LSR -# define pUART_RBR pUART0_RBR -# define pUART_THR pUART0_THR -# define UART_THR UART0_THR -# define UART_LSR UART0_LSR +# define UART_BASE UART0_DLL +# endif +#else +# if CONFIG_UART_CONSOLE != 0 +# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART # endif +# define UART_BASE UART_DLL #endif - -#ifndef __ASSEMBLY__ +#define pUART ((volatile struct bfin_mmr_serial *)UART_BASE)

#ifdef __ADSPBF54x__ # define ACCESS_LATCH() # define ACCESS_PORT_IER() -# define CLEAR_IER() (*pUART_IERC = 0) #else -# define ACCESS_LATCH() (*pUART_LCR |= DLAB) -# define ACCESS_PORT_IER() (*pUART_LCR &= ~DLAB) -# define CLEAR_IER() (*pUART_IER = 0) +# define ACCESS_LATCH() bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB) +# define ACCESS_PORT_IER() bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB) #endif

__attribute__((always_inline)) @@ -142,10 +149,10 @@ static inline void serial_early_init(void) serial_do_portmux();

/* always enable UART -- avoids anomalies 05000309 and 05000350 */ - *pUART_GCTL = UCEN; + bfin_write16(&pUART->gctl, UCEN);

/* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = WLS_8; + bfin_write16(&pUART->lcr, WLS_8);

SSYNC(); } @@ -158,8 +165,8 @@ static inline void serial_early_put_div(uint16_t divisor) SSYNC();

/* Program the divisor to get the baud rate we want */ - *pUART_DLL = LOB(divisor); - *pUART_DLH = HIB(divisor); + bfin_write16(&pUART->dll, LOB(divisor)); + bfin_write16(&pUART->dlh, HIB(divisor)); SSYNC();

/* Clear DLAB in LCR to Access THR RBR IER */ @@ -174,8 +181,8 @@ static inline uint16_t serial_early_get_div(void) ACCESS_LATCH(); SSYNC();

- uint8_t dll = *pUART_DLL; - uint8_t dlh = *pUART_DLH; + uint8_t dll = bfin_read16(&pUART->dll); + uint8_t dlh = bfin_read16(&pUART->dlh); uint16_t divisor = (dlh << 8) | dll;

/* Clear DLAB in LCR to Access THR RBR IER */ diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index 308014a..3fd34b3 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -61,7 +61,7 @@ extern u_long get_vco(void); extern u_long get_cclk(void); extern u_long get_sclk(void);

-# define bfin_revid() (*pCHIPID >> 28) +# define bfin_revid() (bfin_read_CHIPID() >> 28)

extern bool bfin_os_log_check(void); extern void bfin_os_log_dump(void);

Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/asm-blackfin/string.h | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index 18306dd..117f44c 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -29,9 +29,6 @@

#ifdef __KERNEL__ /* only set these up for kernel code */

-#include <config.h> -#include <asm/blackfin.h> - #define __HAVE_ARCH_STRCPY #define __HAVE_ARCH_STRNCPY #define __HAVE_ARCH_STRCMP @@ -47,7 +44,7 @@ extern int strcmp(const char *cs, const char *ct); extern int strncmp(const char *cs, const char *ct, size_t count); extern void *memcpy(void *dest, const void *src, size_t count); extern void *memset(void *s, int c, size_t count); -extern int memcmp(const void *, const void *, __kernel_size_t); +extern int memcmp(const void *, const void *, size_t); extern void *memmove(void *dest, const void *src, size_t count);

#else /* KERNEL */

From: Cliff Cai cliff.cai@analog.com

Signed-off-by: Cliff Cai cliff.cai@analog.com Signed-off-by: Mike Frysinger vapier@gentoo.org CC: Andy Fleming afleming@freescale.com --- board/bf518f-ezbrd/bf518f-ezbrd.c | 8 + board/bf548-ezkit/bf548-ezkit.c | 8 + drivers/mmc/bfin_sdh.c | 519 +++++++++---------------------------- drivers/mmc/bfin_sdh.h | 59 ----- include/asm-blackfin/mmc.h | 1 - include/asm-blackfin/sdh.h | 17 ++ include/configs/bf518f-ezbrd.h | 1 + include/configs/bf548-ezkit.h | 1 + lib_blackfin/board.c | 6 + 9 files changed, 161 insertions(+), 459 deletions(-) delete mode 100644 drivers/mmc/bfin_sdh.h delete mode 100644 include/asm-blackfin/mmc.h create mode 100644 include/asm-blackfin/sdh.h

diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 279c55c..85b350f 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -15,6 +15,7 @@ #include <asm/blackfin.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> +#include <asm/sdh.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -155,3 +156,10 @@ int board_early_init_f(void) #endif return 0; } + +#ifdef CONFIG_BFIN_SDH +int board_mmc_init(bd_t *bis) +{ + return bfin_mmc_init(bis); +} +#endif diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 29c2e92..7659e34 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -11,6 +11,7 @@ #include <config.h> #include <command.h> #include <asm/blackfin.h> +#include <asm/sdh.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -78,3 +79,10 @@ int board_eth_init(bd_t *bis) return smc911x_initialize(0, CONFIG_SMC911X_BASE); } #endif + +#ifdef CONFIG_BFIN_SDH +int board_mmc_init(bd_t *bis) +{ + return bfin_mmc_init(bis); +} +#endif diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 16c9695..f9d560a 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -1,7 +1,7 @@ /* * Driver for Blackfin on-chip SDH controller * - * Copyright (c) 2008 Analog Devices Inc. + * Copyright (c) 2008-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -18,20 +18,6 @@ #include <asm/mach-common/bits/sdh.h> #include <asm/mach-common/bits/dma.h>

-#include "bfin_sdh.h" - -/* SD_CLK frequency must be less than 400k in identification mode */ -#ifndef CONFIG_SYS_MMC_CLK_ID -#define CONFIG_SYS_MMC_CLK_ID 200000 -#endif -/* SD_CLK for normal working */ -#ifndef CONFIG_SYS_MMC_CLK_OP -#define CONFIG_SYS_MMC_CLK_OP 25000000 -#endif -/* support 3.2-3.3V and 3.3-3.4V */ -#define CONFIG_SYS_MMC_OP_COND 0x00300000 -#define MMC_DEFAULT_RCA 1 - #if defined(__ADSPBF51x__) # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL @@ -64,61 +50,17 @@ # error no support for this proc yet #endif

-static unsigned int mmc_rca; -static int mmc_card_is_sd; -static block_dev_desc_t mmc_blkdev; -struct mmc_cid cid; -static __u32 csd[4]; - -#define get_bits(resp, start, size) \ - ({ \ - const int __size = size; \ - const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \ - const int32_t __off = 3 - ((start) / 32); \ - const int32_t __shft = (start) & 31; \ - uint32_t __res; \ - \ - __res = resp[__off] >> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off-1] << ((32 - __shft) % 32); \ - __res & __mask; \ - }) - - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return &mmc_blkdev; -} - -static void mci_set_clk(unsigned long clk) -{ - unsigned long sys_clk; - unsigned long clk_div; - __u16 clk_ctl = 0; - - /* setting SD_CLK */ - sys_clk = get_sclk(); - bfin_write_SDH_CLK_CTL(0); - if (sys_clk % (2 * clk) == 0) - clk_div = sys_clk / (2 * clk) - 1; - else - clk_div = sys_clk / (2 * clk); - - if (clk_div > 0xff) - clk_div = 0xff; - clk_ctl |= (clk_div & 0xff); - clk_ctl |= CLK_E; - bfin_write_SDH_CLK_CTL(clk_ctl); -} - static int -mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) +sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { unsigned int sdh_cmd; unsigned int status; + int cmd = mmc_cmd->cmdidx; + int flags = mmc_cmd->resp_type; + int arg = mmc_cmd->cmdarg; int ret = 0; sdh_cmd = 0; - unsigned long *response = resp; + sdh_cmd |= cmd;

if (flags & MMC_RSP_PRESENT) @@ -138,336 +80,137 @@ mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) CMD_CRC_FAIL)));

if (flags & MMC_RSP_PRESENT) { - response[0] = bfin_read_SDH_RESPONSE0(); + mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0(); if (flags & MMC_RSP_136) { - response[1] = bfin_read_SDH_RESPONSE1(); - response[2] = bfin_read_SDH_RESPONSE2(); - response[3] = bfin_read_SDH_RESPONSE3(); + mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1(); + mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2(); + mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3(); } }

- if (status & CMD_TIME_OUT) { - printf("CMD%d timeout\n", (int)cmd); - ret |= -ETIMEDOUT; - } else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) { - printf("CMD%d CRC failure\n", (int)cmd); - ret |= -EILSEQ; - } + if (status & CMD_TIME_OUT) + ret |= TIMEOUT; + else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) + ret |= COMM_ERR; + bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT); return ret; }

-static int -mmc_acmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) +/* set data for single block transfer */ +static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) { - unsigned long aresp[4]; + u16 data_ctl = 0; + u16 dma_cfg = 0; int ret = 0;

- ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, - MMC_RSP_PRESENT); - if (ret) - return ret; - - if ((aresp[0] & (ILLEGAL_COMMAND | APP_CMD)) != APP_CMD) - return -ENODEV; - ret = mmc_cmd(cmd, arg, resp, flags); - return ret; -} - -static unsigned long -mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, void *buffer) -{ - int ret, i; - unsigned long resp[4]; - unsigned long card_status; - __u8 *buf = buffer; - __u32 status; - __u16 data_ctl = 0; - __u16 dma_cfg = 0; - - if (blkcnt == 0) - return 0; - debug("mmc_bread: dev %d, start %d, blkcnt %d\n", dev, start, blkcnt); - /* Force to use 512-byte block,because a lot of code depends on this */ - data_ctl |= 9 << 4; + /* Don't support write yet. */ + if (data->flags & MMC_DATA_WRITE) + return UNUSABLE_ERR; + data_ctl |= ((ffs(data->blocksize) - 1) << 4); data_ctl |= DTX_DIR; bfin_write_SDH_DATA_CTL(data_ctl); - dma_cfg |= WDSIZE_32 | RESTART | WNR | DMAEN; - - /* FIXME later */ - bfin_write_SDH_DATA_TIMER(0xFFFFFFFF); - for (i = 0; i < blkcnt; ++i, ++start) { - blackfin_dcache_flush_invalidate_range(buf + i * mmc_blkdev.blksz, - buf + (i + 1) * mmc_blkdev.blksz); - bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz); - bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4); - bfin_write_DMA_X_MODIFY(4); - bfin_write_DMA_CONFIG(dma_cfg); - bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz); - /* Put the device into Transfer state */ - ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SELECT_CARD failed\n"); - goto out; - } - /* Set block length */ - ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SET_BLOCKLEN failed\n"); - goto out; - } - ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, - start * mmc_blkdev.blksz, resp, - MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_READ_SINGLE_BLOCK failed\n"); - goto out; - } - bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); + dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;

- do { - udelay(1); - status = bfin_read_SDH_STATUS(); - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN))); - - if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)) { - bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT | \ - DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); - goto read_error; - } else { - bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); - mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0); - } - } - out: + bfin_write_SDH_DATA_TIMER(0xFFFF);

- return i; + blackfin_dcache_flush_invalidate_range(data->dest, + data->dest + data->blocksize); + /* configure DMA */ + bfin_write_DMA_START_ADDR(data->dest); + bfin_write_DMA_X_COUNT(data->blocksize / 4); + bfin_write_DMA_X_MODIFY(4); + bfin_write_DMA_CONFIG(dma_cfg); + bfin_write_SDH_DATA_LGTH(data->blocksize); + /* kick off transfer */ + bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);

- read_error: - mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1); - printf("mmc: bread failed, status = %08x, card status = %08lx\n", - status, card_status); - goto out; + return ret; }

-static unsigned long -mmc_bwrite(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer) + +static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) { - int ret, i = 0; - unsigned long resp[4]; - unsigned long card_status; - const __u8 *buf = buffer; - __u32 status; - __u16 data_ctl = 0; - __u16 dma_cfg = 0; - - if (blkcnt == 0) - return 0; - - debug("mmc_bwrite: dev %d, start %lx, blkcnt %lx\n", - dev, start, blkcnt); - /* Force to use 512-byte block,because a lot of code depends on this */ - data_ctl |= 9 << 4; - data_ctl &= ~DTX_DIR; - bfin_write_SDH_DATA_CTL(data_ctl); - dma_cfg |= WDSIZE_32 | RESTART | DMAEN; - /* FIXME later */ - bfin_write_SDH_DATA_TIMER(0xFFFFFFFF); - for (i = 0; i < blkcnt; ++i, ++start) { - bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz); - bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4); - bfin_write_DMA_X_MODIFY(4); - bfin_write_DMA_CONFIG(dma_cfg); - bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz); - - /* Put the device into Transfer state */ - ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SELECT_CARD failed\n"); - goto out; - } - /* Set block length */ - ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_SET_BLOCKLEN failed\n"); - goto out; - } - ret = mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, - start * mmc_blkdev.blksz, resp, - MMC_RSP_R1); - if (ret) { - printf("MMC_CMD_WRITE_SINGLE_BLOCK failed\n"); - goto out; - } - bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); + u32 status; + int ret = 0;

+ ret = sdh_send_cmd(mmc, cmd); + if (ret) { + printf("sending CMD%d failed\n", cmd->cmdidx); + return ret; + } + if (data) { + ret = sdh_setup_data(mmc, data); do { udelay(1); status = bfin_read_SDH_STATUS(); - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN))); + } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));

- if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN)) { - bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT | - DAT_CRC_FAIL_STAT | TX_UNDERRUN_STAT); - goto write_error; - } else { + if (status & DAT_TIME_OUT) { + bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); + ret |= TIMEOUT; + } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) { + bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); + ret |= COMM_ERR; + } else bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); - mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0); + + if (ret) { + printf("tranfering data failed\n"); + return ret; } } - out: - return i; - - write_error: - mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1); - printf("mmc: bwrite failed, status = %08x, card status = %08lx\n", - status, card_status); - goto out; -} - -static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) -{ - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = resp[2] >> 24; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 16; - cid->psn = (resp[2] << 16) | (resp[3] >> 16); - cid->mdt = resp[3] >> 8; -} - -static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) -{ - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = 0; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 24; - cid->psn = (resp[2] << 8) | (resp[3] >> 24); - cid->mdt = (resp[3] >> 8) & 0x0fff; -} - -static void mmc_dump_cid(const struct mmc_cid *cid) -{ - printf("CID information:\n"); - printf("Manufacturer ID: %02X\n", cid->mid); - printf("OEM/Application ID: %04X\n", cid->oid); - printf("Product name: %s\n", cid->pnm); - printf("Product Revision: %u.%u\n", - cid->prv >> 4, cid->prv & 0x0f); - printf("Product Serial Number: %lu\n", cid->psn); - printf("Manufacturing Date: %02u/%02u\n", - cid->mdt >> 4, cid->mdt & 0x0f); -} - -static void mmc_dump_csd(__u32 *csd) -{ - printf("CSD information:\n"); - printf("CSD structure version: 1.%u\n", get_bits(csd, 126, 2)); - printf("Card command classes: %03x\n", get_bits(csd, 84, 12)); - printf("Max trans speed: %s\n", (get_bits(csd, 96, 8) == 0x32) ? "25MHz" : "50MHz"); - printf("Read block length: %d\n", 1 << get_bits(csd, 80, 4)); - printf("Write block length: %u\n", 1 << get_bits(csd, 22, 4)); - printf("Card capacity: %u bytes\n", - (get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2)) * - (1 << get_bits(csd, 80, 4))); - putc('\n'); + return 0; }

-static int mmc_idle_cards(void) +static void sdh_set_clk(unsigned long clk) { - int ret = 0; - - /* Reset all cards */ - ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); - if (ret) - return ret; - udelay(500); - return mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); + unsigned long sys_clk; + unsigned long clk_div; + u16 clk_ctl = 0; + + clk_ctl = bfin_read_SDH_CLK_CTL(); + if (clk) { + /* setting SD_CLK */ + sys_clk = get_sclk(); + bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); + if (sys_clk % (2 * clk) == 0) + clk_div = sys_clk / (2 * clk) - 1; + else + clk_div = sys_clk / (2 * clk); + + if (clk_div > 0xff) + clk_div = 0xff; + clk_ctl |= (clk_div & 0xff); + clk_ctl |= CLK_E; + bfin_write_SDH_CLK_CTL(clk_ctl); + } else + bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); }

-static int sd_init_card(struct mmc_cid *cid, int verbose) +static void bfin_sdh_set_ios(struct mmc *mmc) { - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; ++i) { - ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, - resp, MMC_RSP_R3); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; + u16 cfg = 0; + u16 clk_ctl = 0; + + if (mmc->bus_width == 4) { + cfg = bfin_read_SDH_CFG(); + cfg &= ~0x80; + cfg |= 0x40; + bfin_write_SDH_CFG(cfg); + clk_ctl |= WIDE_BUS; } - if (ret) - return ret; - - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2); - if (ret) - return ret; - sd_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); - - /* Get RCA of the card that responded */ - ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, MMC_RSP_R6); - if (ret) - return ret; - - mmc_rca = (resp[0] >> 16) & 0xffff; - if (verbose) - printf("SD Card detected (RCA %u)\n", mmc_rca); - mmc_card_is_sd = 1; - return 0; + bfin_write_SDH_CLK_CTL(clk_ctl); + sdh_set_clk(mmc->clock); }

-static int mmc_init_card(struct mmc_cid *cid, int verbose) +static int bfin_sdh_init(struct mmc *mmc) { - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; ++i) { - ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp, - MMC_RSP_R3); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; - } - if (ret) - return ret;

- /* Get CID of all cards. FIXME: Support more than one card */ - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2); - if (ret) - return ret; - mmc_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); - - /* Set Relative Address of the card that responded */ - ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, - MMC_RSP_R1); - return ret; -} - -int mmc_legacy_init(int verbose) -{ - __u16 pwr_ctl = 0; - int ret; - unsigned int max_blksz; - /* Initialize sdh controller */ + u16 pwr_ctl = 0; +/* Initialize sdh controller */ #if defined(__ADSPBF54x__) bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00); @@ -481,56 +224,34 @@ int mmc_legacy_init(int verbose) bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); /* Disable card detect pin */ bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60); - mci_set_clk(CONFIG_SYS_MMC_CLK_ID); - /* setting power control */ + pwr_ctl |= ROD_CTL; pwr_ctl |= PWR_ON; bfin_write_SDH_PWR_CTL(pwr_ctl); - mmc_card_is_sd = 0; - ret = sd_init_card(&cid, verbose); - if (ret) { - mmc_rca = MMC_DEFAULT_RCA; - ret = mmc_init_card(&cid, verbose); - } - if (ret) - return ret; - /* Get CSD from the card */ - ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, csd, MMC_RSP_R2); - if (ret) - return ret; - if (verbose) - mmc_dump_csd(csd); - /* Initialize the blockdev structure */ - mmc_blkdev.if_type = IF_TYPE_MMC; - mmc_blkdev.part_type = PART_TYPE_DOS; - mmc_blkdev.block_read = mmc_bread; - mmc_blkdev.block_write = mmc_bwrite; - sprintf(mmc_blkdev.vendor, - "Man %02x%04x Snr %08lx", - cid.mid, cid.oid, cid.psn); - strncpy(mmc_blkdev.product, cid.pnm, - sizeof(mmc_blkdev.product)); - sprintf(mmc_blkdev.revision, "%x %x", - cid.prv >> 4, cid.prv & 0x0f); - - max_blksz = 1 << get_bits(csd, 80, 4); - /* - * If we can't use 512 byte blocks, refuse to deal with the - * card. Tons of code elsewhere seems to depend on this. - */ - if (max_blksz < 512 || (max_blksz > 512 && !get_bits(csd, 79, 1))) { - printf("Card does not support 512 byte reads, aborting.\n"); - return -ENODEV; - } - - mmc_blkdev.blksz = 512; - mmc_blkdev.lba = (get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2)); - mci_set_clk(CONFIG_SYS_MMC_CLK_OP); - init_part(&mmc_blkdev); return 0; }

-int mmc2info(ulong addr) + +int bfin_mmc_init(bd_t *bis) { + struct mmc *mmc = NULL; + + mmc = malloc(sizeof(struct mmc)); + + if (!mmc) + return -ENOMEM; + sprintf(mmc->name, "Blackfin SDH"); + mmc->send_cmd = bfin_sdh_request; + mmc->set_ios = bfin_sdh_set_ios; + mmc->init = bfin_sdh_init; + mmc->host_caps = MMC_MODE_4BIT; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->f_max = get_sclk(); + mmc->f_min = mmc->f_max >> 9; + mmc->block_dev.part_type = PART_TYPE_DOS; + + mmc_register(mmc); + return 0; } diff --git a/drivers/mmc/bfin_sdh.h b/drivers/mmc/bfin_sdh.h deleted file mode 100644 index 793ec30..0000000 --- a/drivers/mmc/bfin_sdh.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2008 Analog Device Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __BLACKFIN_SDH_H__ -#define __BLACKFIN_SDH_H__ - -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ - -#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ -#define MMC_CMD_AC (0 << 5) -#define MMC_CMD_ADTC (1 << 5) -#define MMC_CMD_BC (2 << 5) -#define MMC_CMD_BCR (3 << 5) - -#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ -#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ -#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ -#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ - -/* - * These are the native response types, and correspond to valid bit - * patterns of the above flags. One additional valid pattern - * is all zeros, which means we don't expect a response. - */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define ILLEGAL_COMMAND (1 << 22) -#define APP_CMD (1 << 5) - -#endif diff --git a/include/asm-blackfin/mmc.h b/include/asm-blackfin/mmc.h deleted file mode 100644 index aa2ac95..0000000 --- a/include/asm-blackfin/mmc.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-avr32/arch-at32ap700x/mmc.h> diff --git a/include/asm-blackfin/sdh.h b/include/asm-blackfin/sdh.h new file mode 100644 index 0000000..2c2f63e --- /dev/null +++ b/include/asm-blackfin/sdh.h @@ -0,0 +1,17 @@ +/* + * sdh.h, export bfin_mmc_init + * + * Copyright (c) 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_SDH_H__ +#define __ASM_SDH_H__ + +#include <mmc.h> +#include <asm/u-boot.h> + +int bfin_mmc_init(bd_t *bis); + +#endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 4928403..234e5a4 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -125,6 +125,7 @@ * SDH Settings */ #if !defined(__ADSPBF512__) +#define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_BFIN_SDH #endif diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 297c3fd..f9c9711 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -161,6 +161,7 @@ * SDH Settings */ #if !defined(__ADSPBF544__) +#define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_BFIN_SDH #endif diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index b682beb..4c66cf0 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -14,6 +14,7 @@ #include <stdio_dev.h> #include <environment.h> #include <malloc.h> +#include <mmc.h> #include <net.h> #include <timestamp.h> #include <status_led.h> @@ -335,6 +336,11 @@ void board_init_r(gd_t * id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif

+#ifdef CONFIG_GENERIC_MMC + puts("MMC: "); + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ env_relocate();

Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/asm-blackfin/io.h | 38 -------------------------------------- 1 files changed, 0 insertions(+), 38 deletions(-)

diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 6806494..354fb7d 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -147,43 +147,5 @@ static inline unsigned int readl(const volatile void *addr)

#define outsw(port, addr, count) cf_outsw((unsigned short *)(port), (unsigned short *)addr, (count))

-#define IO_SPACE_LIMIT 0xffff - -/* Values for nocacheflag and cmode */ -#define IOMAP_FULL_CACHING 0 -#define IOMAP_NOCACHE_SER 1 -#define IOMAP_NOCACHE_NONSER 2 -#define IOMAP_WRITETHROUGH 3 - -extern void *__ioremap(unsigned long physaddr, unsigned long size, - int cacheflag); -extern void __iounmap(void *addr, unsigned long size); - -extern inline void *ioremap(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -extern inline void *ioremap_writethrough(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); -} -extern inline void *ioremap_fullcache(unsigned long physaddr, - unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_FULL_CACHING); -} - -extern void iounmap(void *addr); - -extern void blkfin_inv_cache_all(void); -#define dma_cache_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) -#define dma_cache_wback(_start, _size) do { } while (0) -#define dma_cache_wback_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) - #endif #endif

From: Cliff Cai cliff.cai@analog.com

Signed-off-by: Cliff Cai cliff.cai@analog.com Signed-off-by: Mike Frysinger vapier@gentoo.org --- board/bf527-ezkit/bf527-ezkit.c | 13 +++++++++++++ board/bf548-ezkit/bf548-ezkit.c | 16 ++++++++++++++++ 2 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index a880066..a911880 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -68,3 +68,16 @@ int misc_init_r(void)

return 0; } + +#ifdef CONFIG_USB_BLACKFIN +void board_musb_init(void) +{ + /* + * BF527 EZ-KITs require PG13 to be high for HOST mode + */ + bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13); + bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13); + bfin_write_PORTGIO_SET(PG13); + SSYNC(); +} +#endif diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 7659e34..65fb81a 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -86,3 +86,19 @@ int board_mmc_init(bd_t *bis) return bfin_mmc_init(bis); } #endif + +#ifdef CONFIG_USB_BLACKFIN +void board_musb_init(void) +{ + /* + * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device + * and OTG host modes, while rev 1.1 and greater require PE7 to + * be low for device mode and high for host mode. We set it high + * here because we are in host mode. + */ + bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7); + bfin_write_PORTE_DIR_SET(PE7); + bfin_write_PORTE_SET(PE7); + SSYNC(); +} +#endif

From: Robin Getz robin.getz@analog.com

Signed-off-by: Robin Getz robin.getz@analog.com Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/configs/bfin_adi_common.h | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index db10ccc..f7a2d5c 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -178,7 +178,19 @@ "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" # endif +# ifdef CONFIG_NETCONSOLE +# define NETCONSOLE_ENV \ + "nc=" \ + "set ncip ${serverip};" \ + "set stdin nc;" \ + "set stdout nc" \ + "\0" +# else +# define NETCONSOLE_ENV +# endif # define NETWORK_ENV_SETTINGS \ + NETCONSOLE_ENV \ + \ "ubootfile=" UBOOT_ENV_FILE "\0" \ "update=" \ "tftp $(loadaddr) $(ubootfile);" \

From: Robin Getz robin.getz@analog.com

Need to reload the loop counters to keep from corrupting hardware loops.

Signed-off-by: Robin Getz robin.getz@analog.com Signed-off-by: Mike Frysinger vapier@gentoo.org --- cpu/blackfin/interrupt.S | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S index 71e0fc6..8c7a262 100644 --- a/cpu/blackfin/interrupt.S +++ b/cpu/blackfin/interrupt.S @@ -1,7 +1,7 @@ /* * interrupt.S - trampoline default exceptions/interrupts to C handlers * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2009 Analog Devices Inc. * Licensed under the GPL-2 or later. */

@@ -17,10 +17,19 @@ ENTRY(_trap) sp.l = LO(L1_SRAM_SCRATCH_END - 20); sp.h = HI(L1_SRAM_SCRATCH_END - 20); SAVE_ALL_SYS + r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ sp += -12; call _trap_c; sp += 12; + +#if ANOMALY_05000257 + R7 = LC0; + LC0 = R7; + R7 = LC1; + LC1 = R7; +#endif + RESTORE_ALL_SYS sp = CONFIG_BFIN_SCRATCH_REG; rtx;