[U-Boot] [PATCH] ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25 +++++++++++++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 2f935a21e9..a428922f8e 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -55,6 +55,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges; + u-boot,dm-pre-reloc;
amba { compatible = "simple-bus"; @@ -93,29 +94,35 @@ clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; + u-boot,dm-pre-reloc;
clocks { #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc;
cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; };
cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; };
f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; };
osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; };
main_pll: main_pll@40 { @@ -126,6 +133,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_clk>; reg = <0x40>; + u-boot,dm-pre-reloc;
main_mpu_base_clk: main_mpu_base_clk { #clock-cells = <0>; @@ -214,6 +222,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_clk>, <&main_periph_ref_clk>; reg = <0xC0>; + u-boot,dm-pre-reloc;
peri_mpu_base_clk: peri_mpu_base_clk { #clock-cells = <0>; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 3f59f02577..ae54de6990 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -166,3 +166,28 @@ &watchdog1 { status = "okay"; }; + +/* Clock available early */ +&main_noc_base_clk { + u-boot,dm-pre-reloc; +}; + +&main_periph_ref_clk { + u-boot,dm-pre-reloc; +}; + +&peri_noc_base_clk { + u-boot,dm-pre-reloc; +}; + +&noc_free_clk { + u-boot,dm-pre-reloc; +}; + +&l4_mp_clk { + u-boot,dm-pre-reloc; +}; + +&l4_sp_clk { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 9c6070ded9..998d811210 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -38,3 +38,20 @@ <48 IRQ_TYPE_LEVEL_HIGH>; }; }; + +/* Clock available early */ +&main_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&peri_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_free_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk { + u-boot,dm-pre-reloc; +};
On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25 +++++++++++++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 2f935a21e9..a428922f8e 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -55,6 +55,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges;
u-boot,dm-pre-reloc;amba { compatible = "simple-bus"; @@ -93,29 +94,35 @@ clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>;
u-boot,dm-pre-reloc;clocks { #address-cells = <1>; #size-cells = <0>;
u-boot,dm-pre-reloc;cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; osc1: osc1 { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; main_pll: main_pll@40 { @@ -126,6 +133,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_ clk>; reg = <0x40>;
u-boot,dm-pre-reloc;main_mpu_base_clk: main_mpu_base_clk { #clock-cells = <0>; @@ -214,6 +222,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_ clk>, <&main_periph_ref_clk>; reg = <0xC0>;
u-boot,dm-pre-reloc;peri_mpu_base_clk: peri_mpu_base_clk { #clock-cells = <0>; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 3f59f02577..ae54de6990 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -166,3 +166,28 @@ &watchdog1 { status = "okay"; };
+/* Clock available early */ +&main_noc_base_clk {
- u-boot,dm-pre-reloc;
+};
+&main_periph_ref_clk {
- u-boot,dm-pre-reloc;
+};
+&peri_noc_base_clk {
- u-boot,dm-pre-reloc;
+};
+&noc_free_clk {
- u-boot,dm-pre-reloc;
+};
+&l4_mp_clk {
- u-boot,dm-pre-reloc;
+};
+&l4_sp_clk {
- u-boot,dm-pre-reloc;
+};
Why don't add these to socfpga_arria10.dtsi?
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 9c6070ded9..998d811210 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -38,3 +38,20 @@ <48 IRQ_TYPE_LEVEL_HIGH>; }; };
+/* Clock available early */ +&main_sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&peri_sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_free_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
Same these too.
Regards Ley Foon
On 08/09/2018 10:12 AM, Ley Foon Tan wrote:
On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25 +++++++++++++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 2f935a21e9..a428922f8e 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -55,6 +55,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges;
u-boot,dm-pre-reloc;amba { compatible = "simple-bus"; @@ -93,29 +94,35 @@ clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>;
u-boot,dm-pre-reloc;clocks { #address-cells = <1>; #size-cells = <0>;
u-boot,dm-pre-reloc;cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; osc1: osc1 { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc;}; main_pll: main_pll@40 { @@ -126,6 +133,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_ clk>; reg = <0x40>;
u-boot,dm-pre-reloc;main_mpu_base_clk: main_mpu_base_clk { #clock-cells = <0>; @@ -214,6 +222,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_ clk>, <&main_periph_ref_clk>; reg = <0xC0>;
u-boot,dm-pre-reloc;peri_mpu_base_clk: peri_mpu_base_clk { #clock-cells = <0>; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 3f59f02577..ae54de6990 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -166,3 +166,28 @@ &watchdog1 { status = "okay"; };
+/* Clock available early */ +&main_noc_base_clk {
- u-boot,dm-pre-reloc;
+};
+&main_periph_ref_clk {
- u-boot,dm-pre-reloc;
+};
+&peri_noc_base_clk {
- u-boot,dm-pre-reloc;
+};
+&noc_free_clk {
- u-boot,dm-pre-reloc;
+};
+&l4_mp_clk {
- u-boot,dm-pre-reloc;
+};
+&l4_sp_clk {
- u-boot,dm-pre-reloc;
+};
Why don't add these to socfpga_arria10.dtsi?
They're SoCDK specific and may not be needed on other platforms.
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 9c6070ded9..998d811210 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -38,3 +38,20 @@ <48 IRQ_TYPE_LEVEL_HIGH>; }; };
+/* Clock available early */ +&main_sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&peri_sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_free_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
Same these too.
They are specific to the setup booting from SDMMC.
On Thu, 2018-08-09 at 10:14 +0200, Marek Vasut wrote:
On 08/09/2018 10:12 AM, Ley Foon Tan wrote:
On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25 +++++++++++++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 2f935a21e9..a428922f8e 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -55,6 +55,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges;
u-boot,dm-pre-reloc;amba { compatible = "simple-bus"; @@ -93,29 +94,35 @@ clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>;
u-boot,dm-pre-reloc;clocks { #address-cells = <1>; #size-cells = <0>;
u-boot,dm-pre-reloc;cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc; }; cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc; }; f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc; }; osc1: osc1 { #clock-cells = <0>; compatible = "fixed- clock";
u-boot,dm-pre-reloc; }; main_pll: main_pll@40 { @@ -126,6 +133,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_f ree_ clk>; reg = <0x40>;
u-boot,dm-pre-reloc; main_mpu_base_cl k: main_mpu_base_clk { #clock- cells = <0>; @@ -214,6 +222,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_f ree_ clk>, <&main_periph_ref_clk>; reg = <0xC0>;
u-boot,dm-pre-reloc; peri_mpu_base_cl k: peri_mpu_base_clk { #clock- cells = <0>; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 3f59f02577..ae54de6990 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -166,3 +166,28 @@ &watchdog1 { status = "okay"; };
+/* Clock available early */ +&main_noc_base_clk {
- u-boot,dm-pre-reloc;
+};
+&main_periph_ref_clk {
- u-boot,dm-pre-reloc;
+};
+&peri_noc_base_clk {
- u-boot,dm-pre-reloc;
+};
+&noc_free_clk {
- u-boot,dm-pre-reloc;
+};
+&l4_mp_clk {
- u-boot,dm-pre-reloc;
+};
+&l4_sp_clk {
- u-boot,dm-pre-reloc;
+};
Why don't add these to socfpga_arria10.dtsi?
They're SoCDK specific and may not be needed on other platforms.
Okay.
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 9c6070ded9..998d811210 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -38,3 +38,20 @@ <48 IRQ_TYPE_LEVEL_HIGH>; }; };
+/* Clock available early */ +&main_sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&peri_sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_free_clk {
- u-boot,dm-pre-reloc;
+};
+&sdmmc_clk {
- u-boot,dm-pre-reloc;
+};
Same these too.
They are specific to the setup booting from SDMMC.
Okay.
Regards Ley Foon
participants (2)
-
Ley Foon Tan -
Marek Vasut