CONFIG_ENV_SIZE for NAND was later in this file overwritten because we have the environment in i2c eeprom, so remove this define.

Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com cc: Heiko Schocher hs@denx.de --- Changes for v3: - rebased Changes for v2: - nothing

include/configs/km/km_arm.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 29815be..619acf0 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -55,7 +55,6 @@ #include "asm/arch/config.h"

#define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */ -#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ @@ -208,7 +207,6 @@ int get_scl(void); #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_EEPROM_WREN #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ -#undef CONFIG_ENV_SIZE #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) #define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"

From: Valentin Longchamp valentin.longchamp@keymile.com

The phy is also configured with "RGMII clock transitions when data stable" and "Class A driver for the direct backplane connection".

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com cc: Heiko Schocher hs@denx.de --- Changes for v3: - rebased Changes for v2: - first version has also defines for portl2, they were removed because the board support for portl2 has moved to the end of the serie

board/keymile/km_arm/km_arm.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 files changed, 38 insertions(+), 1 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index d86acc9..ed6ede3 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -335,7 +335,42 @@ void dram_init_banksize(void) } }

-/* Configure and enable MV88E1118 PHY */ +#if defined(CONFIG_MGCOGE3UN) + +#define PHY_LED_SEL 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL 0x1c +#define PHY_RGMII_CLK_STABLE (0x1<<10) +#define PHY_CLSA (0x1<<1) + +/* Configure and enable MV88E3018 PHY */ +void reset_phy(void) +{ + char *name = "egiga0"; + unsigned short reg; + + if (miiphy_set_current_dev(name)) + return; + + /* RGMII clk transition on data stable */ + if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0) + printf("Error reading PHY spec ctrl reg\n"); + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + printf("Error writing PHY spec ctrl reg\n"); + + /* leds setup */ + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + printf("Error writing PHY LED reg\n"); + + /* reset the phy */ + miiphy_reset(name, CONFIG_PHY_BASE_ADR); +} +#else +/* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { char *name = "egiga0"; @@ -346,6 +381,8 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } +#endif +

#if defined(CONFIG_HUSH_INIT_VAR) int hush_init_var(void)

From: Valentin Longchamp valentin.longchamp@keymile.com

This adds support for the keymile Kirkwood BEC portl2 board. This board relies on the km_arm (km_kirkwood) BEC.

The egiga driver is configured for a 100M full-duplex, A/N off connnection to the backplane. This board has always ethernet present, because it is connected to the marvell switch similar to mgcoge3un. The reset_phy functionality is also the same to mgcoge3un.

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com cc: Heiko Schocher hs@denx.de --- Changes for v3: - rebase Changes for v2: - add this board support patch to the end of the serie

MAINTAINERS | 1 + MAKEALL | 1 + board/keymile/km_arm/km_arm.c | 8 +++-- boards.cfg | 1 + include/configs/portl2.h | 81 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 89 insertions(+), 3 deletions(-) create mode 100644 include/configs/portl2.h

diff --git a/MAINTAINERS b/MAINTAINERS index d1ec392..653c928 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -729,6 +729,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com

km_kirkwood ARM926EJS (Kirkwood SoC) + portl2 ARM926EJS (Kirkwood SoC)

Nishanth Menon nm@ti.com

diff --git a/MAKEALL b/MAKEALL index 1798303..3f92449 100755 --- a/MAKEALL +++ b/MAKEALL @@ -364,6 +364,7 @@ LIST_ARM9=" \ openrd_base \ openrd_client \ openrd_ultimate \ + portl2 \ rd6281a \ sbc2410x \ scb9328 \ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed6ede3..5da856f 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -130,10 +130,12 @@ int startup_allowed(void) return 1; return 0; } +#endif

+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) /* - * mgcoge3un has always ethernet present. Its connected to the 6061 switch - * and provides ICNev and piggy4 connections. + * These two boards have always ethernet present. Its connected to the mv + * switch. */ int ethernet_present(void) { @@ -335,7 +337,7 @@ void dram_init_banksize(void) } }

-#if defined(CONFIG_MGCOGE3UN) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))

#define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index 6a50236..649f1af 100644 --- a/boards.cfg +++ b/boards.cfg @@ -109,6 +109,7 @@ davinci_sonata arm arm926ejs sonata davinci km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood mgcoge3un arm arm926ejs km_arm keymile kirkwood +portl2 arm arm926ejs km_arm keymile kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE diff --git a/include/configs/portl2.h b/include/configs/portl2.h new file mode 100644 index 0000000..a8543a5 --- /dev/null +++ b/include/configs/portl2.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar prafulla@marvell.com + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2010-2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. + * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ + +#ifndef _CONFIG_PORTL2_H +#define _CONFIG_PORTL2_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km/km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile Port-L2" +#define CONFIG_HOSTNAME portl2 +#define CONFIG_PORTL2 + +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define KM_ENV_BUS "pca9544a:70:a" /* I2C2 (Mux-Port 2)*/ + +/* + * portl2 has a fixed link to the XMPP backplane + * with 100MB full duplex and autoneg off, for this + * reason we have to change the default settings + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) + +/* + * portl2 does use the PCIe Port0 + */ +#define CONFIG_KIRKWOOD_PCIE_INIT + +#endif /* _CONFIG_PORTL2_H */