In case of multiple eth interfaces currently eth_get_dev fetches the device based on the probe order which can be random hence try with the alias.

Signed-off-by: Keerthy j-keerthy@ti.com --- net/eth-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 031d558625..f11c307b8c 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -68,8 +68,8 @@ struct udevice *eth_get_dev(void)

uc_priv = eth_get_uclass_priv(); if (!uc_priv->current) - eth_errno = uclass_first_device(UCLASS_ETH, - &uc_priv->current); + eth_errno = uclass_get_device_by_seq(UCLASS_ETH, + 0, &uc_priv->current); return uc_priv->current; }

Introduce misc_init_by_ofnode to probe a misc device using its ofnode.

Signed-off-by: Keerthy j-keerthy@ti.com --- drivers/misc/misc-uclass.c | 25 +++++++++++++++++++++++++ include/misc.h | 9 +++++++++ 2 files changed, 34 insertions(+)

diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 55381edc98..835d3f7118 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -5,6 +5,8 @@

#include <common.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> #include <errno.h> #include <misc.h>

@@ -65,6 +67,29 @@ int misc_set_enabled(struct udevice *dev, bool val) return ops->set_enabled(dev, val); }

+int misc_init_by_ofnode(ofnode node) +{ + struct udevice *dev = NULL; + int ret; + long temp1, temp2; + + temp1 = ofnode_to_offset(node); + + for (ret = uclass_find_first_device(UCLASS_MISC, &dev); dev; + ret = uclass_find_next_device(&dev)) { + temp2 = ofnode_to_offset(dev_ofnode(dev)); + if (temp1 == temp2) { + ret = device_probe(dev); + if (ret) + debug("%s: Failed to initialize - %d\n", + dev->name, ret); + return ret; + } + } + + return -ENODEV; +} + UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", diff --git a/include/misc.h b/include/misc.h index 12d1325ee2..79263ed480 100644 --- a/include/misc.h +++ b/include/misc.h @@ -76,6 +76,15 @@ int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size, */ int misc_set_enabled(struct udevice *dev, bool val);

+/** + * misc_init_by_ofnode() - Probe a misc device by using ofnode. + * @node: ofnode of the misc device. + * + * A misc device is probed using ofnode. + * + * Return: -ve on error, 0 on success + */ +int misc_init_by_ofnode(ofnode node); /* * struct misc_ops - Driver model Misc operations *

The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the AM654x family. Each SoC can have one or more PRUSS instances that may or may not be identical.

The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling.

Add support for pruss driver. Currently am654x family is supported.

Signed-off-by: Keerthy j-keerthy@ti.com --- drivers/soc/ti/Kconfig | 13 ++++ drivers/soc/ti/Makefile | 1 + drivers/soc/ti/pruss.c | 128 ++++++++++++++++++++++++++++++++++++++++ include/ti-pruss.h | 12 ++++ 4 files changed, 154 insertions(+) create mode 100644 drivers/soc/ti/pruss.c create mode 100644 include/ti-pruss.h

diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index e4f8834448..179b73a541 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -23,4 +23,17 @@ config TI_KEYSTONE_SERDES SerDes driver for Keystone SoC used for ethernet support on TI K2 platforms.

+config TI_PRUSS + bool "Support for TI's K3 based Pruss driver" + depends on DM + depends on ARCH_K3 + depends on OF_CONTROL + depends on SYSCON + help + + Support for TI PRU-ICSSG subsystem. + + Currently supported on AM65xx SoCs Say Y here to support the + Programmable Realtime Unit (PRU). + endif # SOC_TI diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index 4ec04ee125..34f80aad29 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -2,3 +2,4 @@

obj-$(CONFIG_TI_K3_NAVSS_RINGACC) += k3-navss-ringacc.o obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o +obj-$(CONFIG_TI_PRUSS) += pruss.o diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c new file mode 100644 index 0000000000..03ddaaa539 --- /dev/null +++ b/drivers/soc/ti/pruss.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-ICSS platform driver for various TI SoCs + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy j-keerthy@ti.com + */ + +#include <common.h> +#include <dm.h> +#include <dm/of_access.h> +#include <errno.h> +#include <clk.h> +#include <reset.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <power-domain.h> +#include <ti-pruss.h> + +#define PRUSS_CFG_IEPCLK 0x30 +#define ICSSG_CFG_CORE_SYNC 0x3c + +/* PRUSS_IEPCLK register bits */ +#define PRUSS_IEPCLK_IEP_OCP_CLK_EN BIT(0) + +/* ICSSG CORE_SYNC register bits */ +#define ICSSG_CORE_VBUSP_SYNC_EN BIT(0) + +/** + * enum pruss_mem - PRUSS memory range identifiers + */ +enum pruss_mem { + PRUSS_MEM_DRAM0 = 0, + PRUSS_MEM_DRAM1, + PRUSS_MEM_SHRD_RAM2, + PRUSS_MEM_MAX, +}; + +int pruss_request_shrmem_region(struct udevice *dev, phys_addr_t *loc) +{ + struct pruss *priv; + + priv = dev_get_priv(dev); + if (!priv || !priv->pruss_shrdram2) + return -EINVAL; + + *loc = priv->pruss_shrdram2; + + return 0; +} + +static int pruss_bind(struct udevice *dev) +{ + return dm_scan_fdt_dev(dev); +} + +/** + * pruss_probe() - Basic probe + * @dev: corresponding k3 device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pruss_probe(struct udevice *dev) +{ + struct pruss *priv; + int ret, idx; + ofnode sub_node, node, memories; + struct regmap *regmap_cfg; + struct udevice *syscon; + + priv = dev_get_priv(dev); + node = dev_ofnode(dev); + sub_node = ofnode_find_subnode(node, "cfg"); + memories = ofnode_find_subnode(node, "memories"); + + idx = ofnode_stringlist_search(memories, "reg-names", "dram0"); + priv->pruss_dram0 = ofnode_get_addr_size_index(memories, idx, + (u64 *)&priv->pruss_dram0sz); + idx = ofnode_stringlist_search(memories, "reg-names", "dram1"); + priv->pruss_dram1 = ofnode_get_addr_size_index(memories, idx, + (u64 *)&priv->pruss_dram1sz); + idx = ofnode_stringlist_search(memories, "reg-names", "shrdram2"); + priv->pruss_shrdram2 = ofnode_get_addr_size_index(memories, idx, + (u64 *)&priv->pruss_shrdram2sz); + + ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, sub_node, + &syscon); + + regmap_cfg = syscon_get_regmap(syscon); + + /* + * The CORE block uses two multiplexers to allow software to + * select one of three source clocks (ICSSGn_CORE_CLK, ICSSGn_ICLK or + * ICSSGn_IEP_CLK) for the final clock source of the CORE block. + * The user needs to configure ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN + * bit & ICSSG_IEPCLK_REG[0] IEP_OCP_CLK_EN bit in order to select the + * clock source to the CORE block. + */ + ret = regmap_update_bits(regmap_cfg, ICSSG_CFG_CORE_SYNC, + ICSSG_CORE_VBUSP_SYNC_EN, + ICSSG_CORE_VBUSP_SYNC_EN); + if (ret) + return ret; + ret = regmap_update_bits(regmap_cfg, PRUSS_CFG_IEPCLK, + PRUSS_IEPCLK_IEP_OCP_CLK_EN, + PRUSS_IEPCLK_IEP_OCP_CLK_EN); + if (ret) + return ret; + + dev_dbg(dev, "pruss successfully probed %s\n", dev->name); + + return 0; +} + +static const struct udevice_id pruss_ids[] = { + { .compatible = "ti,am654-icssg"}, + {} +}; + +U_BOOT_DRIVER(pruss) = { + .name = "pruss", + .of_match = pruss_ids, + .id = UCLASS_MISC, + .bind = pruss_bind, + .probe = pruss_probe, + .priv_auto_alloc_size = sizeof(struct pruss), +}; diff --git a/include/ti-pruss.h b/include/ti-pruss.h new file mode 100644 index 0000000000..547ec5ee33 --- /dev/null +++ b/include/ti-pruss.h @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +struct pruss { + phys_addr_t pruss_dram0; + phys_addr_t pruss_dram1; + phys_addr_t pruss_shrdram2; + phys_size_t pruss_dram0sz; + phys_size_t pruss_dram1sz; + phys_size_t pruss_shrdram2sz; +}; + +int pruss_request_shrmem_region(struct udevice *dev, phys_addr_t *loc);

The Programmable Real-Time Unit Subsystem (PRUSS) consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. This patch adds a remoteproc platform driver for managing the individual PRU RISC cores life cycle.

The driver currently supports the AM65xx SoC

Signed-off-by: Keerthy j-keerthy@ti.com --- drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/pru_rproc.c | 384 +++++++++++++++++++++++++++++++++ 3 files changed, 396 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.c

diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index f54a245424..15aeca65ab 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -61,4 +61,15 @@ config REMOTEPROC_TI_POWER help Say 'y' here to add support for TI power processors such as those found on certain TI keystone and OMAP generation SoCs. + +config REMOTEPROC_TI_PRU + bool "Support for TI's K3 based PRU remoteproc driver" + select REMOTEPROC + depends on DM + depends on TI_PRUSS + depends on ARCH_K3 + depends on OF_CONTROL + help + Say 'y' here to add support for TI' K3 remoteproc driver. + endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 271ba55b09..73d061757a 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o +obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c new file mode 100644 index 0000000000..7768cb77e1 --- /dev/null +++ b/drivers/remoteproc/pru_rproc.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-RTU remoteproc driver for various SoCs + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy j-keerthy@ti.com + */ + +#include <common.h> +#include <dm.h> +#include <elf.h> +#include <dm/of_access.h> +#include <remoteproc.h> +#include <errno.h> +#include <clk.h> +#include <reset.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <power-domain.h> +#include <ti-pruss.h> + +/* PRU_ICSS_PRU_CTRL registers */ +#define PRU_CTRL_CTRL 0x0000 +#define PRU_CTRL_STS 0x0004 +#define PRU_CTRL_WAKEUP_EN 0x0008 +#define PRU_CTRL_CYCLE 0x000C +#define PRU_CTRL_STALL 0x0010 +#define PRU_CTRL_CTBIR0 0x0020 +#define PRU_CTRL_CTBIR1 0x0024 +#define PRU_CTRL_CTPPR0 0x0028 +#define PRU_CTRL_CTPPR1 0x002C + +/* CTRL register bit-fields */ +#define CTRL_CTRL_SOFT_RST_N BIT(0) +#define CTRL_CTRL_EN BIT(1) +#define CTRL_CTRL_SLEEPING BIT(2) +#define CTRL_CTRL_CTR_EN BIT(3) +#define CTRL_CTRL_SINGLE_STEP BIT(8) +#define CTRL_CTRL_RUNSTATE BIT(15) + +#define RPROC_FLAGS_SHIFT 16 +#define RPROC_FLAGS_NONE 0 +#define RPROC_FLAGS_ELF_PHDR BIT(0 + RPROC_FLAGS_SHIFT) +#define RPROC_FLAGS_ELF_SHDR BIT(1 + RPROC_FLAGS_SHIFT) + +/** + * enum pru_mem - PRU core memory range identifiers + */ +enum pru_mem { + PRU_MEM_IRAM = 0, + PRU_MEM_CTRL, + PRU_MEM_DEBUG, + PRU_MEM_MAX, +}; + +struct pru_privdata { + phys_addr_t pru_iram; + phys_addr_t pru_ctrl; + phys_addr_t pru_debug; + fdt_size_t pru_iramsz; + fdt_size_t pru_ctrlsz; + fdt_size_t pru_debugsz; + const char *fw_name; + u32 iram_da; + u32 pdram_da; + u32 sdram_da; + u32 shrdram_da; + u32 bootaddr; + int id; + struct pruss *prusspriv; +}; + +static int pru_start(struct udevice *dev) +{ + struct pru_privdata *priv; + int val = 0; + + priv = dev_get_priv(dev); + + val = CTRL_CTRL_EN | ((priv->bootaddr >> 2) << 16); + writel(val, priv->pru_ctrl + PRU_CTRL_CTRL); + + return 0; +} + +static int pru_stop(struct udevice *dev) +{ + struct pru_privdata *priv; + int val = 0; + + priv = dev_get_priv(dev); + + val = readl(priv->pru_ctrl + PRU_CTRL_CTRL); + val &= ~CTRL_CTRL_EN; + writel(val, priv->pru_ctrl + PRU_CTRL_CTRL); + + return 0; +} + +/** + * pru_init() - Initialize the remote processor + * @dev: rproc device pointer + * + * Return: 0 if all went ok, else return appropriate error + */ +static int pru_init(struct udevice *dev) +{ + return 0; +} + +/* + * Convert PRU device address (data spaces only) to kernel virtual address + * + * Each PRU has access to all data memories within the PRUSS, accessible at + * different ranges. So, look through both its primary and secondary Data + * RAMs as well as any shared Data RAM to convert a PRU device address to + * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data + * RAM1 is primary Data RAM for PRU1. + */ +static void *pru_d_da_to_pa(struct pru_privdata *priv, u32 da, int len) +{ + u32 offset; + void *pa = NULL; + phys_addr_t dram0, dram1, shrdram2; + u32 dram0sz, dram1sz, shrdram2sz; + + if (len <= 0) + return NULL; + + dram0 = priv->prusspriv->pruss_dram0; + dram1 = priv->prusspriv->pruss_dram1; + shrdram2 = priv->prusspriv->pruss_shrdram2; + dram0sz = priv->prusspriv->pruss_dram0sz; + dram1sz = priv->prusspriv->pruss_dram1sz; + shrdram2sz = priv->prusspriv->pruss_shrdram2sz; + + /* PRU1 has its local RAM addresses reversed */ + if (priv->id == 1) { + dram1 = priv->prusspriv->pruss_dram0; + dram0 = priv->prusspriv->pruss_dram1; + dram1sz = priv->prusspriv->pruss_dram0sz; + dram0sz = priv->prusspriv->pruss_dram1sz; + } + + if (da >= priv->pdram_da && da + len <= priv->pdram_da + dram0sz) { + offset = da - priv->pdram_da; + pa = (__force void *)(dram0 + offset); + } else if (da >= priv->sdram_da && + da + len <= priv->sdram_da + dram1sz) { + offset = da - priv->sdram_da; + pa = (__force void *)(dram1 + offset); + } else if (da >= priv->shrdram_da && + da + len <= priv->shrdram_da + shrdram2sz) { + offset = da - priv->shrdram_da; + pa = (__force void *)(shrdram2 + offset); + } + + return pa; +} + +/* + * Convert PRU device address (instruction space) to kernel virtual address + * + * A PRU does not have an unified address space. Each PRU has its very own + * private Instruction RAM, and its device address is identical to that of + * its primary Data RAM device address. + */ +static void *pru_i_da_to_pa(struct pru_privdata *priv, u32 da, int len) +{ + u32 offset; + void *pa = NULL; + + if (len <= 0) + return NULL; + + if (da >= priv->iram_da && + da + len <= priv->iram_da + priv->pru_iramsz) { + offset = da - priv->iram_da; + pa = (__force void *)(priv->pru_iram + offset); + } + + return pa; +} + +/* PRU-specific address translator */ +static void *pru_da_to_pa(struct pru_privdata *priv, u64 da, int len, u32 flags) +{ + void *pa; + u32 exec_flag; + + exec_flag = ((flags & RPROC_FLAGS_ELF_SHDR) ? flags & SHF_EXECINSTR : + ((flags & RPROC_FLAGS_ELF_PHDR) ? flags & PF_X : 0)); + + if (exec_flag) + pa = pru_i_da_to_pa(priv, da, len); + else + pa = pru_d_da_to_pa(priv, da, len); + + return pa; +} + +/* + * Custom memory copy implementation for ICSSG PRU/RTU Cores + * + * The ICSSG PRU/RTU cores have a memory copying issue with IRAM memories, that + * is not seen on previous generation SoCs. The data is reflected properly in + * the IRAM memories only for integer (4-byte) copies. Any unaligned copies + * result in all the other pre-existing bytes zeroed out within that 4-byte + * boundary, thereby resulting in wrong text/code in the IRAMs. Also, the + * IRAM memory port interface does not allow any 8-byte copies (as commonly + * used by ARM64 memcpy implementation) and throws an exception. The DRAM + * memory ports do not show this behavior. Use this custom copying function + * to properly load the PRU/RTU firmware images on all memories for simplicity. + * + * TODO: Improve the function to deal with additional corner cases like + * unaligned copy sizes or sub-integer trailing bytes when the need arises. + */ +static int pru_rproc_memcpy(void *dest, void *src, size_t count) +{ + const int *s = src; + int *d = dest; + int size = count / 4; + int *tmp_src = NULL; + + /* limited to 4-byte aligned addresses and copy sizes */ + if ((long)dest % 4 || count % 4) + return -EINVAL; + + /* src offsets in ELF firmware image can be non-aligned */ + if ((long)src % 4) { + tmp_src = malloc(count); + if (!tmp_src) + return -ENOMEM; + + memcpy(tmp_src, src, count); + s = tmp_src; + } + + while (size--) + *d++ = *s++; + + kfree(tmp_src); + + return 0; +} + +static int pru_load(struct udevice *dev, ulong addr, ulong size) +{ + struct pru_privdata *priv; + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + int i, ret = 0; + + priv = dev_get_priv(dev); + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* go through the available ELF segments */ + for (i = 0; i < ehdr->e_phnum; i++, phdr++) { + u32 da = phdr->p_paddr; + u32 memsz = phdr->p_memsz; + u32 filesz = phdr->p_filesz; + u32 offset = phdr->p_offset; + void *ptr; + + if (phdr->p_type != PT_LOAD) + continue; + + dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", + phdr->p_type, da, memsz, filesz); + + if (filesz > memsz) { + dev_dbg(dev, "bad phdr filesz 0x%x memsz 0x%x\n", + filesz, memsz); + ret = -EINVAL; + break; + } + + if (offset + filesz > size) { + dev_dbg(dev, "truncated fw: need 0x%x avail 0x%zx\n", + offset + filesz, size); + ret = -EINVAL; + break; + } + + /* grab the kernel address for this device address */ + ptr = pru_da_to_pa(priv, da, memsz, + RPROC_FLAGS_ELF_PHDR | phdr->p_flags); + if (!ptr) { + dev_dbg(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); + ret = -EINVAL; + break; + } + + /* skip the memzero logic performed by remoteproc ELF loader */ + if (!phdr->p_filesz) + continue; + + ret = pru_rproc_memcpy(ptr, + (void *)addr + phdr->p_offset, filesz); + if (ret) { + dev_dbg(dev, "PRU custom memory copy failed for da 0x%x memsz 0x%x\n", + da, memsz); + break; + } + } + + priv->bootaddr = ehdr->e_entry; + + return ret; +} + +static const struct dm_rproc_ops pru_ops = { + .init = pru_init, + .start = pru_start, + .stop = pru_stop, + .load = pru_load, +}; + +static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) +{ + u32 mask2 = 0x38000; + + if (device_is_compatible(dev, "ti,am654-rtu")) + mask2 = 0x6000; + + if ((priv->pru_iram & mask2) == mask2) + priv->id = 1; + else + priv->id = 0; +} + +/** + * pru_probe() - Basic probe + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_probe(struct udevice *dev) +{ + struct pru_privdata *priv; + int lenp; + ofnode node; + + node = dev_ofnode(dev); + + priv = dev_get_priv(dev); + priv->prusspriv = dev_get_priv(dev->parent); + + priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM, + &priv->pru_iramsz); + priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL, + &priv->pru_ctrlsz); + priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG, + &priv->pru_debugsz); + + priv->fw_name = ofnode_get_property(node, "firmware-name", &lenp); + + priv->iram_da = 0; + priv->pdram_da = 0; + priv->sdram_da = 0x2000; + priv->shrdram_da = 0x10000; + + pru_set_id(priv, dev); + + return 0; +} + +static const struct udevice_id pru_ids[] = { + { .compatible = "ti,am654-pru"}, + { .compatible = "ti,am654-rtu"}, + {} +}; + +U_BOOT_DRIVER(pru) = { + .name = "pru", + .of_match = pru_ids, + .id = UCLASS_REMOTEPROC, + .ops = &pru_ops, + .probe = pru_probe, + .priv_auto_alloc_size = sizeof(struct pru_privdata), +};

Add msmc_ram node needed for prueth

Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/dts/k3-am65-main.dtsi | 21 +++++++++++++++++++++ arch/arm/dts/k3-am65.dtsi | 4 +++- 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 7d03706057..8e2a506185 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -6,6 +6,27 @@ */

&cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x0 0x70000000 0x0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x70000000 0x200000>; + u-boot,dm-spl; + + atf-sram@0 { + reg = <0x0 0x20000>; + }; + + sysfw-sram@f0000 { + reg = <0xf0000 0x10000>; + }; + + l3cache-sram@100000 { + reg = <0x100000 0x100000>; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi index a3abd146d1..431b27813a 100644 --- a/arch/arm/dts/k3-am65.dtsi +++ b/arch/arm/dts/k3-am65.dtsi @@ -76,7 +76,9 @@ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>, + <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>;

cbass_mcu: interconnect@28380000 { compatible = "simple-bus";

Add icssg specific msmc_ram carveout nodes

Signed-off-by: Keerthy j-keerthy@ti.com ---

Carving out as there is no msmc-ram driver. Suggestions welcome.

arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 8589f76d23..71a7069e74 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -361,3 +361,15 @@ &wkup_i2c0 { u-boot,dm-spl; }; + +&msmc_ram { + icssg0_sram: icssg0-sram@40000 { + reg = <0x40000 0x10000>; + }; + icssg1_sram: icssg1-sram@50000 { + reg = <0x50000 0x10000>; + }; + icssg2_sram: icssg2-sram@60000 { + reg = <0x60000 0x10000>; + }; +};

Add pruss nodes. Add nodes as in the 4.19 integration kernel.

Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/dts/k3-am65-main.dtsi | 183 +++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 0cd3e5e606..d357966dac 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ */

+#include <dt-bindings/dma/k3-udma.h> + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -172,4 +174,185 @@ clocks = <&k3_clks 113 1>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; }; + + icssg_soc_bus2: pruss-soc-bus@b226004 { + compatible = "ti,am654-icssg-soc-bus", "simple-bus"; + reg = <0x00 0x0b226004 0x00 0x4>; + power-domains = <&k3_pds 64>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0b200000 0x00 0x0b200000 0x100000>; + dma-ranges; + + icssg2: icssg@b200000 { + compatible = "ti,am654-icssg"; + reg = <0xb200000 0x80000>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + ti,psil-base = <0x4300>; /* ICSSG2 PSIL thread start */ + + ti,psil-config0 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config1 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config2 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config3 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config4 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config5 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config6 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config7 { + linux,udma-mode = <UDMA_PKT_MODE>; + statictr-type = <PSIL_STATIC_TR_NONE>; + ti,needs-epib; + ti,psd-size = <16>; + }; + + icssg2_mem: memories@b200000 { + reg = <0xb200000 0x2000>, + <0xb202000 0x2000>, + <0xb210000 0x10000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + icssg2_cfg: cfg@b226000 { + compatible = "syscon"; + reg = <0xb226000 0x200>; + }; + + icssg2_iep: iep@b22e000 { + compatible = "syscon"; + reg = <0xb22e000 0x1000>; + }; + + icssg2_mii_rt: mii-rt@b232000 { + compatible = "syscon"; + reg = <0xb232000 0x100>; + }; + + icssg2_mii_g_rt: mii-g-rt@b233000 { + compatible = "syscon"; + reg = <0xb233000 0x1000>; + }; + + icssg2_intc: interrupt-controller@b220000 { + compatible = "ti,am654-icssg-intc"; + reg = <0xb220000 0x2000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru2_0: pru@b234000 { + compatible = "ti,am654-pru"; + reg = <0xb234000 0x4000>, + <0xb222000 0x100>, + <0xb222400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru2_0-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <16>, <17>; + interrupt-names = "vring", "kick"; + }; + + rtu2_0: rtu@b204000 { + compatible = "ti,am654-rtu"; + reg = <0xb204000 0x2000>, + <0xb223000 0x100>, + <0xb223400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu2_0-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <20>, <21>; + interrupt-names = "vring", "kick"; + }; + + pru2_1: pru@b238000 { + compatible = "ti,am654-pru"; + reg = <0xb238000 0x4000>, + <0xb224000 0x100>, + <0xb224400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru2_1-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <18>, <19>; + interrupt-names = "vring", "kick"; + }; + + rtu2_1: rtu@b206000 { + compatible = "ti,am654-rtu"; + reg = <0xb206000 0x2000>, + <0xb223800 0x100>, + <0xb223c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu2_1-fw"; + interrupt-parent = <&icssg2_intc>; + interrupts = <22>, <23>; + interrupt-names = "vring", "kick"; + }; + + icssg2_mdio: mdio@b232400 { + compatible = "ti,davinci_mdio"; + reg = <0xb232400 0x100>; + clocks = <&k3_clks 64 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + status = "disabled"; + }; + }; + }; };

ICSSG2 provide dual Gigabit Ethernet support. Currently mdio clock is part of this node and also the icssg2_rgmii_pins_default pinmux node has the mdio pins as there is no davinci mdio driver.

Currently icssg2 instances are supported. Either mii0 or mii1 can be enabled at a time.

Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 118 +++++++++++++++++++ 1 file changed, 118 insertions(+)

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 71a7069e74..53399dfff6 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -16,6 +16,63 @@ serial2 = &main_uart0; ethernet0 = &cpsw_port1; }; + + /* Dual Ethernet application node on PRU-ICSSG2 */ + pruss2_eth: pruss2_eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_rgmii_pins_default>; + sram = <&icssg2_sram>; + clocks = <&k3_clks 64 3>; + clock-names = "mdio_fck"; + u-boot,dm-spl; + + prus = <&pru2_0>, <&rtu2_0>, <&pru2_1>, <&rtu2_1>; + firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf", + "ti-pruss/am65x-rtu0-prueth-fw.elf", + "ti-pruss/am65x-pru1-prueth-fw.elf", + "ti-pruss/am65x-rtu1-prueth-fw.elf"; + mii-g-rt = <&icssg2_mii_g_rt>; + dma-coherent; + dmas = <&mcu_udmap &icssg2 0 UDMA_DIR_TX>, /* egress slice 0 */ + <&mcu_udmap &icssg2 1 UDMA_DIR_TX>, /* egress slice 0 */ + <&mcu_udmap &icssg2 2 UDMA_DIR_TX>, /* egress slice 0 */ + <&mcu_udmap &icssg2 3 UDMA_DIR_TX>, /* mgmnt cmd slice 0 */ + <&mcu_udmap &icssg2 4 UDMA_DIR_TX>, /* egress slice 1 */ + <&mcu_udmap &icssg2 5 UDMA_DIR_TX>, /* egress slice 1 */ + <&mcu_udmap &icssg2 6 UDMA_DIR_TX>, /* egress slice 1 */ + <&mcu_udmap &icssg2 7 UDMA_DIR_TX>, /* mgmnt cmd slice 1 */ + + <&mcu_udmap &icssg2 0 UDMA_DIR_RX>, /* ingress slice 0 */ + <&mcu_udmap &icssg2 1 UDMA_DIR_RX>, /* ingress slice 1 */ + <&mcu_udmap &icssg2 2 UDMA_DIR_RX>, /* mgmnt rsp slice 0 */ + <&mcu_udmap &icssg2 3 UDMA_DIR_RX>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; + + pruss2_emac0: ethernet-mii0 { + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "rgmii-id"; + syscon-rgmii-delay = <&scm_conf 0x4120>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + +/* + * Commenting out the second mii interface as the framework + * supports one interface in a single probe + * So either mii1 or mii2 can be used. In case mii1 is needed + * uncomment mii1 and comment out mii0 + pruss2_emac1: ethernet-mii1 { + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "rgmii-id"; + syscon-rgmii-delay = <&scm_conf 0x4124>; + local-mac-address = [00 00 00 00 00 00]; + }; +*/ + }; };

&cbass_main{ @@ -274,6 +331,47 @@ u-boot,dm-spl; };

+ icssg2_rgmii_pins_default: icssg2_rgmii_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x00ac, PIN_INPUT , 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */ + AM65X_IOPAD(0x00b0, PIN_INPUT , 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */ + AM65X_IOPAD(0x00b4, PIN_INPUT , 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */ + AM65X_IOPAD(0x00b8, PIN_INPUT , 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */ + AM65X_IOPAD(0x00cc, PIN_OUTPUT , 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */ + AM65X_IOPAD(0x00d0, PIN_OUTPUT , 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */ + AM65X_IOPAD(0x00d4, PIN_OUTPUT , 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */ + AM65X_IOPAD(0x00d8, PIN_OUTPUT , 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */ + AM65X_IOPAD(0x00dc, PIN_INPUT , 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */ + AM65X_IOPAD(0x00c4, PIN_OUTPUT , 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */ + AM65X_IOPAD(0x00c0, PIN_INPUT , 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */ + AM65X_IOPAD(0x00bc, PIN_INPUT , 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */ + + AM65X_IOPAD(0x0078, PIN_INPUT , 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */ + AM65X_IOPAD(0x007c, PIN_INPUT , 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */ + AM65X_IOPAD(0x0080, PIN_INPUT , 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */ + AM65X_IOPAD(0x0084, PIN_INPUT , 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */ + AM65X_IOPAD(0x0098, PIN_OUTPUT , 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */ + AM65X_IOPAD(0x009c, PIN_OUTPUT , 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */ + AM65X_IOPAD(0x00a0, PIN_OUTPUT , 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */ + AM65X_IOPAD(0x00a4, PIN_OUTPUT , 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */ + AM65X_IOPAD(0x00a8, PIN_INPUT , 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */ + AM65X_IOPAD(0x0090, PIN_OUTPUT , 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */ + AM65X_IOPAD(0x008c, PIN_INPUT , 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */ + AM65X_IOPAD(0x0088, PIN_INPUT , 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */ + /* HACK to get MDIO Pins in the right state */ + AM65X_IOPAD(0x0094, PIN_INPUT , 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */ + AM65X_IOPAD(0x00c8, PIN_OUTPUT , 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */ + >; + u-boot,dm-spl; + }; + + icssg2_mdio_pins_default: icssg2_mdio_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0094, PIN_INPUT , 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */ + AM65X_IOPAD(0x00c8, PIN_OUTPUT , 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */ + >; + u-boot,dm-spl; + }; };

&main_pmx1 { @@ -373,3 +471,23 @@ reg = <0x60000 0x10000>; }; }; + +&icssg2_mdio{ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_mdio_pins_default>; + + pruss2_eth0_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + + pruss2_eth1_phy: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +};

Enable CONFIG_REMOTEPROC_TI_PRU and related configs. With that enable ICSSG_PRUETH config.

Signed-off-by: Keerthy j-keerthy@ti.com --- configs/am65x_evm_a53_defconfig | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index d43df6a187..dfb5bec794 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -48,6 +48,7 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_SPL_REGMAP=y CONFIG_CLK=y CONFIG_SPL_CLK=y @@ -69,6 +70,7 @@ CONFIG_PHY_TI=y CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_AM64_ICSSG_PRUETH=y CONFIG_PHY=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set @@ -77,10 +79,12 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_REMOTEPROC_TI_PRU=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y +CONFIG_TI_PRUSS=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y