[U-Boot] i.MX6 DRAM_RESET documentation
Hi All
I have a strange issue that maybe you can help explain. Under u-boot during a tftp transfer, we have some boards that show timeouts on our latest build, and 1 board where ethernet doesn't work at all on the latest build. These boards work with an older rev of software. I was able to compare the two versions until I found the relevant change that caused the problem. It was the setting for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.
The working code uses a value of 00b for this field. When I changed it to 11b, things broke. In the documentation, this register is defined differently for mx6q vs mv6solo/duallite. The duallite way works for the quad, and either way works for the duallite.
board/boundary/nitrogen6x/ddr-setup.cfg:DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg:DATA 4 0x020e057c 0x00020030
Who's right? And should it depend on quad vs duallite ? Currently, I believe that the duallite documentation is correct for all.
Thanks Troy
IMX6DQRM-04-2013.pdf has the field defined as below IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET field descriptions 31–20 : This read-only field is reserved and always has the value 0. 19–18 : DDR Select Field Select one of next values for pad: DRAM_RESET. 00 RESERVED0 — Reserved 01 RESERVED1 — Reserved 10 LPDDR2 — LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V) 11 DDR3 — DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V) ___________________________________ mx6solo-Reference Manual Addendum Rev A.2.pdf has the field defined as below
IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET field descriptions Field Description 31–22 : This field is reserved. 21–20 : DO_TRIM Read Only Field 0 0 19–18 : DDR Select Field Select one out of next values for pad: DRAM_RESET. 00 LPDDR1 / DDR3 / (DDR2 ODT) modes 01 DDR2 driver mode 10 LPDDR2 mode 11 Reserved
-----Original Message----- From: Troy Kisky [mailto:troy.kisky@boundarydevices.com] Sent: Wednesday, July 17, 2013 5:59 AM To: Fabio Estevam Cc: Liu Hui-R64343; Benoît Thébaudeau; u-boot@lists.denx.de Subject: i.MX6 DRAM_RESET documentation
Hi All
I have a strange issue that maybe you can help explain. Under u-boot during a tftp transfer, we have some boards that show timeouts on our latest build, and 1 board where ethernet doesn't work at all on the latest build. These boards work with an older rev of software. I was able to compare the two versions until I found the relevant change that caused the problem. It was the setting for IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.
The working code uses a value of 00b for this field. When I changed it to 11b, things broke. In the documentation, this register is defined differently for mx6q vs mv6solo/duallite. The duallite way works for the quad, and either way works for the duallite.
board/boundary/nitrogen6x/ddr-setup.cfg:DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg:DATA 4 0x020e057c 0x00020030
Who's right? And should it depend on quad vs duallite ? Currently, I believe that the duallite documentation is correct for all.
Both are not correct. The MMDC owner has known about this doc issue and will Update them later. The correct is: 00 is the only valid data, others will be Reserved.
Thanks Troy
IMX6DQRM-04-2013.pdf has the field defined as below IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET field descriptions 31–20 : This read-only field is reserved and always has the value 0. 19–18 : DDR Select Field Select one of next values for pad: DRAM_RESET. 00 RESERVED0 — Reserved 01 RESERVED1 — Reserved 10 LPDDR2 — LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V) 11 DDR3 — DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V) ___________________________________ mx6solo-Reference Manual Addendum Rev A.2.pdf has the field defined as below
IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET field descriptions Field Description 31–22 : This field is reserved. 21–20 : DO_TRIM Read Only Field 0 0 19–18 : DDR Select Field Select one out of next values for pad: DRAM_RESET. 00 LPDDR1 / DDR3 / (DDR2 ODT) modes 01 DDR2 driver mode 10 LPDDR2 mode 11 Reserved
On 07/16/2013 07:28 PM, Liu Hui-R64343 wrote:
-----Original Message----- From: Troy Kisky [mailto:troy.kisky@boundarydevices.com]
<snip>
The working code uses a value of 00b for this field. When I changed it to 11b, things broke. In the documentation, this register is defined differently for mx6q vs mv6solo/duallite. The duallite way works for the quad, and either way works for the duallite.
board/boundary/nitrogen6x/ddr-setup.cfg:DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg:DATA 4 0x020e057c 0x00020030
Who's right? And should it depend on quad vs duallite ? Currently, I believe that the duallite documentation is correct for all.
Both are not correct. The MMDC owner has known about this doc issue and will Update them later. The correct is: 00 is the only valid data, others will be Reserved.
Thank you very much for the concise and definitive reply.
On 7/17/2013 7:17 AM, Eric Nelson wrote:
On 07/16/2013 07:28 PM, Liu Hui-R64343 wrote:
-----Original Message----- From: Troy Kisky [mailto:troy.kisky@boundarydevices.com]
<snip>
The working code uses a value of 00b for this field. When I changed it to 11b, things broke. In the documentation, this register is defined differently for mx6q vs mv6solo/duallite. The duallite way works for the quad, and either way works for the duallite.
board/boundary/nitrogen6x/ddr-setup.cfg:DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg:DATA 4 0x020e057c 0x00020030
Who's right? And should it depend on quad vs duallite ? Currently, I believe that the duallite documentation is correct for all.
Both are not correct. The MMDC owner has known about this doc issue and will Update them later. The correct is: 00 is the only valid data, others will be Reserved.
Thank you very much for the concise and definitive reply.
Yes, thank you. I will send a patch for board/boundary/nitrogen6x/ddr-setup.cfg to match board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
Troy
participants (3)
-
Eric Nelson -
Liu Hui-R64343 -
Troy Kisky