This driver was written for Arria10, but it applies to Gen5, too.

The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed.

This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5.

Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs.

To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld.

Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required).

Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---

Changes in v2: - remove detection of sub-mach via compatible version and handle all FPGAs the same - select SYSCON and REGMAP via Kconfig

drivers/net/Kconfig | 2 + drivers/net/dwmac_socfpga.c | 87 ++++++++++++++----------------------- 2 files changed, 35 insertions(+), 54 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7044c6adf3..b7c0b921e6 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -162,6 +162,8 @@ config ETH_DESIGNWARE provide the PHY (physical media interface).

config ETH_DESIGNWARE_SOCFPGA + select REGMAP + select SYSCON bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" depends on DM_ETH && ETH_DESIGNWARE help diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc9677c4..b7bf5dbe69 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -17,16 +17,10 @@

#include <asm/arch/system_manager.h>

-enum dwmac_type { - DWMAC_SOCFPGA_GEN5 = 0, - DWMAC_SOCFPGA_ARRIA10, - DWMAC_SOCFPGA_STRATIX10, -}; - struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; - enum dwmac_type type; void *phy_intf; + u32 reg_shift; };

static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) @@ -63,21 +57,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) }

pdata->phy_intf = range + args.args[0]; - - /* - * Sadly, the Altera DT bindings don't have SoC-specific compatibles, - * so we have to guesstimate which SoC we are running on from the - * DWMAC version. Luckily, Altera at least updated the DWMAC with - * each SoC. - */ - if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a")) - pdata->type = DWMAC_SOCFPGA_GEN5; - - if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a")) - pdata->type = DWMAC_SOCFPGA_ARRIA10; - - if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a")) - pdata->type = DWMAC_SOCFPGA_STRATIX10; + pdata->reg_shift = args.args[1];

return designware_eth_ofdata_to_platdata(dev); } @@ -88,40 +68,39 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; struct reset_ctl_bulk reset_bulk; int ret; - u8 modereg; - - if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { - switch (edata->phy_interface) { - case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_GMII: - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - break; - case PHY_INTERFACE_MODE_RMII: - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - break; - case PHY_INTERFACE_MODE_RGMII: - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - break; - default: - dev_err(dev, "Unsupported PHY mode\n"); - return -EINVAL; - } - - ret = reset_get_bulk(dev, &reset_bulk); - if (ret) { - dev_err(dev, "Failed to get reset: %d\n", ret); - return ret; - } - - reset_assert_bulk(&reset_bulk); - - clrsetbits_le32(pdata->phy_intf, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, - modereg); - - reset_release_bulk(&reset_bulk); + u32 modereg; + u32 modemask; + + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; }

+ ret = reset_get_bulk(dev, &reset_bulk); + if (ret) { + dev_err(dev, "Failed to get reset: %d\n", ret); + return ret; + } + + reset_assert_bulk(&reset_bulk); + + modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; + clrsetbits_le32(pdata->phy_intf, modemask, + modereg << pdata->reg_shift); + + reset_release_bulk(&reset_bulk); + return designware_eth_probe(dev); }

Enable the socfpga specific designware ethernet driver for all Gen5 and Arria10 defconfigs.

This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---

Changes in v2: - only add CONFIG_ETH_DESIGNWARE_SOCFPGA since now REGMAP and SYSCON are selected by this one

configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + 11 files changed, 11 insertions(+)

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 0e5e74a621..a829c33dd8 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -59,6 +59,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index e8de0f5709..5ebc668d32 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b6f4f8a3dd..03a03a6ddd 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -54,6 +54,7 @@ CONFIG_MTD_DEVICE=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 9a89bb5d68..bb202ee3c8 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index db516891ba..3b18e302d2 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -50,6 +50,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 5bed755723..ef3ee65760 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -49,6 +49,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 682e58fdb8..9ce3ec489f 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -54,6 +54,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index abbbcb94d3..39ab85547a 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 53f8d3c348..29d1e557ff 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 97366cdfff..7c4bc5dfc2 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 3eba09dcb1..19c2c5e1e9 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -76,6 +76,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y

The 'dwmac_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon.

This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---

Changes in v2: None

.../mach-socfpga/include/mach/reset_manager.h | 2 - arch/arm/mach-socfpga/misc.c | 65 ------------------- arch/arm/mach-socfpga/misc_gen5.c | 44 +------------ 3 files changed, 1 insertion(+), 110 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index d9e0b33c60..42beaecdd6 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -10,8 +10,6 @@ void reset_cpu(ulong addr);

void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); -int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, - const u8 phymode));

#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 78fbe28724..e1adea143c 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -120,71 +120,6 @@ int arch_cpu_init(void) return 0; }

-#ifdef CONFIG_ETH_DESIGNWARE -static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, - const u8 phymode)) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - resetfn(args.args[0], phy_modereg); - } - - return 0; -} -#endif - #ifndef CONFIG_SPL_BUILD static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 04f237d100..6e11ba6cb2 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -54,48 +54,6 @@ static Altera_desc altera_fpga[] = { }, };

-/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode) -{ - u32 physhift, reset; - - if (of_reset_id == EMAC0_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - reset = SOCFPGA_RESET(EMAC0); - } else if (of_reset_id == EMAC1_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - reset = SOCFPGA_RESET(EMAC1); - } else { - printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); - return; - } - - /* configure to PHY interface select choosed */ - clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, - phymode << physhift); - - /* Release the EMAC controller from reset */ - socfpga_per_reset(reset, 0); -} - -static int socfpga_eth_reset(void) -{ - /* Put all GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - return socfpga_eth_reset_common(gen5_dwmac_reset); -}; -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; -#endif - static const struct { const u16 pn; const char *name; @@ -178,7 +136,7 @@ int arch_misc_init(void) env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) env_set("fpgatype", socfpga_fpga_model[fpga_id].var); - return socfpga_eth_reset(); + return 0; } #endif