On 17 February 2016 at 18:45, Phil Reid preid@electromag.com.au wrote:

G'day George

On 18/02/2016 5:54 AM, George Broz wrote:

...

Hello,

Sorry for the newbie question...

I have an Altera/Terasic board (socfpga_sockit) that has issues recognizing USB storage devices (roughly 60% good / 40% bad):

...

If I try a later release (e.g. v2016.01 which seems to support the Terasic board explicitly) the boot process stops just after loading the SPL.

At this point I have only been changing the u-boot.img component, not the SPL (in the a2 partition of the MMC).

The documentation from Altera about generating the SPL seems to require using Qsys/Quartus tools which I'd really like to avoid.

I can produce u-boot-spl.bin / u-boot.img from make socfpga_sockit_defconfig; make all.

My newbie question ... should be I able to use directly the u-boot-spl.bin generated by the build to replace the SPL on the board?

I've just gone thru the process (this week) of getting uboot 2016.01 to boot on our custom socfpga board. There where a few issues in getting things going. If your using the sd card to boot then the current memory layout is not per the altera documentation. I had to make the changes below to config to match the altera docs. Otherwise it hangs just after the SPL. You also need to use the -dtb image versions with 2016.01 for things to work. Again you may need to make sure the uboot device trees match your hardware. Not all uboot drivers appear to be using the DT as yet.

Note the SPL is tightly coupled to the board design and potentially the FPGA image. If you using bridges or routing HPS resources (eg i2c etc) to the fpga the SPL configures the muxes.

There's a script in uboot src at arch\arm\mach-socfpga\qts-filter.sh That will generate the qts files for you arch.

I haven't tried the USB stuff as yet. There are some issues witht eh altera USB port trigger an Over Current event on device insertation. They've modified the linux kenerl driver to use external OV current detection to get around the problem. My intial workaround was to insert USB device prior to power on. I haven't looked at the uboot USB driver yet to see what's in there.

-- Regards Phil Reid

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906..3a1b59b 100644 (file) --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -357,13 +357,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #endif #endif

Thanks, Phil!

Sorry for the delayed response - got called away, but am back to this now. I patched socfpga_common.h and re-built the project. I picked up spl/u-boot-spl-dtb.sfp and u-boot-dtb.img and transferred them to the SD card with:

dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4

Tried this with both the original DT set (socfpga.dtsi, socfpga_cyclone.dtsi, socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download and also an Altera-patched DT set that I've used to boot into Linux numerous times.

When I start up the board I get:

U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

I'm not a Quartus user, so I haven't done anything with the qts-filter.sh script you mentioned. Do I need to? I don't have any custom FPGA logic - it's just the Terasic board out of the box.

Thanks for any help!

--George Broz Moog Industrial Group

On 2 March 2016 at 23:11, Phil Reid preid@electromag.com.au wrote:

On 3/03/2016 2:49 PM, George Broz wrote:

...

On 1 March 2016 at 19:49, Phil Reid preid@electromag.com.au wrote:

...

On 2/03/2016 10:40 AM, George Broz wrote:

...

Sorry for the delayed response - got called away, but am back to this now. I patched socfpga_common.h and re-built the project. I picked up spl/u-boot-spl-dtb.sfp and u-boot-dtb.img and transferred them to the SD card with:

dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4

Tried this with both the original DT set (socfpga.dtsi, socfpga_cyclone.dtsi, socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download and also an Altera-patched DT set that I've used to boot into Linux numerous times.

When I start up the board I get:

U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

I'm not a Quartus user, so I haven't done anything with the qts-filter.sh script you mentioned. Do I need to? I don't have any custom FPGA logic - it's just the Terasic board out of the box.

Thanks for any help!

Even without the custom FPGA logic the files generated from qts-filter.sh need to match your board. Sets up PLL and SDRAM parameters. I'm not familiar with the Terasic dev board ( I do have the altera devkit, but haven't used it for awhile). I'd hope the files in the git repo are correct for your board. Without the corresponding qsys project it's hard to be sure.

Hi Phil,

So as my next attempt, there was a Quartus/Qsys example that came with the Terasic board (specific to my Rev. of the board).

• I took the contents of the 'handoff folder', .sof, and .sopcinfo file.
• launched an "Embedded Command Shell" from EDS 15.0 and then the BSP

editor GUI

• pointed the BSP editor to the "handoff folder", and hit "Generate"

to produce iocsr, pinmux, pll, etc. files

• applied qts-filter.sh to these files, the output of which I then

dropped into the u-boot source @ ../board/terasic/sockit/qts

• rebuilt uboot spl & image, but got a similar result:

U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

Except now it repeats four times, whereas before it only printed out once.

It that essentially the correct procedure? Is it now a matter of looking through the include files that where generated by qts-filter.sh to find a setting that is "off"?

(BTW - my first attempt was to use EDS 13.0, but that resulted in several undefined macros when it came time to compile u-boot with the qts-filter-generated code. How does one know which tool version to use?)

What does a diff of the new files show compared to the ones in uboot.

Here's two of them...

--- /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig +++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h

@@ -33,10 +33,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6

@@ -46,12 +46,12 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8

@@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32

@@ -168,19 +168,20 @@

#define TRESET_CNTR2_VAL 10 /* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { +const u32 ac_rom_init[] = +{ 0x20700000, 0x20780000, 0x10080431, 0x10080530, 0x10090044, - 0x100a0008, + 0x100a0010, 0x100b0000, 0x10380400, 0x10080449, 0x100804c8, 0x100a0024, - 0x10090010, + 0x10090008, 0x100b0000, 0x30780000, 0x38780000,

@@ -208,7 +209,8 @@ };

/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { +const u32 inst_rom_init[] = +{ 0x80000, 0x80680, 0x8180,

--- /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h.orig +++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h @@ -16,7 +16,7 @@ #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1

I'm using the Quartus 15.0 tool chain at the moment. Turning on debugging in drivers/ddr/altera/sequencer.c may help.

Setting DLEVEL = 2 yields:

U-Boot SPL 2016.01 (Mar 03 2016 - 06:28:33) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration find_vfifo_failing_read:1519: vfifo 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 find_vfifo_failing_read:1519: vfifo 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1864 p: ptap=4 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1877 p/d: ptap=4 dtap=7 end=16399 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1887 found range [14003,16399] rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1895 calculate dtaps_per_ptap for tracking rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1906 backedup phase only: p=3rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1919 find passing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1927 find failing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1948 dtaps_per_ptap=21 - 8 = 13work_bgn=14003 work_end=16399 work_mid=15201 vfifo ptap delay 2496 new work_mid 225 new p 0, tmp_delay=0 new d 9, tmp_delay=225 find_dqs_en_phase: center rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 sdr_find_window_center:1779 center: found: ptap=0 dtap=9 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=0 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=1 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=2 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=3 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=4 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=5 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=6 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=7 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=8 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=9 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=10 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=11 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=12 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=13 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=14 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=15 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (187 != 0) => 1 search_stop_check:2006 center(left): dtap=16 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (179 != 0) => 1 search_stop_check:2006 center(left): dtap=17 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (19 != 0) => 1 search_stop_check:2006 center(left): dtap=18 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (17 != 0) => 1 search_stop_check:2006 center(left): dtap=19 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (16 != 0) => 1 search_stop_check:2006 center(left): dtap=20 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 search_stop_check:2006 center(left): dtap=21 => 255 == 255 &&à

Will try to make sense of these today...

Any insights welcome!

Thanks, --George

-- Regards Phil Reid

On 03/09/2016 02:42 AM, Phil Reid wrote:

G'day George,

On 3/03/2016 10:57 PM, George Broz wrote:

...

On 2 March 2016 at 23:11, Phil Reid preid@electromag.com.au wrote:

...

On 3/03/2016 2:49 PM, George Broz wrote:

...

On 1 March 2016 at 19:49, Phil Reid preid@electromag.com.au wrote:

...

On 2/03/2016 10:40 AM, George Broz wrote:

...

Sorry for the delayed response - got called away, but am back to this now. I patched socfpga_common.h and re-built the project. I picked up spl/u-boot-spl-dtb.sfp and u-boot-dtb.img and transferred them to the SD card with:

dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4

Tried this with both the original DT set (socfpga.dtsi, socfpga_cyclone.dtsi, socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download and also an Altera-patched DT set that I've used to boot into Linux numerous times.

When I start up the board I get:

U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

I'm not a Quartus user, so I haven't done anything with the qts-filter.sh script you mentioned. Do I need to? I don't have any custom FPGA logic - it's just the Terasic board out of the box.

Thanks for any help!

Even without the custom FPGA logic the files generated from qts-filter.sh need to match your board. Sets up PLL and SDRAM parameters. I'm not familiar with the Terasic dev board ( I do have the altera devkit, but haven't used it for awhile). I'd hope the files in the git repo are correct for your board. Without the corresponding qsys project it's hard to be sure.

Hi Phil,

So as my next attempt, there was a Quartus/Qsys example that came with the Terasic board (specific to my Rev. of the board).

• I took the contents of the 'handoff folder', .sof, and .sopcinfo

file.

• launched an "Embedded Command Shell" from EDS 15.0 and then the BSP

editor GUI

• pointed the BSP editor to the "handoff folder", and hit "Generate"

to produce iocsr, pinmux, pll, etc. files

• applied qts-filter.sh to these files, the output of which I then

dropped into the u-boot source @ ../board/terasic/sockit/qts

• rebuilt uboot spl & image, but got a similar result:

U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

Except now it repeats four times, whereas before it only printed out once.

It that essentially the correct procedure? Is it now a matter of looking through the include files that where generated by qts-filter.sh to find a setting that is "off"?

(BTW - my first attempt was to use EDS 13.0, but that resulted in several undefined macros when it came time to compile u-boot with the qts-filter-generated code. How does one know which tool version to use?)

What does a diff of the new files show compared to the ones in uboot.

Here's two of them...

---

/home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig

+++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h

@@ -33,10 +33,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6

@@ -46,12 +46,12 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8

@@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32

@@ -168,19 +168,20 @@

#define TRESET_CNTR2_VAL 10 /* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { +const u32 ac_rom_init[] = +{ 0x20700000, 0x20780000, 0x10080431, 0x10080530, 0x10090044,

• 0x100a0008,

• 0x100a0010, 0x100b0000, 0x10380400, 0x10080449, 0x100804c8, 0x100a0024,

• 0x10090010,

• 0x10090008, 0x100b0000, 0x30780000, 0x38780000,

@@ -208,7 +209,8 @@ };

/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { +const u32 inst_rom_init[] = +{ 0x80000, 0x80680, 0x8180,

---

/home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h.orig

+++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h

@@ -16,7 +16,7 @@ #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1

...

I'm using the Quartus 15.0 tool chain at the moment. Turning on debugging in drivers/ddr/altera/sequencer.c may help.

Setting DLEVEL = 2 yields:

U-Boot SPL 2016.01 (Mar 03 2016 - 06:28:33) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration find_vfifo_failing_read:1519: vfifo 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 find_vfifo_failing_read:1519: vfifo 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1864 p: ptap=4 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1877 p/d: ptap=4 dtap=7 end=16399 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1887 found range [14003,16399] rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1895 calculate dtaps_per_ptap for tracking rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1906 backedup phase only: p=3rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1919 find passing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1927 find failing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1948 dtaps_per_ptap=21 - 8 = 13work_bgn=14003 work_end=16399 work_mid=15201 vfifo ptap delay 2496 new work_mid 225 new p 0, tmp_delay=0 new d 9, tmp_delay=225 find_dqs_en_phase: center rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 sdr_find_window_center:1779 center: found: ptap=0 dtap=9 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=0 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=1 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=2 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=3 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=4 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=5 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=6 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=7 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=8 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=9 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=10 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=11 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=12 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=13 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=14 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=15 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (187 != 0) => 1 search_stop_check:2006 center(left): dtap=16 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (179 != 0) => 1 search_stop_check:2006 center(left): dtap=17 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (19 != 0) => 1 search_stop_check:2006 center(left): dtap=18 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (17 != 0) => 1 search_stop_check:2006 center(left): dtap=19 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (16 != 0) => 1 search_stop_check:2006 center(left): dtap=20 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 search_stop_check:2006 center(left): dtap=21 => 255 == 255 &&à

Will try to make sense of these today...

Any insights welcome!

Any success.

You've reached the limits of my knowledge. The diff shows that there are differences in config. Failure of Memory Calibration has always been my biggest fear with hardware design.

Interesting that the 2013.01 build from the Quartus tools works. But the 2016.01 using the same qts generated files does not. Which would suggest there is something amiss in the code.

Is there similar debug statements in the 2013.01 code?

There is debug(), which you can enable by adding #define DEBUG at the beginning of drivers/ddr/altera/*.c . The other way of tracking down this bug would be to rig the writel()/readl() calls and check what values they use compared to the original altera code.

I'll try and find time to build with the 2016.01 debug statements here and send you a log for comparison.

On 9 March 2016 at 08:06, George Broz brozgeo@gmail.com wrote:

On 9 March 2016 at 02:55, Marek Vasut marex@denx.de wrote:

...

On 03/09/2016 02:42 AM, Phil Reid wrote:

...

G'day George,

On 3/03/2016 10:57 PM, George Broz wrote:

...

On 2 March 2016 at 23:11, Phil Reid preid@electromag.com.au wrote:

...

On 3/03/2016 2:49 PM, George Broz wrote:

...

On 1 March 2016 at 19:49, Phil Reid preid@electromag.com.au wrote: > > On 2/03/2016 10:40 AM, George Broz wrote: > >> Sorry for the delayed response - got called away, but am back to this >> now. I patched >> socfpga_common.h and re-built the project. I picked up >> spl/u-boot-spl-dtb.sfp and >> u-boot-dtb.img and transferred them to the SD card with: >> >> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 >> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4 >> >> Tried this with both the original DT set (socfpga.dtsi, >> socfpga_cyclone.dtsi, >> socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 >> download >> and >> also an Altera-patched DT set that I've used to boot into Linux >> numerous >> times. >> >> When I start up the board I get: >> >> U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) >> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration >> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED >> drivers/ddr/altera/sequencer.c: Calibration complete >> SDRAM calibration failed. >> ### ERROR ### Please RESET the board ### >> >> I'm not a Quartus user, so I haven't done anything with the >> qts-filter.sh script you >> mentioned. Do I need to? I don't have any custom FPGA logic - it's >> just the Terasic >> board out of the box. >> >> Thanks for any help! >> > > Even without the custom FPGA logic the files generated from > qts-filter.sh > need to match your board. > Sets up PLL and SDRAM parameters. > I'm not familiar with the Terasic dev board ( I do have the altera > devkit, > but haven't used it for awhile). > I'd hope the files in the git repo are correct for your board. > Without the corresponding qsys project it's hard to be sure. > Hi Phil,

So as my next attempt, there was a Quartus/Qsys example that came with the Terasic board (specific to my Rev. of the board).

• I took the contents of the 'handoff folder', .sof, and .sopcinfo

file.

• launched an "Embedded Command Shell" from EDS 15.0 and then the BSP

editor GUI

• pointed the BSP editor to the "handoff folder", and hit "Generate"

to produce iocsr, pinmux, pll, etc. files

• applied qts-filter.sh to these files, the output of which I then

dropped into the u-boot source @ ../board/terasic/sockit/qts

• rebuilt uboot spl & image, but got a similar result:

U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

Except now it repeats four times, whereas before it only printed out once.

It that essentially the correct procedure? Is it now a matter of looking through the include files that where generated by qts-filter.sh to find a setting that is "off"?

(BTW - my first attempt was to use EDS 13.0, but that resulted in several undefined macros when it came time to compile u-boot with the qts-filter-generated code. How does one know which tool version to use?)

What does a diff of the new files show compared to the ones in uboot.

Here's two of them...

---

/home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig

+++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h

@@ -33,10 +33,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6

@@ -46,12 +46,12 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8

@@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32

@@ -168,19 +168,20 @@

#define TRESET_CNTR2_VAL 10 /* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { +const u32 ac_rom_init[] = +{ 0x20700000, 0x20780000, 0x10080431, 0x10080530, 0x10090044,

• 0x100a0008,

• 0x100a0010, 0x100b0000, 0x10380400, 0x10080449, 0x100804c8, 0x100a0024,

• 0x10090010,

• 0x10090008, 0x100b0000, 0x30780000, 0x38780000,

@@ -208,7 +209,8 @@ };

/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { +const u32 inst_rom_init[] = +{ 0x80000, 0x80680, 0x8180,

---

/home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h.orig

+++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h

@@ -16,7 +16,7 @@ #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1

...

I'm using the Quartus 15.0 tool chain at the moment. Turning on debugging in drivers/ddr/altera/sequencer.c may help.

Setting DLEVEL = 2 yields:

U-Boot SPL 2016.01 (Mar 03 2016 - 06:28:33) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration find_vfifo_failing_read:1519: vfifo 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 find_vfifo_failing_read:1519: vfifo 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1864 p: ptap=4 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1877 p/d: ptap=4 dtap=7 end=16399 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1887 found range [14003,16399] rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1895 calculate dtaps_per_ptap for tracking rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1906 backedup phase only: p=3rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1919 find passing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1927 find failing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1948 dtaps_per_ptap=21 - 8 = 13work_bgn=14003 work_end=16399 work_mid=15201 vfifo ptap delay 2496 new work_mid 225 new p 0, tmp_delay=0 new d 9, tmp_delay=225 find_dqs_en_phase: center rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 sdr_find_window_center:1779 center: found: ptap=0 dtap=9 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=0 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=1 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=2 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=3 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=4 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=5 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=6 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=7 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=8 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=9 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=10 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=11 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=12 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=13 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=14 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=15 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (187 != 0) => 1 search_stop_check:2006 center(left): dtap=16 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (179 != 0) => 1 search_stop_check:2006 center(left): dtap=17 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (19 != 0) => 1 search_stop_check:2006 center(left): dtap=18 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (17 != 0) => 1 search_stop_check:2006 center(left): dtap=19 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (16 != 0) => 1 search_stop_check:2006 center(left): dtap=20 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 search_stop_check:2006 center(left): dtap=21 => 255 == 255 &&à

Will try to make sense of these today...

Any insights welcome!

Any success.

You've reached the limits of my knowledge. The diff shows that there are differences in config. Failure of Memory Calibration has always been my biggest fear with hardware design.

Interesting that the 2013.01 build from the Quartus tools works. But the 2016.01 using the same qts generated files does not. Which would suggest there is something amiss in the code.

Is there similar debug statements in the 2013.01 code?

There is debug(), which you can enable by adding #define DEBUG at the beginning of drivers/ddr/altera/*.c . The other way of tracking down this bug would be to rig the writel()/readl() calls and check what values they use compared to the original altera code.

Thanks, Phil. I will see what the 2013.01 debug produces. But below is what I see if I add DEBUG to the 2016.03-rc3 code.

Marek - The marking on my DDR parts is 4NE77 D9PXV which translates to Micron part# MT41K256M16HA-125:E. I was looking at the data sheet to see if I could further manually relax some of the settings in sdram_config.h. I was also wondering what DDR parts you have on your boards. Given that your two Rev. D boards work fine, I'm beginning to think mine is defective and I'd be better off to get a new one.

Best regards, --George Broz

U-Boot SPL 2016.03-rc3 (Mar 08 2016 - 15:46:07) scc_mgr_initialize:281: Clearing SCC RFILE index 0 scc_mgr_initialize:281: Clearing SCC RFILE index 1 scc_mgr_initialize:281: Clearing SCC RFILE index 2 scc_mgr_initialize:281: Clearing SCC RFILE index 3 scc_mgr_initialize:281: Clearing SCC RFILE index 4 scc_mgr_initialize:281: Clearing SCC RFILE index 5 scc_mgr_initialize:281: Clearing SCC RFILE index 6 scc_mgr_initialize:281: Clearing SCC RFILE index 7 scc_mgr_initialize:281: Clearing SCC RFILE index 8 scc_mgr_initialize:281: Clearing SCC RFILE index 9 scc_mgr_initialize:281: Clearing SCC RFILE index 10 scc_mgr_initialize:281: Clearing SCC RFILE index 11 scc_mgr_initialize:281: Clearing SCC RFILE index 12 scc_mgr_initialize:281: Clearing SCC RFILE index 13 scc_mgr_initialize:281: Clearing SCC RFILE index 14 scc_mgr_initialize:281: Clearing SCC RFILE index 15 drivers/ddr/altera/sequencer.c: Preparing to start memory calibration DDR3 FULL_RATE ranks=1 cs/dimm=1 dq/dqs=8,8 vg/dqs=1,1 dqs=5,5 dq=40 dm=5 ptap_delay=312 dtap_delay=25 dtap_dqsen_delay=25, dll=8max values: en_p=7 dqdqs_p=0 en_d=31 dqs_in_d=31 io_in_d=31 io_out1_d=31 io_out2_d=0 dqs_in_reserve=4 dqs_out_reserve=6 scc_mgr_set_hhp_extras:477 Setting HHP Extras scc_mgr_set_hhp_extras:480 Done Setting HHP Extras rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=0 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(0,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=0 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-5 (index=3) vfifo_center: new mid_min=-5 new_dqs=9 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=9 mid_min=-5 get_window_mid_index:2288 vfifo_center: *mid_min=2 (index=6) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=0 (index=3) vfifo_center: new mid_min=0 new_dqs=9 vfifo_center: start_dqs=9 start_dqs_en=-1 new_dqs=9 mid_min=0 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=1 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(1,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=1 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-4 (index=3) vfifo_center: new mid_min=-4 new_dqs=8 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=8 mid_min=-4 get_window_mid_index:2288 vfifo_center: *mid_min=2 (index=2) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=-1 (index=3) vfifo_center: new mid_min=-1 new_dqs=9 vfifo_center: start_dqs=8 start_dqs_en=-1 new_dqs=9 mid_min=-1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=2 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(2,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=2 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-3 (index=3) vfifo_center: new mid_min=-3 new_dqs=7 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=7 mid_min=-3 get_window_mid_index:2288 vfifo_center: *mid_min=2 (index=2) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=-1 (index=7) vfifo_center: new mid_min=-1 new_dqs=8 vfifo_center: start_dqs=7 start_dqs_en=-1 new_dqs=8 mid_min=-1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=3 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(3,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=3 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-4 (index=7) vfifo_center: new mid_min=-4 new_dqs=8 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=8 mid_min=-4 get_window_mid_index:2288 vfifo_center: *mid_min=1 (index=2) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=0 (index=3) vfifo_center: new mid_min=0 new_dqs=8 vfifo_center: start_dqs=8 start_dqs_en=-1 new_dqs=8 mid_min=0 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 2) DQS: 2 > 0; adding 2 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 2) DQS: 2 > 0; adding 2 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 4) DQS: 4 > 0; adding 4 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 4) DQS: 4 > 0; adding 4 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 6) DQS: 6 > 0; adding 6 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 6) DQS: 6 > 0; adding 6 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 8) DQS: 8 > 0; adding 8 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 8) DQS: 8 > 0; adding 8 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 10) DQS: 10 > 0; adding 10 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 10) DQS: 10 > 0; adding 10 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 12) DQS: 12 > 0; adding 12 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 12) DQS: 12 > 0; adding 12 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

...

...

I'll try and find time to build with the 2016.01 debug statements here and send you a log for comparison.

-- Best regards, Marek Vasut

Hello again -

So under the assumption my SoCKit h/w was broken, I bought a new board. They are back ordered on SoCKit boards, so I got a DE0-Nano-SoC instead.

I build the v2016.03 (release) version of u-boot-with-spl.sfp.

I power-up the (brand new) board and get:

U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC

U-Boot 2016.03 (Mar 15 2016 - 14:52:42 -0700)

CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A4 or SX/C4, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 In: serial Out: serial Err: serial Model: Terasic DE0-Nano(Atlas) Net: Error: ethernet@ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 =>

And this is a good case... usually it doesn't succeed after the fourth try and I have to cycle power 4 or 5 times before I get lucky.

If I do get lucky and then try to see a USB storage device, then I get:

=> => usb start starting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found =>

(Every time)

The version of u-boot SPL that ships with the board: U-Boot SPL 2013.01.01 (Dec 29 2014 - 15:29:15)

boots every time and has limited USB capability as it can see some USB sticks, but not others.

Anyway - brand new board - same old symptoms.

Is it perhaps a toolchain problem?? I'm using:

Thread model: posix gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 4.9-2014.11)

COLLECT_GCC=arm-poky-linux-gnueabi-gcc COLLECT_LTO_WRAPPER=/opt/poky/1.7.1/sysroots/x86_64-pokysdk-linux/usr/libexec/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/4.9.3/lto-wrapper < snip >

Any advice greatly appreciated.

Regards, --George Broz

On 04/06/2016 02:31 AM, George Broz wrote:

On 5 April 2016 at 15:03, Marek Vasut marex@denx.de wrote:

...

On 04/05/2016 10:33 AM, Phil Reid wrote:

...

On 27/03/2016 4:52 AM, Marek Vasut wrote:

...

On 03/22/2016 06:06 PM, Dinh Nguyen wrote:

...

On 03/20/2016 11:42 AM, Marek Vasut wrote:

...

> > Sorry, I know that doesn't help. So let's walk through my workflow. > I am > not using any Altera tools when I build. > > $make socfpga_de0_nano_soc_defconfig > $make u-boot-with-spl.sfp > $dd if=u-boot-with-spl.sfp of=/dev/sdb3 > > My gcc is: arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1) 4.7.3 > > Has the board ever worked for you at all? Can you try this image: > > https://rocketboards.org/foswiki/view/Documentation/AtlasSoCSdCardImage > > > Dinh

I just ported U-Boot to another customer board. I noticed QSPI has problems and USB can be flaky. That's the standard cache issue we have, disabling dcache fixed that.

I am starting to wonder whether we're hitting some corner case here. Maybe we should eventually try and trace all the register reads and writes generated by the DDR calibration code both in old and new SPL and make a diff to see if something really did change.

Dinh, can you share the marking on the SoC and the DRAMs on your board?

My SoC is:

5CSEMA4U23C6N CACAU1525A

DRAMs are:

ISSI 1510 IS43TR16256A 15HBL K080 P4482100QER2 TWN

Thanks, that's indeed rev. C . About time I bang my head against the desk because this is creepy.

FYI

I've just spend some time trying to update the spl / uboot / kernel & rootfs image on our Altera socdk to use for some software testing / development. Unfortunately it fails in the mem calibration process with the latest uboot most of the time. And when it does boot somtimes fails loading uboot fomr the mmc.

Try this u-boot-socfpga/ddr branch [1] , see if it works for you.

[1] http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr

I downloaded a "snapshot" from the above link producing, u-boot-socfpga-1931be2.tar.gz

When I try to build for sockit or de0_nano_soc I get:

CC drivers/mmc/mmc-uclass.o CC drivers/mmc/dw_mmc.o CC drivers/mmc/mmc.o CC drivers/mmc/socfpga_dw_mmc.o drivers/mmc/socfpga_dw_mmc.c:9:28: fatal error: asm/arch/dwmmc.h: No such file or directory #include <asm/arch/dwmmc.h> ^ compilation terminated. make[1]: *** [drivers/mmc/socfpga_dw_mmc.o] Error 1 make: *** [drivers/mmc] Error 2

Thanks for spotting this. Did you try the most basic of basic approaches:

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 43a7e7e..097db81 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,7 +6,6 @@

#include <common.h> #include <asm/arch/clock_manager.h> -#include <asm/arch/dwmmc.h> #include <asm/arch/system_manager.h> #include <dm.h> #include <dwmmc.h>

The git tree is updated now.

Best regards, Marek Vasut

On 04/06/2016 03:17 AM, George Broz wrote:

On 5 April 2016 at 17:45, Marek Vasut marex@denx.de wrote:

...

On 04/06/2016 02:31 AM, George Broz wrote:

...

On 5 April 2016 at 15:03, Marek Vasut marex@denx.de wrote:

...

On 04/05/2016 10:33 AM, Phil Reid wrote:

...

On 27/03/2016 4:52 AM, Marek Vasut wrote:

...

On 03/22/2016 06:06 PM, Dinh Nguyen wrote: > > > On 03/20/2016 11:42 AM, Marek Vasut wrote: >>> >>> Sorry, I know that doesn't help. So let's walk through my workflow. >>> I am >>> not using any Altera tools when I build. >>> >>> $make socfpga_de0_nano_soc_defconfig >>> $make u-boot-with-spl.sfp >>> $dd if=u-boot-with-spl.sfp of=/dev/sdb3 >>> >>> My gcc is: arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1) 4.7.3 >>> >>> Has the board ever worked for you at all? Can you try this image: >>> >>> https://rocketboards.org/foswiki/view/Documentation/AtlasSoCSdCardImage >>> >>> >>> Dinh >> >> I just ported U-Boot to another customer board. I noticed QSPI has >> problems and USB can be flaky. That's the standard cache issue we >> have, disabling dcache fixed that. >> >> I am starting to wonder whether we're hitting some corner case here. >> Maybe we should eventually try and trace all the register reads and >> writes generated by the DDR calibration code both in old and new SPL >> and make a diff to see if something really did change. >> >> Dinh, can you share the marking on the SoC and the DRAMs on your board? >> > > My SoC is: > > 5CSEMA4U23C6N > CACAU1525A > > DRAMs are: > > ISSI 1510 > IS43TR16256A > 15HBL K080 > P4482100QER2 TWN

Thanks, that's indeed rev. C . About time I bang my head against the desk because this is creepy.

FYI

I've just spend some time trying to update the spl / uboot / kernel & rootfs image on our Altera socdk to use for some software testing / development. Unfortunately it fails in the mem calibration process with the latest uboot most of the time. And when it does boot somtimes fails loading uboot fomr the mmc.

Try this u-boot-socfpga/ddr branch [1] , see if it works for you.

[1] http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr

I downloaded a "snapshot" from the above link producing, u-boot-socfpga-1931be2.tar.gz

When I try to build for sockit or de0_nano_soc I get:

CC drivers/mmc/mmc-uclass.o CC drivers/mmc/dw_mmc.o CC drivers/mmc/mmc.o CC drivers/mmc/socfpga_dw_mmc.o drivers/mmc/socfpga_dw_mmc.c:9:28: fatal error: asm/arch/dwmmc.h: No such file or directory #include <asm/arch/dwmmc.h> ^ compilation terminated. make[1]: *** [drivers/mmc/socfpga_dw_mmc.o] Error 1 make: *** [drivers/mmc] Error 2

Thanks for spotting this. Did you try the most basic of basic approaches:

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 43a7e7e..097db81 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,7 +6,6 @@

#include <common.h> #include <asm/arch/clock_manager.h> -#include <asm/arch/dwmmc.h> #include <asm/arch/system_manager.h> #include <dm.h> #include <dwmmc.h>

The git tree is updated now.

It compiles and it works!

On sockit:

U-Boot SPL 2016.03 (Apr 05 2016 - 17:57:23) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC1

First time that an SPL built from a recent version has run successfully on that board.

Will try it out on de0 tomorrow morning...

This is great news, thanks!

Best regards, Marek Vasut

On Tue, 2016-04-12 at 18:11 +0200, Marek Vasut wrote:

On 04/12/2016 06:08 PM, Dinh Nguyen wrote:

...

On 04/12/2016 11:00 AM, Marek Vasut wrote:

...

On 04/12/2016 05:53 PM, Dinh Nguyen wrote:

...

On 04/07/2016 06:31 PM, George Broz wrote:

...

On 7 April 2016 at 13:39, Marek Vasut marex@denx.de wrote:

...

On 04/07/2016 03:14 PM, George Broz wrote: > On 6 April 2016 at 19:05, Marek Vasut marex@denx.de > wrote: > > On 04/07/2016 03:42 AM, George Broz wrote: > > > > Hi, > > > > > > > U-Boot SPL 2016.03 (Apr 05 2016 - 17:57:23) > > > > > drivers/ddr/altera/sequencer.c: Preparing to > > > > > start memory calibration > > > > > drivers/ddr/altera/sequencer.c: CALIBRATION > > > > > PASSED > > > > > drivers/ddr/altera/sequencer.c: Calibration > > > > > complete > > > > > Trying to boot from MMC1 > > > > > > > > > > First time that an SPL built from a recent > > > > > version has run successfully > > > > > on that board. > > > > > > > > > > Will try it out on de0 tomorrow morning... > > > > > > > > This is great news, thanks! > > > > > > This patch also fixes the intermittent SDRAM > > > calibration failures on my > > > de0_nano_soc board. Thanks so much! > > > > Great > > > > > Now with up-to-date versions of SPL and image... I > > > have some > > > USB questions/news/observations: > > > > > > When using an OTG cable between USB port and mass > > > storage > > > device, the de0_nano_soc board is able to detect and > > > access some USB > > > sticks. The detection with these is almost immediate > > > from when 'usb start' > > > is entered. If the same (working) USB stick is used > > > with a non-OTG cable, > > > I get the timeout messages from before: > > > > > > dwc_otg_core_host_init: Timeout! > > > dwc_otg_core_host_init: Timeout! > > > > > > and this is true even if I add 'dr_mode = "host" ' > > > > I don't think the driver supports the dr_mode property > > yet. Patch is > > welcome. > > > > > to the dts for usb1 > > > of the de0 > > > (and rebuild/reload). The older SPL/image that ships > > > from the Terasic factory > > > detects USB sticks with a non-OTG cable, (the cable > > > that ships with the unit). > > > What is the correct "expected" behavior here?? Is an > > > OTG cable required or > > > not? > > > > The DWC2 driver tests the value of the OTG ID pin, so > > if you don't use > > OTG cable with correct ID pin setup, the host won't > > work. > > > > > Even with the OTG cable, some USB sticks "fail" in a > > > not-so-great way. > > > I have a Kingston stick and the sequence goes like > > > this: > > > > > > => usb reset > > > resetting USB... > > > USB0: Core Release: 2.93a > > > scanning bus 0 for devices... > > > > > > <<< 1 minute, 41 seconds pass before >>> > > > ... Device NOT ready > > > Request Sense returned 00 00 00 > > > > > > <<< then another 24 seconds pass before >>> > > > > > > 2 USB Device(s) found > > > > > > It was able to read some information about the stick: > > > > > > => usb info > > > : > > > 2: Mass Storage, USB Revision 2.0 > > > - Kingston DataTraveler SE9 0014857749E5ECB0173000D3 > > > - Class: (from Interface) Mass Storage > > > - PacketSize: 64 Configurations: 1 > > > - Vendor: 0x0930 Product 0x6545 Version 1.0 > > > Configuration: 1 > > > - Interfaces: 1 Bus Powered 200mA > > > Interface: 0 > > > - Alternate Setting 0, Endpoints: 2 > > > - Class Mass Storage, Transp. SCSI, Bulk only > > > - Endpoint 1 In Bulk MaxPacket 512 > > > - Endpoint 2 Out Bulk MaxPacket 512 > > > > > > BUT, the stick cannot be accessed otherwise, for > > > example: > > > > > > => usb part 0 > > > ## Unknown partition table type 0 > > > > > > > > > Is there any feature of the USB stick that would > > > indicate > > > whether or not it is "compatible" with u-boot? > > > > Can you do "dcache off" before you do "usb reset" and > > see if thusb at fixes > > the problem ? > > The behavior is unchanged if "dcache off" done before > "usb reset".

Try with the attached patch (and probably with dcache off)

The patch applied cleanly. The behavior is unchanged with both dcache on and off. The "good" sticks still work, and "bad" sticks still don't.

Not sure if this helps, but with this patch and dcache off, my "bad" stick (SanDisk Cruzer U 4C530200250418114310) is now working.

You mean the revert is needed on SoCFPGA, right ? I tried bashing Stefan about the patch a bit and I am tempted to just revert it for now, since there seems to be no time to repair it proper :(

Yes, I applied your attached patch as is, not realizing it was a revert of 'c998da0d "usb: Change power-on / scanning timeout handling"'.

I also tested with a revert as well.

Grumble ... I will either look into the patch or revert it. I am not sure yet. Still, the dcache issue is not gone even with the DDR patches.

Yup, same to my case. The DDR works as can boot to Linux at CV socdk but still same issue with USB. I am still suspecting the issue between the cache and DDR area.

With that, I tried to patch both L1 and L2 cache auxiliary register but doesn't help. Attaching the change here and hope can spark some thoughts.

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index d588f94..8c1d217 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -17,8 +17,11 @@ #define L2X0_CTRL_EN 1

#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) +#define L310_AUX_CTRL_FULL_LINE_ZERO_MASK (1 << 0) +#define L310_AUX_CTRL_NS_LOCKDOWN_MASK (1 << 26) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_AUX_CTRL_EARLY_BRESP_MASK (1 << 30)

struct pl310_regs { u32 pl310_cache_id; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach -socfpga/misc.c index dd05e14..f67ab0b 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -53,6 +53,13 @@ void enable_caches(void)

void v7_outer_cache_enable(void) { + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr |= (0x7 << 1); + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); + /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

@@ -60,6 +67,9 @@ void v7_outer_cache_enable(void) setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_AUX_CTRL_EARLY_BRESP_MASK | + L310_AUX_CTRL_NS_LOCKDOWN_MASK | + L310_AUX_CTRL_FULL_LINE_ZERO_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE);

/* Enable the L2 cache */

CC: Marek Vasut

On 03/01/2016 08:40 PM, George Broz wrote:

On 17 February 2016 at 18:45, Phil Reid preid@electromag.com.au wrote:

...

G'day George

On 18/02/2016 5:54 AM, George Broz wrote:

...

Hello,

Sorry for the newbie question...

I have an Altera/Terasic board (socfpga_sockit) that has issues recognizing USB storage devices (roughly 60% good / 40% bad):

...

...

If I try a later release (e.g. v2016.01 which seems to support the Terasic board explicitly) the boot process stops just after loading the SPL.

At this point I have only been changing the u-boot.img component, not the SPL (in the a2 partition of the MMC).

The documentation from Altera about generating the SPL seems to require using Qsys/Quartus tools which I'd really like to avoid.

I can produce u-boot-spl.bin / u-boot.img from make socfpga_sockit_defconfig; make all.

My newbie question ... should be I able to use directly the u-boot-spl.bin generated by the build to replace the SPL on the board?

I've just gone thru the process (this week) of getting uboot 2016.01 to boot on our custom socfpga board. There where a few issues in getting things going. If your using the sd card to boot then the current memory layout is not per the altera documentation. I had to make the changes below to config to match the altera docs. Otherwise it hangs just after the SPL. You also need to use the -dtb image versions with 2016.01 for things to work. Again you may need to make sure the uboot device trees match your hardware. Not all uboot drivers appear to be using the DT as yet.

Note the SPL is tightly coupled to the board design and potentially the FPGA image. If you using bridges or routing HPS resources (eg i2c etc) to the fpga the SPL configures the muxes.

There's a script in uboot src at arch\arm\mach-socfpga\qts-filter.sh That will generate the qts files for you arch.

I haven't tried the USB stuff as yet. There are some issues witht eh altera USB port trigger an Over Current event on device insertation. They've modified the linux kenerl driver to use external OV current detection to get around the problem. My intial workaround was to insert USB device prior to power on. I haven't looked at the uboot USB driver yet to see what's in there.

-- Regards Phil Reid

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906..3a1b59b 100644 (file) --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -357,13 +357,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #endif #endif

Thanks, Phil!

Sorry for the delayed response - got called away, but am back to this now. I patched socfpga_common.h and re-built the project. I picked up spl/u-boot-spl-dtb.sfp and u-boot-dtb.img and transferred them to the SD card with:

dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4

You can just do a 'make u-boot-with-spl.sfp' and burn the u-boot-with-spl.sfp file straight to the a2 partition, or sdf3.

Tried this with both the original DT set (socfpga.dtsi, socfpga_cyclone.dtsi, socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download and also an Altera-patched DT set that I've used to boot into Linux numerous times.

When I start up the board I get:

U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

I'm not a Quartus user, so I haven't done anything with the qts-filter.sh script you mentioned. Do I need to? I don't have any custom FPGA logic - it's just the Terasic board out of the box.

I just tested U-Boot(v2016.03-rc3) and USB is not working on the devkit or sockit. It's failing to detect my mass storage device.

Debugging...

Dinh

On 03/02/2016 04:54 PM, Dinh Nguyen wrote:

CC: Marek Vasut

On 03/01/2016 08:40 PM, George Broz wrote:

...

On 17 February 2016 at 18:45, Phil Reid preid@electromag.com.au wrote:

...

G'day George

On 18/02/2016 5:54 AM, George Broz wrote:

...

Hello,

Sorry for the newbie question...

I have an Altera/Terasic board (socfpga_sockit) that has issues recognizing USB storage devices (roughly 60% good / 40% bad):

...

...

If I try a later release (e.g. v2016.01 which seems to support the Terasic board explicitly) the boot process stops just after loading the SPL.

At this point I have only been changing the u-boot.img component, not the SPL (in the a2 partition of the MMC).

The documentation from Altera about generating the SPL seems to require using Qsys/Quartus tools which I'd really like to avoid.

I can produce u-boot-spl.bin / u-boot.img from make socfpga_sockit_defconfig; make all.

My newbie question ... should be I able to use directly the u-boot-spl.bin generated by the build to replace the SPL on the board?

I've just gone thru the process (this week) of getting uboot 2016.01 to boot on our custom socfpga board. There where a few issues in getting things going. If your using the sd card to boot then the current memory layout is not per the altera documentation. I had to make the changes below to config to match the altera docs. Otherwise it hangs just after the SPL. You also need to use the -dtb image versions with 2016.01 for things to work. Again you may need to make sure the uboot device trees match your hardware. Not all uboot drivers appear to be using the DT as yet.

Note the SPL is tightly coupled to the board design and potentially the FPGA image. If you using bridges or routing HPS resources (eg i2c etc) to the fpga the SPL configures the muxes.

There's a script in uboot src at arch\arm\mach-socfpga\qts-filter.sh That will generate the qts files for you arch.

I haven't tried the USB stuff as yet. There are some issues witht eh altera USB port trigger an Over Current event on device insertation. They've modified the linux kenerl driver to use external OV current detection to get around the problem. My intial workaround was to insert USB device prior to power on. I haven't looked at the uboot USB driver yet to see what's in there.

-- Regards Phil Reid

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906..3a1b59b 100644 (file) --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -357,13 +357,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #endif #endif

Thanks, Phil!

Sorry for the delayed response - got called away, but am back to this now. I patched socfpga_common.h and re-built the project. I picked up spl/u-boot-spl-dtb.sfp and u-boot-dtb.img and transferred them to the SD card with:

dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4

You can just do a 'make u-boot-with-spl.sfp' and burn the u-boot-with-spl.sfp file straight to the a2 partition, or sdf3.

...

Tried this with both the original DT set (socfpga.dtsi, socfpga_cyclone.dtsi, socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download and also an Altera-patched DT set that I've used to boot into Linux numerous times.

When I start up the board I get:

U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

I'm not a Quartus user, so I haven't done anything with the qts-filter.sh script you mentioned. Do I need to? I don't have any custom FPGA logic - it's just the Terasic board out of the box.

I just tested U-Boot(v2016.03-rc3) and USB is not working on the devkit or sockit. It's failing to detect my mass storage device.

Debugging...

Sorry, I mis-spoke for the sockit. I have to turn dcache off for USB to work reliably.

=> dcache off => usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 200mA) SanDisk Firebird USB Flash Drive 4C532000040115111005

=> version

U-Boot 2016.03-rc3 (Mar 02 2016 - 17:00:25 -0600)

Dinh

On 03/02/2016 05:24 PM, Marek Vasut wrote:

Well, that's our usual USB/QSPI cache issue that's tormenting your soul. CCing Chin ;-)

Does the issue by any chance magically disappear if you apply this patch:

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 026e7ef..06802c6 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)

/* options available for data cache on each page */ enum dcache_option {

•   DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  

•   DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
  

TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),

I'm away from my office today and don't have access to the sockit. I can test this tomorrow.

But what's interesting is that I have the DE0-NANO-SOCKIT board at home, and USB seems to be working fine with dcache on.

Dinh

On 3 March 2016 at 06:51, Marek Vasut marex@denx.de wrote:

On 03/03/2016 03:48 PM, Dinh Nguyen wrote:

...

On 03/02/2016 05:24 PM, Marek Vasut wrote:

...

Well, that's our usual USB/QSPI cache issue that's tormenting your soul. CCing Chin ;-)

Does the issue by any chance magically disappear if you apply this patch:

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 026e7ef..06802c6 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)

/* options available for data cache on each page */ enum dcache_option {

•   DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  

•   DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
  

TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),

The 2016.01 code I'm using already includes this patch. If I try reading a USB stick with dcache on or off I get the same result:

=> dcache off => usb reset resetting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub

...

I'm away from my office today and don't have access to the sockit. I can test this tomorrow.

But what's interesting is that I have the DE0-NANO-SOCKIT board at home, and USB seems to be working fine with dcache on.

Yeah, the USB issue happens only with some stick :-/

I've tried five different sticks, same result.

--George

-- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

On 03/03/2016 04:09 PM, Marek Vasut wrote:

On 03/03/2016 11:00 PM, George Broz wrote:

...

On 3 March 2016 at 06:51, Marek Vasut marex@denx.de wrote:

...

On 03/03/2016 03:48 PM, Dinh Nguyen wrote:

...

On 03/02/2016 05:24 PM, Marek Vasut wrote:

...

Well, that's our usual USB/QSPI cache issue that's tormenting your soul. CCing Chin ;-)

Does the issue by any chance magically disappear if you apply this patch:

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 026e7ef..06802c6 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)

/* options available for data cache on each page */ enum dcache_option {

•   DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  

•   DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
  

TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),

The 2016.01 code I'm using already includes this patch. If I try reading a USB stick with dcache on or off I get the same result:

=> dcache off => usb reset resetting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub

This more likely means that either clock or reset bits are not configured correctly OR you're using the wrong controller. Since you're mixing old U-Boot SPL with new U-Boot, there can be some discrepancy and I have no idea how to help you with that :(

Can you try these steps?

1)Boot up 2)"dcache off" 3)"mw.l 0xffb40440 0x00001000 1" 4)"usb start"

On the devkit, it seems that the USB port power bit is not getting turned on, so it's failing to detect the USB device. You can probably ignore stop 2, if you already Marek's patch.

Dinh

On 03/04/2016 05:06 PM, Dinh Nguyen wrote:

On 03/02/2016 05:24 PM, Marek Vasut wrote:

...

On 03/03/2016 12:08 AM, Dinh Nguyen wrote:

...

On 03/02/2016 04:54 PM, Dinh Nguyen wrote:

...

CC: Marek Vasut

On 03/01/2016 08:40 PM, George Broz wrote:

...

On 17 February 2016 at 18:45, Phil Reid preid@electromag.com.au wrote:

...

G'day George

On 18/02/2016 5:54 AM, George Broz wrote: > > Hello, > > Sorry for the newbie question... > > I have an Altera/Terasic board (socfpga_sockit) that has issues > recognizing > USB storage devices (roughly 60% good / 40% bad): >

...

> If I try a later release (e.g. v2016.01 which seems to support the Terasic > board explicitly) the boot process stops just after loading the SPL. > > At this point I have only been changing the u-boot.img component, not the > SPL (in the a2 partition of the MMC). > > The documentation from Altera about generating the SPL seems to require > using Qsys/Quartus tools which I'd really like to avoid. > > I can produce u-boot-spl.bin / u-boot.img from > make socfpga_sockit_defconfig; make all. > > My newbie question ... should be I able to use directly the u-boot-spl.bin > generated by the build to replace the SPL on the board? >

I've just gone thru the process (this week) of getting uboot 2016.01 to boot on our custom socfpga board. There where a few issues in getting things going. If your using the sd card to boot then the current memory layout is not per the altera documentation. I had to make the changes below to config to match the altera docs. Otherwise it hangs just after the SPL. You also need to use the -dtb image versions with 2016.01 for things to work. Again you may need to make sure the uboot device trees match your hardware. Not all uboot drivers appear to be using the DT as yet.

Note the SPL is tightly coupled to the board design and potentially the FPGA image. If you using bridges or routing HPS resources (eg i2c etc) to the fpga the SPL configures the muxes.

There's a script in uboot src at arch\arm\mach-socfpga\qts-filter.sh That will generate the qts files for you arch.

I haven't tried the USB stuff as yet. There are some issues witht eh altera USB port trigger an Over Current event on device insertation. They've modified the linux kenerl driver to use external OV current detection to get around the problem. My intial workaround was to insert USB device prior to power on. I haven't looked at the uboot USB driver yet to see what's in there.

-- Regards Phil Reid

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906..3a1b59b 100644 (file) --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -357,13 +357,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#define CONFIG_SPL_LIBDISK_SUPPORT #else -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #endif #endif

Thanks, Phil!

Sorry for the delayed response - got called away, but am back to this now. I patched socfpga_common.h and re-built the project. I picked up spl/u-boot-spl-dtb.sfp and u-boot-dtb.img and transferred them to the SD card with:

dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4

You can just do a 'make u-boot-with-spl.sfp' and burn the u-boot-with-spl.sfp file straight to the a2 partition, or sdf3.

...

Tried this with both the original DT set (socfpga.dtsi, socfpga_cyclone.dtsi, socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download and also an Altera-patched DT set that I've used to boot into Linux numerous times.

When I start up the board I get:

U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###

I'm not a Quartus user, so I haven't done anything with the qts-filter.sh script you mentioned. Do I need to? I don't have any custom FPGA logic - it's just the Terasic board out of the box.

I just tested U-Boot(v2016.03-rc3) and USB is not working on the devkit or sockit. It's failing to detect my mass storage device.

Debugging...

Sorry, I mis-spoke for the sockit. I have to turn dcache off for USB to work reliably.

=> dcache off => usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 200mA) SanDisk Firebird USB Flash Drive 4C532000040115111005

=> version

U-Boot 2016.03-rc3 (Mar 02 2016 - 17:00:25 -0600)

Well, that's our usual USB/QSPI cache issue that's tormenting your soul. CCing Chin ;-)

Does the issue by any chance magically disappear if you apply this patch:

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 026e7ef..06802c6 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)

/* options available for data cache on each page */ enum dcache_option {

•   DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  

•   DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
  

TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),

Yes, this patch fixes USB with dcache left on.

Except that it doesn't fix anything, it just makes the system slower by setting the S bit :-/ So this is not a fix :-(

Best regards, Marek Vasut

On Mon, 2016-03-21 at 22:05 +0800, Chin Liang See wrote:

On Fri, 2016-03-04 at 20:03 +0100, Marek Vasut wrote:

...

On 03/04/2016 05:06 PM, Dinh Nguyen wrote:

...

On 03/02/2016 05:24 PM, Marek Vasut wrote:

...

On 03/03/2016 12:08 AM, Dinh Nguyen wrote:

...

On 03/02/2016 04:54 PM, Dinh Nguyen wrote:

...

CC: Marek Vasut

On 03/01/2016 08:40 PM, George Broz wrote: > On 17 February 2016 at 18:45, Phil Reid < > preid@electromag.com.au> wrote: > > G'day George > > > > > > On 18/02/2016 5:54 AM, George Broz wrote: > > > > > > Hello, > > > > > > Sorry for the newbie question... > > > > > > I have an Altera/Terasic board (socfpga_sockit) that > > > has issues > > > recognizing > > > USB storage devices (roughly 60% good / 40% bad): > > > > > > > If I try a later release (e.g. v2016.01 which seems > > > to > > > support the Terasic > > > board explicitly) the boot process stops just after > > > loading the SPL. > > > > > > At this point I have only been changing the u > > > -boot.img > > > component, not the > > > SPL (in the a2 partition of the MMC). > > > > > > The documentation from Altera about generating the > > > SPL > > > seems to require > > > using Qsys/Quartus tools which I'd really like to > > > avoid. > > > > > > I can produce u-boot-spl.bin / u-boot.img from > > > make socfpga_sockit_defconfig; make all. > > > > > > My newbie question ... should be I able to use > > > directly > > > the u-boot-spl.bin > > > generated by the build to replace the SPL on the > > > board? > > > > > > > I've just gone thru the process (this week) of getting > > uboot 2016.01 to boot > > on our custom socfpga board. > > There where a few issues in getting things going. > > If your using the sd card to boot then the current > > memory > > layout is not per > > the altera documentation. > > I had to make the changes below to config to match the > > altera docs. > > Otherwise it hangs just after the SPL. > > You also need to use the -dtb image versions with > > 2016.01 > > for things to > > work. > > Again you may need to make sure the uboot device trees > > match your hardware. > > Not all uboot drivers appear to be using the DT as yet. > > > > Note the SPL is tightly coupled to the board design and > > potentially the FPGA > > image. > > If you using bridges or routing HPS resources (eg i2c > > etc) to the fpga the > > SPL configures the muxes. > > > > There's a script in uboot src at arch\arm\mach > > -socfpga\qts-filter.sh > > That will generate the qts files for you arch. > > > > I haven't tried the USB stuff as yet. > > There are some issues witht eh altera USB port trigger > > an > > Over Current event > > on device insertation. > > They've modified the linux kenerl driver to use > > external > > OV current > > detection to get around the problem. > > My intial workaround was to insert USB device prior to > > power on. > > I haven't looked at the uboot USB driver yet to see > > what's in there. > > > > > > -- > > Regards > > Phil Reid > > > > > > diff --git a/include/configs/socfpga_common.h > > b/include/configs/socfpga_common.h > > index a09e906..3a1b59b 100644 (file) > > --- a/include/configs/socfpga_common.h > > +++ b/include/configs/socfpga_common.h > > @@ -357,13 +357,13 @@ unsigned int > > cm_get_qspi_controller_clk_hz(void); > > > > /* SPL SDMMC boot support */ > > #ifdef CONFIG_SPL_MMC_SUPPORT > > +#define CONFIG_SPL_LIBDISK_SUPPORT > > #if defined(CONFIG_SPL_FAT_SUPPORT) || > > defined(CONFIG_SPL_EXT_SUPPORT) > > #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 > > #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot > > -dtb.img" > > -#define CONFIG_SPL_LIBDISK_SUPPORT > > #else > > -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 > > -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 > > /* > > offset 2560 sect > > (1M+256k) */ > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 3 > > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 > > #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 > > KB > > */ > > #endif > > #endif > > > > > > Thanks, Phil! > > Sorry for the delayed response - got called away, but am > back to this > now. I patched > socfpga_common.h and re-built the project. I picked up > spl/u-boot-spl-dtb.sfp and > u-boot-dtb.img and transferred them to the SD card with: > > dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 > dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4 >

You can just do a 'make u-boot-with-spl.sfp' and burn the u-boot-with-spl.sfp file straight to the a2 partition, or sdf3.

> Tried this with both the original DT set (socfpga.dtsi, > socfpga_cyclone.dtsi, > socfpga_cyclone5_sockit.dts) that came with the u-boot > v2016.01 download and > also an Altera-patched DT set that I've used to boot into > Linux numerous times. > > When I start up the board I get: > > U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) > drivers/ddr/altera/sequencer.c: Preparing to start memory > calibration > drivers/ddr/altera/sequencer.c: CALIBRATION FAILED > drivers/ddr/altera/sequencer.c: Calibration complete > SDRAM calibration failed. > ### ERROR ### Please RESET the board ### > > I'm not a Quartus user, so I haven't done anything with > the > qts-filter.sh script you > mentioned. Do I need to? I don't have any custom FPGA > logic > - it's > just the Terasic > board out of the box. >

I just tested U-Boot(v2016.03-rc3) and USB is not working on the devkit or sockit. It's failing to detect my mass storage device.

Debugging...

Sorry, I mis-spoke for the sockit. I have to turn dcache off for USB to work reliably.

=> dcache off => usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 200mA) SanDisk Firebird USB Flash Drive 4C532000040115111005

=> version

U-Boot 2016.03-rc3 (Mar 02 2016 - 17:00:25 -0600)

Well, that's our usual USB/QSPI cache issue that's tormenting your soul. CCing Chin ;-)

Does the issue by any chance magically disappear if you apply this patch:

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 026e7ef..06802c6 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)

/* options available for data cache on each page */ enum dcache_option {

•   DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK |
  

TTB_SECT,

•   DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
  

TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),

Yes, this patch fixes USB with dcache left on.

Except that it doesn't fix anything, it just makes the system slower by setting the S bit :-/ So this is not a fix :-(

Sorry for away for a while as busy with some critical issues.

Finally relooking back on this. I notice that with SanDisk Cruzer Blade pendrive, U-Boot 2013.01.01 can detect it while latest cannot. The dcache disablement at latest U-Boot doesn't help.

With that, I compared a bunch of registers from clocks, sysmgr, SCTLR, ATCLR and USB1 too. I noticed they are similar except the usb1.globgrp.gusbcfg.ulpiextvbusdrv. The latest U-Boot is indicating external supply (address 0xffb4000c return value 0x00101710) while working 2013.01.01 indicating internal charge pump (return value 0x00001710)

Wonder you guys are seeing the same too? Will dig more about this. FYI, I tried to add lot of delay within dwc2.c but doesn't help at all.

While modifying the USB power control of the code, I noticed the patch made by Dinh is not there. Just realize the git clone through http from main git doesn't work. I was able to clone but getting older version.

With getting the latest code, all my pendrive now can works with dcache off. Its easier now as I can get consistent behaviour compared previously. With that, dcache investigation for tomorrow then

Thanks Chin Liang

Thanks Chin Liang

...

Best regards,

Hi Chin,

On 23.03.2016 16:00, Chin Liang See wrote:

On Mon, 2016-03-21 at 23:45 +0800, Chin Liang See wrote:

...

On Mon, 2016-03-21 at 22:05 +0800, Chin Liang See wrote:

...

On Fri, 2016-03-04 at 20:03 +0100, Marek Vasut wrote:

...

On 03/04/2016 05:06 PM, Dinh Nguyen wrote:

...

On 03/02/2016 05:24 PM, Marek Vasut wrote:

[..]

...

...

...

...

...

Well, that's our usual USB/QSPI cache issue that's tormenting your soul. CCing Chin ;-)

Does the issue by any chance magically disappear if you apply this patch:

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 026e7ef..06802c6 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)

/* options available for data cache on each page */ enum dcache_option {

•   DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK |
  

TTB_SECT,

•   DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
  

TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),

Yes, this patch fixes USB with dcache left on.

Except that it doesn't fix anything, it just makes the system slower by setting the S bit :-/ So this is not a fix :-(

Sorry for away for a while as busy with some critical issues.

Finally relooking back on this. I notice that with SanDisk Cruzer Blade pendrive, U-Boot 2013.01.01 can detect it while latest cannot. The dcache disablement at latest U-Boot doesn't help.

With that, I compared a bunch of registers from clocks, sysmgr, SCTLR, ATCLR and USB1 too. I noticed they are similar except the usb1.globgrp.gusbcfg.ulpiextvbusdrv. The latest U-Boot is indicating external supply (address 0xffb4000c return value 0x00101710) while working 2013.01.01 indicating internal charge pump (return value 0x00001710)

Wonder you guys are seeing the same too? Will dig more about this. FYI, I tried to add lot of delay within dwc2.c but doesn't help at all.

While modifying the USB power control of the code, I noticed the patch made by Dinh is not there. Just realize the git clone through http from main git doesn't work. I was able to clone but getting older version.

With getting the latest code, all my pendrive now can works with dcache off. Its easier now as I can get consistent behaviour compared previously. With that, dcache investigation for tomorrow then

Thanks Chin Liang

Spent more time on the dcache + USB issue today. Narrow down to below patch which can make all my USB pendrives work with dcache enabled. But still need to understand further as not in depth familiar with dwc2. Probably this might ring a bell to you guys?

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index b2f4bc6..b11d8d7 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -776,6 +776,7 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | (*pid << DWC2_HCTSIZ_PID_OFFSET), &hc_regs->hctsiz);

•   udelay(2);
  
     if (!in && xfer_len) {
             memcpy(aligned_buffer, buffer, xfer_len);
  

I can't really comment on the USB problem, as I've only seen this d-cache / S-bit problem with SPI NOR flash. This is because I've never really used USB on this platform intensively. But I'm nearly 100% sure, that all changes that add some delays (or debug printfs) resulting in a "working solution", either in the USB case or the SPI NOR case, are just papering over the real problem.

Thanks, Stefan

On 04/06/2016 06:35 PM, Dinh Nguyen wrote:

On Wed, Mar 23, 2016 at 10:37 AM, Stefan Roese sr@denx.de wrote:

...

I can't really comment on the USB problem, as I've only seen this d-cache / S-bit problem with SPI NOR flash. This is because I've never really used USB on this platform intensively. But I'm nearly 100% sure, that all changes that add some delays (or debug printfs) resulting in a "working solution", either in the USB case or the SPI NOR case, are just papering over the real problem.

After a quick chat with Mark Rutland here at ELC, he alluded that there could be a problem with the PL310 interfering with the L1 DCACHE. I won't be able to try it until I get back, but perhaps somebody can test turning off the PL310?

--- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -78,7 +78,6 @@

• Cache

*/ #define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS

Dinh

If this is about disabling PL310 (L2 cache controller), then I already tried that. It did not help :(