[U-Boot] [PATCH 1/3] rockchip: rk3399: add tpl support
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/mach-rockchip/Kconfig | 34 ++++++++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-tpl.c | 84 +++++++++++++++++++++++ include/configs/rk3399_common.h | 9 +++ 4 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d0ed369f55..50add08338 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -154,12 +154,28 @@ config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 select SUPPORT_SPL + select SUPPORT_TPL select SPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER + imply TPL_SERIAL_SUPPORT + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOOTROM_SUPPORT + imply TPL_DRIVERS_MISC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_DM + imply TPL_REGMAP + imply TPL_SYSCON + imply TPL_RAM + imply TPL_CLK + imply TPL_TINY_MEMSET help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -168,6 +184,22 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+if ROCKCHIP_RK3399 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_TEXT_BASE + default 0xff8c2000 + +config TPL_MAX_SIZE + default 188416 + +config TPL_STACK + default 0xff8effff + +endif + config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A @@ -195,7 +227,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" - default y if ROCKCHIP_RK3368 + default y select ROCKCHIP_BROM_HELPER depends on TPL help diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index fd62a693fe..846c82d70a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,6 +12,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c new file mode 100644 index 0000000000..86d3ffe97c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> + +#define TIMER_CHN10_BASE 0xff8680a0 +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void secure_timer_init(void) +{ + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + printascii("U-Boot TPL board init\n"); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + secure_timer_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + pr_err("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index b977b1faa7..6ae3c1f920 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -18,12 +18,21 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_TEXT_BASE 0x00000000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#else #define CONFIG_SPL_STACK 0xff8effff #define CONFIG_SPL_TEXT_BASE 0xff8c2000 #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
Init the ddr sdram in TPL instead of SPL, update the code.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 05ec5fc28d..52518656c4 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -30,7 +30,8 @@ struct chan_info { };
struct dram_info { -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) struct chan_info chan[2]; struct clk ddr_clk; struct rk3399_cru *cru; @@ -55,7 +56,8 @@ struct dram_info { #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf
-#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
struct rockchip_dmc_plat { #if CONFIG_IS_ENABLED(OF_PLATDATA) @@ -1187,7 +1189,8 @@ static int rk3399_dmc_init(struct udevice *dev)
static int rk3399_dmc_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) if (rk3399_dmc_init(dev)) return 0; #else @@ -1226,12 +1229,14 @@ U_BOOT_DRIVER(dmc_rk3399) = { .id = UCLASS_RAM, .of_match = rk3399_dmc_ids, .ops = &rk3399_dmc_ops, -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, #endif .probe = rk3399_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), #endif };
Kever Yang kever.yang@rock-chips.com 于2019年4月1日周一 下午5:25写道：
Init the ddr sdram in TPL instead of SPL, update the code.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
Tested-by: Andy Yan andy.yan@rock-chips.com
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 05ec5fc28d..52518656c4 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -30,7 +30,8 @@ struct chan_info { };
struct dram_info { -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) struct chan_info chan[2]; struct clk ddr_clk; struct rk3399_cru *cru;@@ -55,7 +56,8 @@ struct dram_info { #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf
-#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))struct rockchip_dmc_plat { #if CONFIG_IS_ENABLED(OF_PLATDATA) @@ -1187,7 +1189,8 @@ static int rk3399_dmc_init(struct udevice *dev)
static int rk3399_dmc_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) if (rk3399_dmc_init(dev)) return 0;#else @@ -1226,12 +1229,14 @@ U_BOOT_DRIVER(dmc_rk3399) = { .id = UCLASS_RAM, .of_match = rk3399_dmc_ids, .ops = &rk3399_dmc_ops, -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,#endif .probe = rk3399_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),#endif }; -- 2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
The SPL is now running at SDRAM, and 0x10000 is used by BL31, and the ARM SPL do not support relocate now, we need reserved 0x50000 so that it won't overwrite the code when we load the bl31 to target space. We should remove this after we enable the relocate feature.
The SPL need malloc 0x9000 for MMC as buffer used for transfer data to IRAM(The EMMC DMA can not transfer data to IRAM directly).
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
configs/evb-rk3399_defconfig | 6 ++++-- configs/firefly-rk3399_defconfig | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3a0ed1808b..b5a6019343 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -18,9 +18,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -77,4 +78,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 3b3be2218f..444af07f9a 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -18,9 +18,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -72,4 +73,5 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Kever Yang kever.yang@rock-chips.com 于2019年4月1日周一 下午5:26写道：
The SPL is now running at SDRAM, and 0x10000 is used by BL31, and the ARM SPL do not support relocate now, we need reserved 0x50000 so that it won't overwrite the code when we load the bl31 to target space. We should remove this after we enable the relocate feature.
The SPL need malloc 0x9000 for MMC as buffer used for transfer data to IRAM(The EMMC DMA can not transfer data to IRAM directly).
Signed-off-by: Kever Yang kever.yang@rock-chips.com
configs/evb-rk3399_defconfig | 6 ++++-- configs/firefly-rk3399_defconfig | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-)
Tested-by: Andy Yan andy.yan@rock-chips.com
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3a0ed1808b..b5a6019343 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -18,9 +18,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -77,4 +78,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 3b3be2218f..444af07f9a 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -18,9 +18,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -72,4 +73,5 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -- 2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
Regards, Simon
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/mach-rockchip/Kconfig | 34 ++++++++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-tpl.c | 84 +++++++++++++++++++++++ include/configs/rk3399_common.h | 9 +++ 4 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c
Simon,
On 18.04.2019, at 06:32, Simon Glass sjg@chromium.org wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
For TPL->SPL implementation on Rockchip, we generally rely on the BootROM to load the TPL stage (to SRAM) and the SPL stage (to the start of DRAM). The BootROM usually limits the size of the SPL stage, so we can’t use a full U-Boot already.
Even more constricting are the TPL size constraints (as this seems to have originally only been intended to be size-optimized DRAM init code) on some devices.
Hope this explains the situation, Philipp.
Am Donnerstag, 18. April 2019, 08:35:49 CEST schrieb Philipp Tomsich:
Simon,
On 18.04.2019, at 06:32, Simon Glass sjg@chromium.org wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
For TPL->SPL implementation on Rockchip, we generally rely on the BootROM to load the TPL stage (to SRAM) and the SPL stage (to the start of DRAM). The BootROM usually limits the size of the SPL stage, so we can’t use a full U-Boot already.
Even more constricting are the TPL size constraints (as this seems to have originally only been intended to be size-optimized DRAM init code) on some devices.
and maybe for a broader functionality description, something needs to load things like ATF via a FIT image from a mmc for example. (which needs FIT code and also real mmc drivers).
And as we experienced on rk3288 as well recently, SRAM may be very well too small to accomplish that, so TPL needs to init the sdram separately to make room for the code needed to get ATF up and running, which must be done before jumping into proper uboot.
Heiko
Hi,
On Thu, 18 Apr 2019 at 10:47, Heiko Stübner heiko@sntech.de wrote:
Am Donnerstag, 18. April 2019, 08:35:49 CEST schrieb Philipp Tomsich:
Simon,
On 18.04.2019, at 06:32, Simon Glass sjg@chromium.org wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
For TPL->SPL implementation on Rockchip, we generally rely on the BootROM to load the TPL stage (to SRAM) and the SPL stage (to the start of DRAM). The BootROM usually limits the size of the SPL stage, so we can’t use a full U-Boot already.
Even more constricting are the TPL size constraints (as this seems to have originally only been intended to be size-optimized DRAM init code) on some devices.
and maybe for a broader functionality description, something needs to load things like ATF via a FIT image from a mmc for example. (which needs FIT code and also real mmc drivers).
And as we experienced on rk3288 as well recently, SRAM may be very well too small to accomplish that, so TPL needs to init the sdram separately to make room for the code needed to get ATF up and running, which must be done before jumping into proper uboot.
I have to ask what the boot ROM is buying us? U-Boot TPL/SPL can load programs itself without the boot ROM and its size limit. Why not just stop using the boot ROM on these devices?
Regards, Simon
Hi Simon,
Am Donnerstag, 25. April 2019, 00:26:28 CEST schrieb Simon Glass:
On Thu, 18 Apr 2019 at 10:47, Heiko Stübner heiko@sntech.de wrote:
Am Donnerstag, 18. April 2019, 08:35:49 CEST schrieb Philipp Tomsich:
Simon,
On 18.04.2019, at 06:32, Simon Glass sjg@chromium.org wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
For TPL->SPL implementation on Rockchip, we generally rely on the BootROM to load the TPL stage (to SRAM) and the SPL stage (to the start of DRAM). The BootROM usually limits the size of the SPL stage, so we can’t use a full U-Boot already.
Even more constricting are the TPL size constraints (as this seems to have originally only been intended to be size-optimized DRAM init code) on some devices.
and maybe for a broader functionality description, something needs to load things like ATF via a FIT image from a mmc for example. (which needs FIT code and also real mmc drivers).
And as we experienced on rk3288 as well recently, SRAM may be very well too small to accomplish that, so TPL needs to init the sdram separately to make room for the code needed to get ATF up and running, which must be done before jumping into proper uboot.
I have to ask what the boot ROM is buying us? U-Boot TPL/SPL can load programs itself without the boot ROM and its size limit. Why not just stop using the boot ROM on these devices?
The problem is more that the sram is to small to hold mmc + fit + everything else. So we need at least on some socs bootrom -> tpl (in sram) -> sdram init -> bootrom -> spl (in ddr) (1) -> load fit with u-boot and atf binaries -> jump to ATF -> jump to uboot or in falcon mode for vyasa for example (2) -> load linux directly -> jump to Linux
Heiko
Hi Heiko,
On Thu, 25 Apr 2019 at 03:00, Heiko Stuebner heiko@sntech.de wrote:
Hi Simon,
Am Donnerstag, 25. April 2019, 00:26:28 CEST schrieb Simon Glass:
On Thu, 18 Apr 2019 at 10:47, Heiko Stübner heiko@sntech.de wrote:
Am Donnerstag, 18. April 2019, 08:35:49 CEST schrieb Philipp Tomsich:
Simon,
On 18.04.2019, at 06:32, Simon Glass sjg@chromium.org wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
For TPL->SPL implementation on Rockchip, we generally rely on the BootROM to load the TPL stage (to SRAM) and the SPL stage (to the start of DRAM). The BootROM usually limits the size of the SPL stage, so we can’t use a full U-Boot already.
Even more constricting are the TPL size constraints (as this seems to have originally only been intended to be size-optimized DRAM init code) on some devices.
and maybe for a broader functionality description, something needs to load things like ATF via a FIT image from a mmc for example. (which needs FIT code and also real mmc drivers).
And as we experienced on rk3288 as well recently, SRAM may be very well too small to accomplish that, so TPL needs to init the sdram separately to make room for the code needed to get ATF up and running, which must be done before jumping into proper uboot.
I have to ask what the boot ROM is buying us? U-Boot TPL/SPL can load programs itself without the boot ROM and its size limit. Why not just stop using the boot ROM on these devices?
The problem is more that the sram is to small to hold mmc + fit + everything else. So we need at least on some socs bootrom -> tpl (in sram) -> sdram init -> bootrom -> spl (in ddr) (1) -> load fit with u-boot and atf binaries -> jump to ATF -> jump to uboot or in falcon mode for vyasa for example (2) -> load linux directly -> jump to Linux
But my understanding is that RK3399 has 192KB of SRAM. How much do you need? That should be plenty for SPL?
Regards, Simon
Hi Simon,
On 04/18/2019 12:32 PM, Simon Glass wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
The model is: TPL's code in SRAM, load by BOOTROM, EL3 mode(armv8) ,and focus at DDR SDRAM init, have code size limit by SRAM; SPL's code in DDR, load by BOOTROM, EL3 mode(armv8), and main feature is: - parse and load trust, eg, bl31, bl32, op-tee, which need to before U-Boot; - parse and load firmware for next stage, eg. u-boot, kernel; U-Boot proper code in DDR, load by SPL, EL2 mode(armv8), full feature;
and we may add features like below for SPL: - secure verify for u-boot.itb; - relocate to support bl31 better; - boot kernel in falcon mode directly from SPL; - implement usb download mode(rockusb) in case u-boot is broken; - enable partition support to support A/B system for U-Boot; - more storage driver support at the same time other than mmc, eg. spi, nand;
This model can apply to all Rockchip SoCs, eg, rk3229(patch in list) and rk3288(vyasa) already use this model. RK3399 has bigger SRAM, but it still may have problem to meet the SIZE limit with only one SPL(no TPL) mode, eg. for lpddr4, we need 3 copy of different frequency parameters to init lpddr4, and space available for other driver is be much smaller.
Does this make sense to you?
Thanks, - Kever
Regards, Simon
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/mach-rockchip/Kconfig | 34 ++++++++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-tpl.c | 84 +++++++++++++++++++++++ include/configs/rk3399_common.h | 9 +++ 4 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c
Hi Kever,
On Thu, Apr 18, 2019 at 12:37 PM Kever Yang kever.yang@rock-chips.com wrote:
Hi Simon,
On 04/18/2019 12:32 PM, Simon Glass wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
The model is: TPL's code in SRAM, load by BOOTROM, EL3 mode(armv8) ,and focus at DDR SDRAM init, have code size limit by SRAM; SPL's code in DDR, load by BOOTROM, EL3 mode(armv8), and main feature is:
- parse and load trust, eg, bl31, bl32, op-tee, which need to before U-Boot;
- parse and load firmware for next stage, eg. u-boot, kernel;
U-Boot proper code in DDR, load by SPL, EL2 mode(armv8), full feature;
and we may add features like below for SPL:
- secure verify for u-boot.itb;
- relocate to support bl31 better;
- boot kernel in falcon mode directly from SPL;
- implement usb download mode(rockusb) in case u-boot is broken;
- enable partition support to support A/B system for U-Boot;
- more storage driver support at the same time other than mmc, eg. spi,
nand;
Agreed.
I have tried for similar model to add falcon in rk3288. So the TPL can boot from ROM and SPL can be from boot device sd/emmc/ etc correct?
Jagan.
participants (7)
-
Andy Yan -
Heiko Stuebner -
Heiko Stübner
-
Jagan Teki -
Kever Yang -
Philipp Tomsich -
Simon Glass