This patch adds the header files which will be used in the subsquent board / drivers to enable support for hi6220 hikey board.

Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/include/asm/arch-hi6220/hi6220.h | 387 +++++++++++++++++++ .../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 420 +++++++++++++++++++++ 2 files changed, 807 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h

diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h new file mode 100644 index 0000000..4b987c2 --- /dev/null +++ b/arch/arm/include/asm/arch-hi6220/hi6220.h @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI6220_H__ +#define __HI6220_H__ + +#include "hi6220_regs_alwayson.h" + +#define HI6220_MMC0_BASE 0xF723D000 +#define HI6220_MMC1_BASE 0xF723E000 + +#define HI6220_PMUSSI_BASE 0xF8000000 + +#define HI6220_PERI_BASE 0xF7030000 + +struct peri_sc_periph_regs { + u32 ctrl1; /*0x0*/ + u32 ctrl2; + u32 ctrl3; + u32 ctrl4; + u32 ctrl5; + u32 ctrl6; + u32 ctrl8; + u32 ctrl9; + u32 ctrl10; + u32 ctrl12; + u32 ctrl13; + u32 ctrl14; + + u32 unknown_1[8]; + + u32 ddr_ctrl0; /*0x50*/ + + u32 unknown_2[16]; + + u32 stat1; /*0x94*/ + + u32 unknown_3[90]; + + u32 clk0_en; /*0x200*/ + u32 clk0_dis; + u32 clk0_stat; + + u32 unknown_4; + + u32 clk1_en; /*0x210*/ + u32 clk1_dis; + u32 clk1_stat; + + u32 unknown_5; + + u32 clk2_en; /*0x220*/ + u32 clk2_dis; + u32 clk2_stat; + + u32 unknown_6; + + u32 clk3_en; /*0x230*/ + u32 clk3_dis; + u32 clk3_stat; + + u32 unknown_7; + + u32 clk8_en; /*0x240*/ + u32 clk8_dis; + u32 clk8_stat; + + u32 unknown_8; + + u32 clk9_en; /*0x250*/ + u32 clk9_dis; + u32 clk9_stat; + + u32 unknown_9; + + u32 clk10_en; /*0x260*/ + u32 clk10_dis; + u32 clk10_stat; + + u32 unknown_10; + + u32 clk12_en; /*0x270*/ + u32 clk12_dis; + u32 clk12_stat; + + u32 unknown_11[33]; + + u32 rst0_en; /*0x300*/ + u32 rst0_dis; + u32 rst0_stat; + + u32 unknown_12; + + u32 rst1_en; /*0x310*/ + u32 rst1_dis; + u32 rst1_stat; + + u32 unknown_13; + + u32 rst2_en; /*0x320*/ + u32 rst2_dis; + u32 rst2_stat; + + u32 unknown_14; + + u32 rst3_en; /*0x330*/ + u32 rst3_dis; + u32 rst3_stat; + + u32 unknown_15; + + u32 rst8_en; /*0x340*/ + u32 rst8_dis; + u32 rst8_stat; + + u32 unknown_16[45]; + + u32 clk0_sel; /*0x400*/ + + u32 unknown_17[36]; + + u32 clkcfg8bit1; /*0x494*/ + u32 clkcfg8bit2; + + u32 unknown_18[538]; + + u32 reserved8_addr; /*0xd04*/ +}; + + +/* CTRL1 bit definitions */ + +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) +#define PERI_CTRL1_HIFI_INT_MASK (1 << 1) +#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) +#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) +#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) + + +/* CTRL2 bit definitions */ + +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) +#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) +#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) +#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) +#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) +#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) +#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) +#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) + +/* CTRL3 bit definitions */ + +#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) +#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) +#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) + +/* CTRL4 bit definitions */ + +#define PERI_CTRL4_PICO_FSELV (1 << 0) +#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) +#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) +#define PERI_CTRL4_PICO_SIDDQ (1 << 6) +#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) +#define PERI_CTRL4_PICO_OGDISABLE (1 << 8) +#define PERI_CTRL4_PICO_COMMONONN (1 << 9) +#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) +#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) +#define PERI_CTRL4_PICO_VATESTENB (1 << 12) +#define PERI_CTRL4_PICO_SUSPENDM (1 << 14) +#define PERI_CTRL4_PICO_SLEEPM (1 << 15) +#define PERI_CTRL4_BC11_C (1 << 16) +#define PERI_CTRL4_BC11_B (1 << 17) +#define PERI_CTRL4_BC11_A (1 << 18) +#define PERI_CTRL4_BC11_GND (1 << 19) +#define PERI_CTRL4_BC11_FLOAT (1 << 20) +#define PERI_CTRL4_OTG_PHY_SEL (1 << 21) +#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) +#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) +#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) +#define PERI_CTRL4_OTG_IDPULLUP (1 << 26) +#define PERI_CTRL4_OTG_DRVBUS (1 << 27) +#define PERI_CTRL4_OTG_SESSEND (1 << 28) +#define PERI_CTRL4_OTG_BVALID (1 << 29) +#define PERI_CTRL4_OTG_AVALID (1 << 30) +#define PERI_CTRL4_OTG_VBUSVALID (1 << 31) + +/* CTRL5 bit definitions */ + +#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) +#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) +#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) +#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) +#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) +#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) +#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) +#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) +#define PERI_CTRL5_DBG_MUX (1 << 11) + +/* CTRL6 bit definitions */ + +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) + +/* CTRL8 bit definitions */ + +#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) +#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) +#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) +#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) +#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) +#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) +#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) +#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) +#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) +#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) + +/* CTRL9 bit definitions */ + +#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) +#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) +#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) +#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) + +/* CLK0 EN/DIS/STAT bit definitions */ + +#define PERI_CLK0_MMC0 (1 << 0) +#define PERI_CLK0_MMC1 (1 << 1) +#define PERI_CLK0_MMC2 (1 << 2) +#define PERI_CLK0_NANDC (1 << 3) +#define PERI_CLK0_USBOTG (1 << 4) +#define PERI_CLK0_PICOPHY (1 << 5) +#define PERI_CLK0_PLL (1 << 6) + +/* CLK1 EN/DIS/STAT bit definitions */ + +#define PERI_CLK1_HIFI (1 << 0) +#define PERI_CLK1_DIGACODEC (1 << 5) + +/* CLK2 EN/DIS/STAT bit definitions */ + +#define PERI_CLK2_IPF (1 << 0) +#define PERI_CLK2_SOCP (1 << 1) +#define PERI_CLK2_DMAC (1 << 2) +#define PERI_CLK2_SECENG (1 << 3) +#define PERI_CLK2_HPM0 (1 << 5) +#define PERI_CLK2_HPM1 (1 << 6) +#define PERI_CLK2_HPM2 (1 << 7) +#define PERI_CLK2_HPM3 (1 << 8) + +/* CLK8 EN/DIS/STAT bit definitions */ + +#define PERI_CLK8_RS0 (1 << 0) +#define PERI_CLK8_RS2 (1 << 1) +#define PERI_CLK8_RS3 (1 << 2) +#define PERI_CLK8_MS0 (1 << 3) +#define PERI_CLK8_MS2 (1 << 5) +#define PERI_CLK8_XG2RAM0 (1 << 6) +#define PERI_CLK8_X2SRAM (1 << 7) +#define PERI_CLK8_SRAM (1 << 8) +#define PERI_CLK8_ROM (1 << 9) +#define PERI_CLK8_HARQ (1 << 10) +#define PERI_CLK8_MMU (1 << 11) +#define PERI_CLK8_DDRC (1 << 12) +#define PERI_CLK8_DDRPHY (1 << 13) +#define PERI_CLK8_DDRPHY_REF (1 << 14) +#define PERI_CLK8_X2X_SYSNOC (1 << 15) +#define PERI_CLK8_X2X_CCPU (1 << 16) +#define PERI_CLK8_DDRT (1 << 17) +#define PERI_CLK8_DDRPACK_RS (1 << 18) + +/* CLK9 EN/DIS/STAT bit definitions */ + +#define PERI_CLK9_CARM_DAP (1 << 0) +#define PERI_CLK9_CARM_ATB (1 << 1) +#define PERI_CLK9_CARM_LBUS (1 << 2) +#define PERI_CLK9_CARM_KERNEL (1 << 3) + +/* CLK10 EN/DIS/STAT bit definitions */ + +#define PERI_CLK10_IPF_CCPU (1 << 0) +#define PERI_CLK10_SOCP_CCPU (1 << 1) +#define PERI_CLK10_SECENG_CCPU (1 << 2) +#define PERI_CLK10_HARQ_CCPU (1 << 3) +#define PERI_CLK10_IPF_MCU (1 << 16) +#define PERI_CLK10_SOCP_MCU (1 << 17) +#define PERI_CLK10_SECENG_MCU (1 << 18) +#define PERI_CLK10_HARQ_MCU (1 << 19) + +/* CLK12 EN/DIS/STAT bit definitions */ + +#define PERI_CLK12_HIFI_SRC (1 << 0) +#define PERI_CLK12_MMC0_SRC (1 << 1) +#define PERI_CLK12_MMC1_SRC (1 << 2) +#define PERI_CLK12_MMC2_SRC (1 << 3) +#define PERI_CLK12_SYSPLL_DIV (1 << 4) +#define PERI_CLK12_TPIU_SRC (1 << 5) +#define PERI_CLK12_MMC0_HF (1 << 6) +#define PERI_CLK12_MMC1_HF (1 << 7) +#define PERI_CLK12_PLL_TEST_SRC (1 << 8) +#define PERI_CLK12_CODEC_SOC (1 << 9) +#define PERI_CLK12_MEDIA (1 << 10) + +/* RST0 EN/DIS/STAT bit definitions */ + +#define PERI_RST0_MMC0 (1 << 0) +#define PERI_RST0_MMC1 (1 << 1) +#define PERI_RST0_MMC2 (1 << 2) +#define PERI_RST0_NANDC (1 << 3) +#define PERI_RST0_USBOTG_BUS (1 << 4) +#define PERI_RST0_POR_PICOPHY (1 << 5) +#define PERI_RST0_USBOTG (1 << 6) +#define PERI_RST0_USBOTG_32K (1 << 7) + +/* RST1 EN/DIS/STAT bit definitions */ + +#define PERI_RST1_HIFI (1 << 0) +#define PERI_RST1_DIGACODEC (1 << 5) + +/* RST2 EN/DIS/STAT bit definitions */ + +#define PERI_RST2_IPF (1 << 0) +#define PERI_RST2_SOCP (1 << 1) +#define PERI_RST2_DMAC (1 << 2) +#define PERI_RST2_SECENG (1 << 3) +#define PERI_RST2_ABB (1 << 4) +#define PERI_RST2_HPM0 (1 << 5) +#define PERI_RST2_HPM1 (1 << 6) +#define PERI_RST2_HPM2 (1 << 7) +#define PERI_RST2_HPM3 (1 << 8) + +/* RST3 EN/DIS/STAT bit definitions */ + +#define PERI_RST3_CSSYS (1 << 0) +#define PERI_RST3_I2C0 (1 << 1) +#define PERI_RST3_I2C1 (1 << 2) +#define PERI_RST3_I2C2 (1 << 3) +#define PERI_RST3_I2C3 (1 << 4) +#define PERI_RST3_UART1 (1 << 5) +#define PERI_RST3_UART2 (1 << 6) +#define PERI_RST3_UART3 (1 << 7) +#define PERI_RST3_UART4 (1 << 8) +#define PERI_RST3_SSP (1 << 9) +#define PERI_RST3_PWM (1 << 10) +#define PERI_RST3_BLPWM (1 << 11) +#define PERI_RST3_TSENSOR (1 << 12) +#define PERI_RST3_DAPB (1 << 18) +#define PERI_RST3_HKADC (1 << 19) +#define PERI_RST3_CODEC (1 << 20) + +/* RST8 EN/DIS/STAT bit definitions */ + +#define PERI_RST8_RS0 (1 << 0) +#define PERI_RST8_RS2 (1 << 1) +#define PERI_RST8_RS3 (1 << 2) +#define PERI_RST8_MS0 (1 << 3) +#define PERI_RST8_MS2 (1 << 5) +#define PERI_RST8_XG2RAM0 (1 << 6) +#define PERI_RST8_X2SRAM_TZMA (1 << 7) +#define PERI_RST8_SRAM (1 << 8) +#define PERI_RST8_HARQ (1 << 10) +#define PERI_RST8_DDRC (1 << 12) +#define PERI_RST8_DDRC_APB (1 << 13) +#define PERI_RST8_DDRPACK_APB (1 << 14) +#define PERI_RST8_DDRT (1 << 17) + +#endif /*__HI62220_H__*/ diff --git a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h new file mode 100644 index 0000000..7d286c0 --- /dev/null +++ b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h @@ -0,0 +1,420 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI6220_ALWAYSON_H__ +#define __HI6220_ALWAYSON_H__ + +#define ALWAYSON_CTRL_BASE 0xF7800000 + +struct alwayson_sc_regs { + u32 ctrl0; /*0x0*/ + u32 ctrl1; + u32 ctrl2; + + u32 unknown; + + u32 stat0; /*0x10*/ + u32 stat1; + u32 mcu_imctrl; + u32 mcu_imstat; + + u32 unknown_1[9]; + + u32 secondary_int_en0; /*0x44*/ + u32 secondary_int_statr0; + u32 secondary_int_statm0; + + u32 unknown_2; + + u32 mcu_wkup_int_en6; /*0x54*/ + u32 mcu_wkup_int_statr6; + u32 mcu_wkup_int_statm6; + + u32 unknown_3; + + u32 mcu_wkup_int_en5; /*0x64*/ + u32 mcu_wkup_int_statr5; + u32 mcu_wkup_int_statm5; + + u32 unknown_4[9]; + + u32 mcu_wkup_int_en4; /*0x94*/ + u32 mcu_wkup_int_statr4; + u32 mcu_wkup_int_statm4; + + u32 unknown_5[2]; + + u32 mcu_wkup_int_en0; /*0xa8*/ + u32 mcu_wkup_int_statr0; + u32 mcu_wkup_int_statm0; + + u32 mcu_wkup_int_en1; /*0xb4*/ + u32 mcu_wkup_int_statr1; + u32 mcu_wkup_int_statm1; + + u32 unknown_6; + + u32 int_statr; /*0xc4*/ + u32 int_statm; + u32 int_clear; + + u32 int_en_set; /*0xd0*/ + u32 int_en_dis; + u32 int_en_stat; + + u32 unknown_7[2]; + + u32 int_statr1; /*0xc4*/ + u32 int_statm1; + u32 int_clear1; + + u32 int_en_set1; /*0xf0*/ + u32 int_en_dis1; + u32 int_en_stat1; + + u32 unknown_8[53]; + + u32 timer_en0; /*0x1d0*/ + u32 timer_en1; + + u32 unknown_9[6]; + + u32 timer_en4; /*0x1f0*/ + u32 timer_en5; + + u32 unknown_10[130]; + + u32 mcu_subsys_ctrl0; /*0x400*/ + u32 mcu_subsys_ctrl1; + u32 mcu_subsys_ctrl2; + u32 mcu_subsys_ctrl3; + u32 mcu_subsys_ctrl4; + u32 mcu_subsys_ctrl5; + u32 mcu_subsys_ctrl6; + u32 mcu_subsys_ctrl7; + + u32 unknown_10_1[8]; + + u32 mcu_subsys_stat0; /*0x440*/ + u32 mcu_subsys_stat1; + u32 mcu_subsys_stat2; + u32 mcu_subsys_stat3; + u32 mcu_subsys_stat4; + u32 mcu_subsys_stat5; + u32 mcu_subsys_stat6; + u32 mcu_subsys_stat7; + + u32 unknown_11[116]; + + u32 clk4_en; /*0x630*/ + u32 clk4_dis; + u32 clk4_stat; + + u32 clk5_en; /*0x63c*/ + u32 clk5_dis; + u32 clk5_stat; + + u32 unknown_12[42]; + + u32 rst4_en; /*0x6f0*/ + u32 rst4_dis; + u32 rst4_stat; + + u32 rst5_en; /*0x6fc*/ + u32 rst5_dis; + u32 rst5_stat; + + u32 unknown_13[62]; + + u32 pw_clk0_en; /*0x800*/ + u32 pw_clk0_dis; + u32 pw_clk0_stat; + + u32 unknown_13_1; + + u32 pw_rst0_en; /*0x810*/ + u32 pw_rst0_dis; + u32 pw_rst0_stat; + + u32 unknown_14; + + u32 pw_isoen0; /*0x820*/ + u32 pw_isodis0; + u32 pw_iso_stat0; + + u32 unknown_14_1; + + u32 pw_mtcmos_en0; /*0x830*/ + u32 pw_mtcmos_dis0; + u32 pw_mtcmos_stat0; + u32 pw_mtcmos_ack_stat0; + u32 pw_mtcmos_timeout_stat0; + + u32 unknown_14_2[3]; + + u32 pw_stat0; /*0x850*/ + u32 pw_stat1; + + u32 unknown_15[10]; + + u32 systest_stat; /*0x880*/ + + u32 unknown_16[3]; + + u32 systest_slicer_cnt0;/*0x890*/ + u32 systest_slicer_cnt1; + + u32 unknown_17[12]; + + u32 pw_ctrl1; /*0x8C8*/ + u32 pw_ctrl; + + u32 mcpu_voteen; + u32 mcpu_votedis; + u32 mcpu_votestat; + + u32 unknown_17_1; + + u32 mcpu_vote_msk0; /*0x8E0*/ + u32 mcpu_vote_msk1; + u32 mcpu_votestat0_msk; + u32 mcpu_votestat1_msk; + + u32 peri_voteen; /*0x8F0*/ + u32 peri_votedis; + u32 peri_votestat; + + u32 unknown_17_2; + + u32 peri_vote_msk0; /*0x900*/ + u32 peri_vote_msk1; + u32 peri_votestat0_msk; + u32 erpi_votestat1_msk; + u32 acpu_voteen; + u32 acpu_votedis; + u32 acpu_votestat; + + u32 unknown_18; + + u32 acpu_vote_msk0; /*0x920*/ + u32 acpu_vote_msk1; + u32 acpu_votestat0_msk; + u32 acpu_votestat1_msk; + u32 mcu_voteen; + u32 mcu_votedis; + u32 mcu_votestat; + + u32 unknown_18_1; + + u32 mcu_vote_msk0; /*0x940*/ + u32 mcu_vote_msk1; + u32 mcu_vote_votestat0_msk; + u32 mcu_vote_votestat1_msk; + + u32 unknown_18_1_2[4]; + + u32 mcu_vote_vote1en; /*0x960*/ + u32 mcu_vote_vote1dis; + u32 mcu_vote_vote1stat; + + u32 unknown_18_2; + + u32 mcu_vote_vote1_msk0;/*0x970*/ + u32 mcu_vote_vote1_msk1; + u32 mcu_vote_vote1stat0_msk; + u32 mcu_vote_vote1stat1_msk; + u32 mcu_vote_vote2en; + u32 mcu_vote_vote2dis; + u32 mcu_vote_vote2stat; + + u32 unknown_18_3; + + u32 mcu_vote2_msk0; /*0x990*/ + u32 mcu_vote2_msk1; + u32 mcu_vote2stat0_msk; + u32 mcu_vote2stat1_msk; + u32 vote_ctrl; + u32 vote_stat; /*0x9a4*/ + + u32 unknown_19[342]; + + u32 econum; /*0xf00*/ + + u32 unknown_20_1[3]; + + u32 scchipid; /*0xf10*/ + + u32 unknown_20_2[2]; + + u32 scsocid; /*0xf1c*/ + + u32 unknown_20[48]; + + u32 soc_fpga_rtl_def; /*0xfe0*/ + u32 soc_fpga_pr_def; + u32 soc_fpga_res_def0; + u32 soc_fpga_res_def1; /*0xfec*/ +}; + +/* ctrl0 bit definitions */ + +#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004 +#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007 + +/* ctrl1 bit definitions */ + +#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) +#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) +#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) +#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) +#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) +#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) +#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) +#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) +#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) +#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) +#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) +#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) + +/* ctrl2 bit definitions */ + +#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) +#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) +#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) +#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) +#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) +#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) + +/* stat0 bit definitions */ + +#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) +#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) +#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) +#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) +#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) +#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) +#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) + +/* stat1 bit definitions */ + +#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0) +#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) +#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) +#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) +#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) +#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) +#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) +#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) + +/* ctrl3 bit definitions */ + +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) + +/* clk4_en bit definitions */ + +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7) +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8) +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31) + +/* clk5_en bit definitions */ + +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19) + +/* rst4_dis bit definitions */ + +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7) +#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8) +#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29) +#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30) + +#define PCLK_TIMER1 (1 << 16) +#define PCLK_TIMER0 (1 << 15) + +#endif /* __HI6220_ALWAYSON_H__ */

This adds a simple pmic driver for the hi6553 pmic which is used in conjunction with the hi6220 SoC on the hikey board. Eventually this driver will be updated to be a proper UCLASS PMIC driver which can parse the voltages direct from device tree.

Signed-off-by: Peter Griffin peter.griffin@linaro.org --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_hi6553.c | 133 +++++++++++++++++++++++++++++++++++++++ include/power/hi6553_pmic.h | 79 +++++++++++++++++++++++ 3 files changed, 213 insertions(+) create mode 100644 drivers/power/pmic/pmic_hi6553.c create mode 100644 include/power/hi6553_pmic.h

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index ae86f04..21e9535 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o +obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o diff --git a/drivers/power/pmic/pmic_hi6553.c b/drivers/power/pmic/pmic_hi6553.c new file mode 100644 index 0000000..0af7987 --- /dev/null +++ b/drivers/power/pmic/pmic_hi6553.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <common.h> +#include <power/pmic.h> +#include <power/max8997_muic.h> +#include <power/hi6553_pmic.h> +#include <errno.h> + +u8 *pmussi_base; + +uint8_t hi6553_readb(u32 offset) +{ + return readb(pmussi_base + (offset << 2)); +} + +void hi6553_writeb(u32 offset, uint8_t value) +{ + writeb(value, pmussi_base + (offset << 2)); +} + +int pmic_reg_write(struct pmic *p, u32 reg, u32 val) +{ + if (check_reg(p, reg)) + return -1; + + hi6553_writeb(reg, (uint8_t)val); + + return 0; +} + +int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) +{ + if (check_reg(p, reg)) + return -1; + + *val = (u32)hi6553_readb(reg); + + return 0; +} + +static void hi6553_init(void) +{ + int data; + + hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e); + hi6553_writeb(HI6553_NP_REG_ADJ1, 0); + data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC | + HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2; + hi6553_writeb(HI6553_DISABLE6_XO_CLK, data); + + /* configure BUCK0 & BUCK1 */ + hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e); + hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10); + hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10); + hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e); + hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e); + hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc); + hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc); + + /* configure BUCK2 */ + hi6553_writeb(HI6553_BUCK2_REG1, 0x4f); + hi6553_writeb(HI6553_BUCK2_REG5, 0x99); + hi6553_writeb(HI6553_BUCK2_REG6, 0x45); + mdelay(1); + hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22); + mdelay(1); + + /* configure BUCK3 */ + hi6553_writeb(HI6553_BUCK3_REG3, 0x02); + hi6553_writeb(HI6553_BUCK3_REG5, 0x99); + hi6553_writeb(HI6553_BUCK3_REG6, 0x41); + hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02); + mdelay(1); + + /* configure BUCK4 */ + hi6553_writeb(HI6553_BUCK4_REG2, 0x9a); + hi6553_writeb(HI6553_BUCK4_REG5, 0x99); + hi6553_writeb(HI6553_BUCK4_REG6, 0x45); + + /* configure LDO20 */ + hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50); + + hi6553_writeb(HI6553_NP_REG_CHG, 0x0f); + hi6553_writeb(HI6553_CLK_TOP0, 0x06); + hi6553_writeb(HI6553_CLK_TOP3, 0xc0); + hi6553_writeb(HI6553_CLK_TOP4, 0x00); + + /* configure LDO7 & LDO10 for SD slot */ + data = hi6553_readb(HI6553_LDO7_REG_ADJ); + data = (data & 0xf8) | 0x2; + hi6553_writeb(HI6553_LDO7_REG_ADJ, data); + mdelay(5); + /* enable LDO7 */ + hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6); + mdelay(5); + data = hi6553_readb(HI6553_LDO10_REG_ADJ); + data = (data & 0xf8) | 0x5; + hi6553_writeb(HI6553_LDO10_REG_ADJ, data); + mdelay(5); + /* enable LDO10 */ + hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1); + mdelay(5); + + /* select 32.764KHz */ + hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01); +} + +int power_hi6553_init(u8 *base) +{ + static const char name[] = "HI6553 PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_NONE; + p->number_of_regs = 44; + pmussi_base = base; + + hi6553_init(); + + puts("HI6553 PMIC init\n"); + + return 0; +} diff --git a/include/power/hi6553_pmic.h b/include/power/hi6553_pmic.h new file mode 100644 index 0000000..fcd131a --- /dev/null +++ b/include/power/hi6553_pmic.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI6553_PMIC_H__ +#define __HI6553_PMIC_H__ + +/* Registers */ +enum { + HI6553_VERSION_REG = 0x000, + HI6553_ENABLE2_LDO1_8 = 0x029, + HI6553_DISABLE2_LDO1_8, + HI6553_ONOFF_STATUS2_LDO1_8, + HI6553_ENABLE3_LDO9_16, + HI6553_DISABLE3_LDO9_16, + HI6553_ONOFF_STATUS3_LDO9_16, + + HI6553_DISABLE6_XO_CLK = 0x036, + HI6553_PERI_EN_MARK = 0x040, + HI6553_BUCK2_REG1 = 0x04a, + HI6553_BUCK2_REG5 = 0x04e, + HI6553_BUCK2_REG6, + + HI6553_BUCK3_REG3 = 0x054, + HI6553_BUCK3_REG5 = 0x056, + HI6553_BUCK3_REG6, + HI6553_BUCK4_REG2 = 0x05b, + HI6553_BUCK4_REG5 = 0x05e, + HI6553_BUCK4_REG6, + + HI6553_CLK_TOP0 = 0x063, + HI6553_CLK_TOP3 = 0x066, + HI6553_CLK_TOP4, + HI6553_VSET_BUCK2_ADJ = 0x06d, + HI6553_VSET_BUCK3_ADJ, + HI6553_LDO7_REG_ADJ = 0x078, + HI6553_LDO10_REG_ADJ = 0x07b, + HI6553_LDO19_REG_ADJ = 0x084, + HI6553_LDO20_REG_ADJ, + HI6553_DR_LED_CTRL = 0x098, + HI6553_DR_OUT_CTRL, + HI6553_DR3_ISET, + HI6553_DR3_START_DEL, + HI6553_DR4_ISET, + HI6553_DR4_START_DEL, + HI6553_DR345_TIM_CONF0 = 0x0a0, + HI6553_NP_REG_ADJ1 = 0x0be, + HI6553_NP_REG_CHG = 0x0c0, + HI6553_BUCK01_CTRL2 = 0x0d9, + HI6553_BUCK0_CTRL1 = 0x0dd, + HI6553_BUCK0_CTRL5 = 0x0e1, + HI6553_BUCK0_CTRL7 = 0x0e3, + HI6553_BUCK1_CTRL1 = 0x0e8, + HI6553_BUCK1_CTRL5 = 0x0ec, + HI6553_BUCK1_CTRL7 = 0x0ef, + HI6553_CLK19M2_600_586_EN = 0x0fe, +}; + +#define HI6553_DISABLE6_XO_CLK_BB (1 << 0) +#define HI6553_DISABLE6_XO_CLK_CONN (1 << 1) +#define HI6553_DISABLE6_XO_CLK_NFC (1 << 2) +#define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3) +#define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4) + +#define HI6553_LED_START_DELAY_TIME 0x00 +#define HI6553_LED_ELEC_VALUE 0x07 +#define HI6553_LED_LIGHT_TIME 0xf0 +#define HI6553_LED_GREEN_ENABLE (1 << 1) +#define HI6553_LED_OUT_CTRL 0x00 + +#define HI6553_PMU_V300 0x30 +#define HI6553_PMU_V310 0x31 + +int power_hi6553_init(u8 *base); + +#endif /* __HI6553_PMIC_H__ */

HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's.

This initial port adds support for: - 1) Serial 2) eMMC / SD card 3) USB 4) GPIO

It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.

Notes:

eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode.

SD card slot has been tested for reading and booting kernels into DDR. It is also currently configured to save the u-boot environment to the SD card.

USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage are correctly enumerated.

GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs.

Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf

Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf

Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/Kconfig | 8 + board/hisilicon/hikey/Kconfig | 15 ++ board/hisilicon/hikey/Makefile | 8 + board/hisilicon/hikey/hikey.c | 356 +++++++++++++++++++++++++++++++++++++++++ configs/hikey_defconfig | 5 + include/configs/hikey.h | 159 ++++++++++++++++++ 6 files changed, 551 insertions(+) create mode 100644 board/hisilicon/hikey/Kconfig create mode 100644 board/hisilicon/hikey/Makefile create mode 100644 board/hisilicon/hikey/hikey.c create mode 100644 configs/hikey_defconfig create mode 100644 include/configs/hikey.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9908b43..767f0d8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -735,6 +735,13 @@ config TARGET_LS2085ARDB development platform that supports the QorIQ LS2085A Layerscape Architecture processor.

+config TARGET_HIKEY + bool "Support HiKey 96boards Consumer Edition Platform" + select ARM64 + help + Support for HiKey 96boards platform. It features a HI6220 + SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -880,6 +887,7 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/hisilicon/hikey/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig new file mode 100644 index 0000000..f7f1055 --- /dev/null +++ b/board/hisilicon/hikey/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HIKEY + +config SYS_BOARD + default "hikey" + +config SYS_VENDOR + default "hisilicon" + +config SYS_SOC + default "hi6220" + +config SYS_CONFIG_NAME + default "hikey" + +endif diff --git a/board/hisilicon/hikey/Makefile b/board/hisilicon/hikey/Makefile new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/hisilicon/hikey/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := hikey.o diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c new file mode 100644 index 0000000..8c1271b --- /dev/null +++ b/board/hisilicon/hikey/hikey.c @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <netdev.h> +#include <asm/io.h> +#include <usb.h> +#include <power/hi6553_pmic.h> +#include <asm-generic/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/periph.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/hi6220.h> + +/*TODO drop this table in favour of device tree */ +static const struct hikey_gpio_platdata hi6220_gpio[] = { + { 0, HI6220_GPIO_BASE(0)}, + { 1, HI6220_GPIO_BASE(1)}, + { 2, HI6220_GPIO_BASE(2)}, + { 3, HI6220_GPIO_BASE(3)}, + { 4, HI6220_GPIO_BASE(4)}, + { 5, HI6220_GPIO_BASE(5)}, + { 6, HI6220_GPIO_BASE(6)}, + { 7, HI6220_GPIO_BASE(7)}, + { 8, HI6220_GPIO_BASE(8)}, + { 9, HI6220_GPIO_BASE(9)}, + { 10, HI6220_GPIO_BASE(10)}, + { 11, HI6220_GPIO_BASE(11)}, + { 12, HI6220_GPIO_BASE(12)}, + { 13, HI6220_GPIO_BASE(13)}, + { 14, HI6220_GPIO_BASE(14)}, + { 15, HI6220_GPIO_BASE(15)}, + { 16, HI6220_GPIO_BASE(16)}, + { 17, HI6220_GPIO_BASE(17)}, + { 18, HI6220_GPIO_BASE(18)}, + { 19, HI6220_GPIO_BASE(19)}, + +}; + +U_BOOT_DEVICES(hi6220_gpios) = { + { "gpio_hi6220", &hi6220_gpio[0] }, + { "gpio_hi6220", &hi6220_gpio[1] }, + { "gpio_hi6220", &hi6220_gpio[2] }, + { "gpio_hi6220", &hi6220_gpio[3] }, + { "gpio_hi6220", &hi6220_gpio[4] }, + { "gpio_hi6220", &hi6220_gpio[5] }, + { "gpio_hi6220", &hi6220_gpio[6] }, + { "gpio_hi6220", &hi6220_gpio[7] }, + { "gpio_hi6220", &hi6220_gpio[8] }, + { "gpio_hi6220", &hi6220_gpio[9] }, + { "gpio_hi6220", &hi6220_gpio[10] }, + { "gpio_hi6220", &hi6220_gpio[11] }, + { "gpio_hi6220", &hi6220_gpio[12] }, + { "gpio_hi6220", &hi6220_gpio[13] }, + { "gpio_hi6220", &hi6220_gpio[14] }, + { "gpio_hi6220", &hi6220_gpio[15] }, + { "gpio_hi6220", &hi6220_gpio[16] }, + { "gpio_hi6220", &hi6220_gpio[17] }, + { "gpio_hi6220", &hi6220_gpio[18] }, + { "gpio_hi6220", &hi6220_gpio[19] }, +}; + +DECLARE_GLOBAL_DATA_PTR; + +struct peri_sc_periph_regs *peri_sc = + (struct peri_sc_periph_regs *)HI6220_PERI_BASE; + +struct alwayson_sc_regs *ao_sc = + (struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE; + +/* status offset from enable reg */ +#define STAT_EN_OFF 0x2 + +void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base) +{ + uint32_t data; + + data = readl(clk_base); + data |= bitfield; + + writel(bitfield, clk_base); + do { + data = readl(clk_base + STAT_EN_OFF); + } while ((data & bitfield) == 0); +} + +/* status offset from disable reg */ +#define STAT_DIS_OFF 0x1 + +void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base) +{ + uint32_t data; + + data = readl(clk_base); + data |= bitfield; + + writel(data, clk_base); + do { + data = readl(clk_base + STAT_DIS_OFF); + } while (data & bitfield); +} + +#define EYE_PATTERN 0x70533483 + +int board_usb_init(int index, enum usb_init_type init) +{ + unsigned int data; + + /* enable USB clock */ + hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en); + + /* take usb IPs out of reset */ + writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY | + PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K, + &peri_sc->rst0_dis); + do { + data = readl(&peri_sc->rst0_stat); + data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY | + PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K; + } while (data); + + /*CTRL 5*/ + data = readl(&peri_sc->ctrl5); + data &= ~PERI_CTRL5_PICOPHY_BC_MODE; + data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB; + data |= 0x300; + writel(data, &peri_sc->ctrl5); + + /*CTRL 4*/ + + /* configure USB PHY */ + data = readl(&peri_sc->ctrl4); + + /* make PHY out of low power mode */ + data &= ~PERI_CTRL4_PICO_SIDDQ; + data &= ~PERI_CTRL4_PICO_OGDISABLE; + data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT; + writel(data, &peri_sc->ctrl4); + + writel(EYE_PATTERN, &peri_sc->ctrl8); + + mdelay(5); + return 0; +} + +static int config_sd_carddetect(void) +{ + int ret; + + /* configure GPIO8 as nopull */ + writel(0, 0xf8001830); + + gpio_request(8, "SD CD"); + + gpio_direction_input(8); + ret = gpio_get_value(8); + + if (!ret) { + printf("%s: SD card present\n", __func__); + return 1; + } + + printf("%s: SD card not present\n", __func__); + return 0; +} + + +static void mmc1_init_pll(void) +{ + uint32_t data; + + /* select SYSPLL as the source of MMC1 */ + /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ + writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel); + do { + data = readl(&peri_sc->clk0_sel); + } while (!(data & (1 << 11))); + + /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ + writel(1 << 30, &peri_sc->clk0_sel); + do { + data = readl(&peri_sc->clk0_sel); + } while (data & (1 << 14)); + + hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en); + + hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en); + + do { + /* 1.2GHz / 50 = 24MHz */ + writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2); + data = readl(&peri_sc->clkcfg8bit2); + } while ((data & 0x31) != 0x31); +} + +static void mmc1_reset_clk(void) +{ + unsigned int data; + + /* disable mmc1 bus clock */ + hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis); + + /* enable mmc1 bus clock */ + hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en); + + /* reset mmc1 clock domain */ + writel(PERI_RST0_MMC1, &peri_sc->rst0_en); + + /* bypass mmc1 clock phase */ + data = readl(&peri_sc->ctrl2); + data |= 3 << 2; + writel(data, &peri_sc->ctrl2); + + /* disable low power */ + data = readl(&peri_sc->ctrl13); + data |= 1 << 4; + writel(data, &peri_sc->ctrl13); + do { + data = readl(&peri_sc->rst0_stat); + } while (!(data & PERI_RST0_MMC1)); + + /* unreset mmc0 clock domain */ + writel(PERI_RST0_MMC1, &peri_sc->rst0_dis); + do { + data = readl(&peri_sc->rst0_stat); + } while (data & PERI_RST0_MMC1); +} + +/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */ +static void hi6220_pmussi_init(void) +{ + uint32_t data; + + /* Take PMUSSI out of reset */ + writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N, + &ao_sc->rst4_dis); + do { + data = readl(&ao_sc->rst4_stat); + } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N); + + /* set PMU SSI clock latency for read operation */ + data = readl(&ao_sc->mcu_subsys_ctrl3); + data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK; + data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3; + writel(data, &ao_sc->mcu_subsys_ctrl3); + + /* enable PMUSSI clock */ + data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU | + ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU; + + hi6220_clk_enable(data, &ao_sc->clk5_en); + + /* Output high to PMIC on PWR_HOLD_GPIO0_0 */ + gpio_request(0, "PWR_HOLD_GPIO0_0"); + gpio_direction_output(0, 1); +} + +int misc_init_r(void) +{ + return 0; +} + +int board_init(void) +{ + gd->flags = 0; + + return 0; +} + +#ifdef CONFIG_GENERIC_MMC + +static int init_dwmmc(void) +{ + int ret; + +#ifdef CONFIG_DWMMC + + /* mmc0 clocks are already configured by ATF */ + ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0); + if (ret) + printf("%s: Error configuring pinmux for eMMC (%d)\n" + , __func__, ret); + + ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8); + if (ret) + printf("%s: Error adding eMMC port (%d)\n", __func__, ret); + + + /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */ + mmc1_init_pll(); + mmc1_reset_clk(); + + ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1); + if (ret) + printf("%s: Error configuring pinmux for eMMC (%d)\n" + , __func__, ret); + + config_sd_carddetect(); + + ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4); + if (ret) + printf("%s: Error adding SD port (%d)\n", __func__, ret); + +#endif + return ret; +} + +/* setup board specific PMIC */ +int power_init_board(void) +{ + /* init the hi6220 pmussi ip */ + hi6220_pmussi_init(); + + power_hi6553_init((u8 *)HI6220_PMUSSI_BASE); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* add the eMMC and sd ports */ + ret = init_dwmmc(); + + if (ret) + debug("init_dwmmc failed\n"); + + return ret; +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +/* Use the Watchdog to cause reset */ +void reset_cpu(ulong addr) +{ + /* TODO program the watchdog */ +} diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig new file mode 100644 index 0000000..aa4fb0d --- /dev/null +++ b/configs/hikey_defconfig @@ -0,0 +1,5 @@ +# 96boards HiKey +CONFIG_ARM=y +CONFIG_TARGET_HIKEY=y +CONFIG_NET=y +# CONFIG_CMD_IMLS is not set diff --git a/include/configs/hikey.h b/include/configs/hikey.h new file mode 100644 index 0000000..6bb0b7d --- /dev/null +++ b/include/configs/hikey.h @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2015 Linaro + * + * Peter Griffin peter.griffin@linaro.org + * + * Configuration for HiKey 96boards CE. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HIKEY_H +#define __HIKEY_H + +/* We use generic board for hikey */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_POWER +#define CONFIG_POWER_HI6553 + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SUPPORT_RAW_INITRD + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_IDENT_STRING "hikey" + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* Physical Memory Map */ + +/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ +#define CONFIG_SYS_TEXT_BASE 0x35000000 + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 + +/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ +#define PHYS_SDRAM_1_SIZE 0x3f000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xf6801000 +#define GICC_BASE 0xf6802000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL + +#define CONFIG_PL011_CLOCK 19200000 +#define CONFIG_PL01x_PORTS {(void *)0xF8015000} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 +/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MISC_INIT_R +#endif + +#define CONFIG_HIKEY_GPIO +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_DM + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_DWMMC +#define CONFIG_HIKEY_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC + +#define CONFIG_FS_EXT4 + +/* Command line configuration */ +#define CONFIG_MENU +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_ENV + +#define CONFIG_MTD_PARTITIONS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +#include <config_distro_defaults.h> + +/* Initial environment variables */ + +/* + * Defines where the kernel and FDT will be put in RAM + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=Image\0" \ + "kernel_addr_r=0x00080000\0" \ + "fdt_name=hi6220-hikey.dtb\0" \ + "fdt_addr_r=0x02000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Assume we boot with root on the seventh partition of eMMC */ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw" + +/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "usb start; dhcp;" \ + "tftp $kernel_addr_r $kernel_name;" \ + "tftp $fdt_addr_r $fdt_name;" \ + "booti $kernel_addr_r - $fdt_addr_r" + +#define CONFIG_BOOTDELAY 2 + +/* Preserve enviroment on sd card */ +#define CONFIG_COMMAND_HISTORY + +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "1:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_NO_FLASH + +#endif /* __HIKEY_H */

To help others with compiling and flashing ATF and u-boot add a README for this board.

Signed-off-by: Peter Griffin peter.griffin@linaro.org --- board/hisilicon/hikey/README | 160 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 board/hisilicon/hikey/README

diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README new file mode 100644 index 0000000..25c8143 --- /dev/null +++ b/board/hisilicon/hikey/README @@ -0,0 +1,160 @@ +Introduction +============ + +HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: - +* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz. +* ARM Mali 450-MP4 GPU +* 1GB 800MHz LPDDR3 DRAM +* 4GB eMMC Flash Storage +* microSD +* 802.11a/b/g/n WiFi, Bluetooth + +The HiKey schematic can be found here: - +https://github.com/96boards/documentation/blob/master/hikey/96Boards-Hikey-R... + +A SoC datasheet can be found here: - +https://github.com/96boards/documentation/blob/master/hikey/ +Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf + +Currently the u-boot port supports: - +* USB +* eMMC +* SD card +* GPIO + +Compile u-boot +============== + +make CROSS_COMPILE=aarch64-linux-gnu- hikey_config +make CROSS_COMPILE=aarch64-linux-gnu- + +ARM Trusted Firmware (ATF) & l-loader +===================================== + +This u-boot port has been tested with l-loader, booting ATF, which then boots +u-boot as the bl33.bin executable. + +1. Get ATF source code +git clone https://github.com/96boards/arm-trusted-firmware.git + +2. Compile ATF I use the makefile here +http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/build-... + +3. Get l-loader +git clone https://github.com/96boards/l-loader.git + +4. Make sym links to ATF bip / fip binaries +ln -s /home/griffinp/aarch64/bl1-hikey.bin bl1.bin +ln -s /home/griffinp/aarch64/fip-hikey.bin fip.bin + +arm-linux-gnueabihf-gcc -c -o start.o start.S +arm-linux-gnueabihf-gcc -c -o debug.o debug.S +arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader +arm-linux-gnueabihf-objcopy -O binary loader temp + +python gen_loader.py -o l-loader.bin --img_loader=temp --img_bl1=bl1.bin +sudo bash -x generate_ptable.sh +python gen_loader.py -o ptable.img --img_prm_ptable=prm_ptable.img --img_sec_ptable=sec_ptable.img + +These instructions are adapted from +https://github.com/96boards/documentation/wiki/HiKeyUEFI + +FLASHING +======== + +1. Connect jumper J2 to go into recovery mode and flash l-loader.bin with + fastboot using the hisi-idt.py utility + +> git clone https://github.com/96boards/burn-boot.git +> sudo python /home/griffinp/Software/hikey/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=/tmp/l-loader.bin + +2. Once LED 0 comes on solid, it should be detected as a fastboot device + (on some boards I've found this to be unreliable) + +sudo fastboot devices + +3. Flash the images +wget https://builds.96boards.org/releases/hikey/nvme.img +sudo fastboot flash ptable ptable.img +sudo fastboot flash fastboot fip.bin +sudo fastboot flash nvme nvme.img + +4. Disconnect jumper J2, and reset the board and you will now (hopefully) + have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the + flashing twice in the past to avoid an ATF error. + +See working boot trace below: - + +debug EMMC boot: print init OK +debug EMMC boot: send RST_N . +debug EMMC boot: start eMMC boot...... +load fastboot1! +Switch to aarch64 mode. CPU0 executes at 0xf9801000! +NOTICE: Booting Trusted Firmware +NOTICE: BL1: v1.1(release):a0c0399 +NOTICE: BL1: Built : 13:23:48, May 22 2015 +NOTICE: succeed to init lpddr3 rank0 dram phy +INFO: lpddr3_freq_init, set ddrc 533mhz +INFO: init ddr3 rank0 +INFO: ddr3 rank1 init pass +INFO: lpddr3_freq_init, set ddrc 800mhz +INFO: init ddr3 rank0 +INFO: ddr3 rank1 init pass +INFO: Elpida DDR +NOTICE: BL1: Booting BL2 +INFO: [BDID] [fff91c18] midr: 0x410fd033 +INFO: [BDID] [fff91c1c] board type: 0 +INFO: [BDID] [fff91c20] board id: 0x2b +INFO: init_acpu_dvfs: pmic version 17 +INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00. +INFO: acpu_dvfs_volt_init: success! +INFO: acpu_dvfs_set_freq: support freq num is 5 +INFO: acpu_dvfs_set_freq: start prof is 0x4 +INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5 +INFO: acpu_dvfs_set_freq: voltage: +INFO: - 0: 0x3a +INFO: - 1: 0x3a +INFO: - 2: 0x4a +INFO: - 3: 0x5b +INFO: - 4: 0x6b +NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):a0c0399 +NOTICE: BL2: Built : 10:19:28, May 27 2015 +INFO: BL2: Loading BL3-0 +INFO: Using FIP +WARNING: Failed to access image 'bl30.bin' (-1) +ERROR: Failed to load BL3-0 (-1) +ERROR: Please burn mcu image: +ERROR: sudo fastboot flash mcuimage mcuimage.bin +INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000 +INFO: BL2: Loading BL3-1 +INFO: Using FIP +INFO: Loading file 'bl31.bin' at address 0xf9858000 +INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9860010 +INFO: BL2: Loading BL3-2 +INFO: Using FIP +WARNING: Failed to access image 'bl32.bin' (-1) +WARNING: Failed to load BL3-2 (-1) +INFO: BL2: Loading BL3-3 +INFO: Using FIP +INFO: Loading file 'bl33.bin' at address 0x35000000 +INFO: File 'bl33.bin' loaded: 0x35000000 - 0x35042938 +NOTICE: BL1: Booting BL3-1 +NOTICE: BL3-1: v1.1(debug):a0c0399 +NOTICE: BL3-1: Built : 10:19:31, May 27 2015 +INFO: BL3-1: Initializing runtime services +INFO: BL3-1: Preparing for EL3 exit to normal world +INFO: BL3-1: Next image address = 0x35000000 +INFO: BL3-1: Next image spsr = 0x3c9 + + +U-Boot 2015.04-00007-g1b3d379-dirty (May 27 2015 - 10:18:16) hikey + +DRAM: 1008 MiB +MMC: sd_card_detect: SD card present +HiKey DWMMC: 0, HiKey DWMMC: 1 +In: serial +Out: serial +Err: serial +Net: Net Initialization Skipped +No ethernet found. +Hit any key to stop autoboot: 0