Hello Hans,

Am 04.04.2015 14:13, schrieb Hans de Goede:

Hi,

On 04-04-15 13:27, Paul Kocialkowski wrote:

...

Orion5x, Kirkwood and Armada XP platforms come with a single TWSI (I2C) MVTWSI controller. However, other platforms using MVTWSI may come with more: this is the case on Allwinner (sunxi) platforms, where up to 4 controllers can be found on the same chip.

Signed-off-by: Paul Kocialkowski contact@paulk.fr

Looks good to me:

Acked-by: Hans de Goede hdegoede@redhat.com

Heiko can you pick this one up please ? The second patch will likely cause conflicts in the sunxi tree so I will pack that one up once you've merged the first one, also I've some review remarks for the second patch so that needs to be respun.

No need to wait for me, please pick up the hole series. I look through the patch, and send my comments (now for v3). Then you can pick up this patches through your sunxi tree.

bye, Heiko

Regards,

Hans

...

---

arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- drivers/i2c/mvtwsi.c | 124 ++++++++++++++++++++------- include/configs/db-mv784mp-gp.h | 2 +- include/configs/edminiv2.h | 2 +- include/configs/maxbcm.h | 2 +- 6 files changed, 100 insertions(+), 34 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index dc5406b..502e3c6 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -8,7 +8,7 @@

#include <asm/arch/cpu.h>

-#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE +#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000

diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index e77ac40..d049395 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -44,7 +44,7 @@ #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 #define CONFIG_NR_DRAM_BANKS_MAX 2

-#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE #define MV_UART_CONSOLE_BASE KW_UART0_BASE #define MV_SATA_BASE KW_SATA_BASE #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 6f6edd5..331d73c 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -14,7 +14,7 @@ #include <asm/io.h>

/*

• • include a file that will provide CONFIG_I2C_MVTWSI_BASE

• • include a file that will provide CONFIG_I2C_MVTWSI_BASE*
  • and possibly other settings
  */

@@ -91,11 +91,37 @@ struct mvtwsi_registers { #define MVTWSI_STATUS_IDLE 0xF8

/*

• • The single instance of the controller we'll be dealing with

• • MVTWSI controller base
  */

-static struct mvtwsi_registers *twsi =

• (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE;

+static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) +{

• switch (adap->hwadapnr) {
• case 0:

•    return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
  

+#ifdef CONFIG_I2C_MVTWSI_BASE1

• case 1:

•    return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
  

+#endif +#ifdef CONFIG_I2C_MVTWSI_BASE2

• case 2:

•    return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
  

+#endif +#ifdef CONFIG_I2C_MVTWSI_BASE3

• case 3:

•    return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
  

+#endif +#ifdef CONFIG_I2C_MVTWSI_BASE4

• case 4:

•    return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
  

+#endif

• default:

•    printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
  

•    break;
  

• }
• return NULL;

+}

/*

• Returned statuses are 0 for success and nonzero otherwise.

@@ -117,8 +143,9 @@ static struct mvtwsi_registers *twsi =

• Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
• return 0 (ok) or return 'wrong status'.

*/ -static int twsi_wait(int expected_status) +static int twsi_wait(struct i2c_adapter *adap, int expected_status) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap); int control, status; int timeout = 1000;

@@ -153,35 +180,40 @@ static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;

• Assert the START condition, either in a single I2C transaction
• or inside back-to-back ones (repeated starts).

*/ -static int twsi_start(int expected_status) +static int twsi_start(struct i2c_adapter *adap, int expected_status) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap);

• /* globally set TWSIEN in case it was not */
  twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
  /* assert START */
  writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
  /* wait for controller to process START */
  

• return twsi_wait(expected_status);

• return twsi_wait(adap, expected_status); }

  /*

  • Send a byte (i2c address or data).

  */

-static int twsi_send(u8 byte, int expected_status) +static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap);

• /* put byte in data register for sending */
  writel(byte, &twsi->data);
  /* clear any pending interrupt -- that'll cause sending */
  writel(twsi_control_flags, &twsi->control);
  /* wait for controller to receive byte and check ACK */
  

• return twsi_wait(expected_status);

• return twsi_wait(adap, expected_status); }

  /*

  • Receive a byte.
  • Global mvtwsi_control_flags variable says if we should ack or nak.

  */

-static int twsi_recv(u8 *byte) +static int twsi_recv(struct i2c_adapter *adap, u8 *byte) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap); int expected_status, status;

  /* compute expected status based on ACK bit in global control flags */

@@ -192,7 +224,7 @@ static int twsi_recv(u8 *byte) /* acknowledge *previous state* and launch receive */ writel(twsi_control_flags, &twsi->control); /* wait for controller to receive byte and assert ACK or NAK */

• status = twsi_wait(expected_status);

• status = twsi_wait(adap, expected_status); /* if we did receive expected byte then store it */ if (status == 0) *byte = readl(&twsi->data);

@@ -204,8 +236,9 @@ static int twsi_recv(u8 *byte)

• Assert the STOP condition.
• This is also used to force the bus back in idle (SDA=SCL=1).

*/ -static int twsi_stop(int status) +static int twsi_stop(struct i2c_adapter *adap, int status) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap); int control, stop_status; int timeout = 1000;

@@ -244,6 +277,7 @@ static unsigned int twsi_calc_freq(const int n, const int m) */ static void twsi_reset(struct i2c_adapter *adap) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap); /* ensure controller will be enabled by any twsi*() function */ twsi_control_flags = MVTWSI_CONTROL_TWSIEN; /* reset controller */

@@ -259,6 +293,7 @@ static void twsi_reset(struct i2c_adapter *adap) static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int requested_speed) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap); unsigned int tmp_speed, highest_speed, n, m; unsigned int baud = 0x44; /* baudrate at controller reset */

@@ -281,6 +316,8 @@ static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,

static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) {

• struct mvtwsi_registers *twsi = twsi_get_base(adap);

• /* reset controller */
  twsi_reset(adap);
  /* set speed */
  

@@ -289,7 +326,7 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) writel(slaveadd, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); /* assert STOP but don't care for the result */

• (void) twsi_stop(0);

• (void) twsi_stop(adap, 0); }

  /*

@@ -297,7 +334,8 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)

• Common to i2c_probe, i2c_read and i2c_write.
• Expected address status will derive from direction bit (bit 0) in addr.

*/ -static int i2c_begin(int expected_start_status, u8 addr) +static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,

•         u8 addr)
  

  { int status, expected_addr_status;

@@ -307,10 +345,10 @@ static int i2c_begin(int expected_start_status, u8 addr) else /* writing */ expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; /* assert START */

• status = twsi_start(expected_start_status);

• status = twsi_start(adap, expected_start_status); /* send out the address if the start went well */ if (status == 0)

•    status = twsi_send(addr, expected_addr_status);
  

•    status = twsi_send(adap, addr, expected_addr_status);
  /* return ok or status of first failure to caller */
  return status;
  

  }

@@ -325,12 +363,12 @@ static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) int status;

  /* begin i2c read */

• status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1);

• status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1); /* dummy read was accepted: receive byte but NAK it. */ if (status == 0)

•    status = twsi_recv(&dummy_byte);
  

•    status = twsi_recv(adap, &dummy_byte);
  /* Stop transaction */
  

• twsi_stop(0);

• twsi_stop(adap, 0); /* return 0 or status of first failure */ return status; }

@@ -351,15 +389,15 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, int status;

  /* begin i2c write to send the address bytes */

• status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));

• status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1)); /* send addr bytes */ while ((status == 0) && alen--)

•    status = twsi_send(addr >> (8*alen),
  

•    status = twsi_send(adap, addr >> (8*alen),
          MVTWSI_STATUS_DATA_W_ACK);
  /* begin i2c read to receive eeprom data bytes */
  if (status == 0)
  

•    status = i2c_begin(
  

•        MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1);
  

•    status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
  

•               (chip << 1) | 1);
  /* prepare ACK if at least one byte must be received */
  if (length > 0)
      twsi_control_flags |= MVTWSI_CONTROL_ACK;
  

@@ -369,10 +407,10 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, if (length == 0) twsi_control_flags &= ~MVTWSI_CONTROL_ACK; /* read current byte */

•    status = twsi_recv(data++);
  

•    status = twsi_recv(adap, data++);
  }
  /* Stop transaction */
  

• status = twsi_stop(status);

• status = twsi_stop(adap, status); /* return 0 or status of first failure */ return status; }

@@ -387,16 +425,16 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int status;

  /* begin i2c write to send the eeprom adress bytes then data bytes */

• status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));

• status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1)); /* send addr bytes */ while ((status == 0) && alen--)

•    status = twsi_send(addr >> (8*alen),
  

•    status = twsi_send(adap, addr >> (8*alen),
          MVTWSI_STATUS_DATA_W_ACK);
  /* send data bytes */
  while ((status == 0) && (length-- > 0))
  

•    status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK);
  

•    status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
  /* Stop transaction */
  

• status = twsi_stop(status);

• status = twsi_stop(adap, status); /* return 0 or status of first failure */ return status; }

@@ -405,3 +443,31 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_read, twsi_i2c_write, twsi_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) +#ifdef CONFIG_I2C_MVTWSI_BASE1 +U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,

•         twsi_i2c_read, twsi_i2c_write,
  

•         twsi_i2c_set_bus_speed,
  

•         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
  

+#endif +#ifdef CONFIG_I2C_MVTWSI_BASE2 +U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,

•         twsi_i2c_read, twsi_i2c_write,
  

•         twsi_i2c_set_bus_speed,
  

•         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
  

+#endif +#ifdef CONFIG_I2C_MVTWSI_BASE3 +U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,

•         twsi_i2c_read, twsi_i2c_write,
  

•         twsi_i2c_set_bus_speed,
  

•         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
  

+#endif +#ifdef CONFIG_I2C_MVTWSI_BASE4 +U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,

•         twsi_i2c_read, twsi_i2c_write,
  

•         twsi_i2c_set_bus_speed,
  

•         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
  

+#endif diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 1683a15..4dd7b11 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -37,7 +37,7 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000

diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 5ce01fb..bd08740 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -208,7 +208,7 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 #endif diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 5999d60..e909623 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -35,7 +35,7 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000

Hi,

On 04-04-15 13:27, Paul Kocialkowski wrote:

Sunxi platforms come with at least 3 TWI (I2C) controllers and some platforms even have up to 5. This adds support for every controller on each supported platform, which is especially useful when using expansion ports on single-board- computers.

Signed-off-by: Paul Kocialkowski contact@paulk.fr

Looks good in general, see comments inline for some minor things which need fixing.

---

arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++ arch/arm/include/asm/arch-sunxi/gpio.h | 15 ++++++- arch/arm/include/asm/arch-sunxi/i2c.h | 9 ++++ board/sunxi/board.c | 67 ++++++++++++++++++++++++++++- 4 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index dae6069..f403742 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -94,6 +94,13 @@ #define SUNXI_TWI0_BASE 0x01c2ac00 #define SUNXI_TWI1_BASE 0x01c2b000 #define SUNXI_TWI2_BASE 0x01c2b400 +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_TWI3_BASE 0x01c0b800 +#endif +#ifdef CONFIG_MACH_SUN7I +#define SUNXI_TWI3_BASE 0x01c2b800 +#define SUNXI_TWI4_BASE 0x01c2c000 +#endif

#define SUNXI_CAN_BASE 0x01c2bc00

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f227044..ae7cbb7 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -148,7 +148,11 @@ enum sunxi_gpio_number { #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4

-#define SUNXI_GPB_TWI0 2 +#define SUN4I_GPB_TWI0 2 +#define SUN4I_GPB_TWI1 2 +#define SUN5I_GPB_TWI1 2 +#define SUN4I_GPB_TWI2 2 +#define SUN5I_GPB_TWI2 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2

@@ -160,6 +164,7 @@ enum sunxi_gpio_number { #define SUNXI_GPD_LVDS0 3

#define SUN5I_GPE_SDC2 3 +#define SUN8I_GPE_TWI2 3

#define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 @@ -169,12 +174,20 @@ enum sunxi_gpio_number { #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 +#define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4

#define SUN4I_GPH_SDC1 5 +#define SUN6I_GPH_TWI0 2 +#define SUN8I_GPH_TWI0 2 +#define SUN6I_GPH_TWI1 2 +#define SUN8I_GPH_TWI1 2 +#define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2

#define SUNXI_GPI_SDC3 2 +#define SUN7I_GPI_TWI3 3 +#define SUN7I_GPI_TWI4 3

#define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 502e3c6..5bec18c 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -9,6 +9,15 @@ #include <asm/arch/cpu.h>

#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE +#ifdef SUNXI_TWI3_BASE +#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE +#endif +#ifdef SUNXI_TWI4_BASE +#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE +#endif

• /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000

This will cause us to register all possible i2c controllers for each soc, but they might very well not be hooked up to anything, and the pins of the SoC the code below will now mux to i2c may even be used for something else, so this needs to be activated by a Kconfig option (one per i2c controller).

diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 7633d65..b3eecbb 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -276,9 +276,72 @@ int board_mmc_init(bd_t *bis)

void i2c_init_board(void) {

• sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB_TWI0);

+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1);

+#elif defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
• clock_twi_onoff(0, 1);

+#elif defined(CONFIG_MACH_SUN8I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
• clock_twi_onoff(0, 1);

+#endif

+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
• clock_twi_onoff(1, 1);

+#elif defined(CONFIG_MACH_SUN5I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
• clock_twi_onoff(1, 1);

+#elif defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
• clock_twi_onoff(1, 1);

+#elif defined(CONFIG_MACH_SUN8I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
• clock_twi_onoff(1, 1);

+#endif

+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
• clock_twi_onoff(2, 1);

+#elif defined(CONFIG_MACH_SUN5I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
• clock_twi_onoff(2, 1);

+#elif defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
• clock_twi_onoff(2, 1);

+#elif defined(CONFIG_MACH_SUN8I)

• sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
• clock_twi_onoff(2, 1);

+#endif

+#if defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
• sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
• clock_twi_onoff(3, 1);

+#elif defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
• sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
• clock_twi_onoff(3, 1);

+#endif

+#if defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
• sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
• clock_twi_onoff(4, 1);

+#endif

Idem you are muxing pins here which may be used by something else, and if they are not then they are best left as generic inputs rather then configured as i2c pins, except when we know that there actually is an i2c bus connected.

#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);

Regards,

Hans

Hi,

On 04-04-15 14:54, Paul Kocialkowski wrote:

Hi Hans,

Le samedi 04 avril 2015 à 14:18 +0200, Hans de Goede a écrit :

...

On 04-04-15 13:27, Paul Kocialkowski wrote:

...

Sunxi platforms come with at least 3 TWI (I2C) controllers and some platforms even have up to 5. This adds support for every controller on each supported platform, which is especially useful when using expansion ports on single-board- computers.

Signed-off-by: Paul Kocialkowski contact@paulk.fr

Looks good in general, see comments inline for some minor things which need fixing.

Thanks for the review!

...

...

---

arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++ arch/arm/include/asm/arch-sunxi/gpio.h | 15 ++++++- arch/arm/include/asm/arch-sunxi/i2c.h | 9 ++++ board/sunxi/board.c | 67 ++++++++++++++++++++++++++++- 4 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index dae6069..f403742 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -94,6 +94,13 @@ #define SUNXI_TWI0_BASE 0x01c2ac00 #define SUNXI_TWI1_BASE 0x01c2b000 #define SUNXI_TWI2_BASE 0x01c2b400 +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_TWI3_BASE 0x01c0b800 +#endif +#ifdef CONFIG_MACH_SUN7I +#define SUNXI_TWI3_BASE 0x01c2b800 +#define SUNXI_TWI4_BASE 0x01c2c000 +#endif

#define SUNXI_CAN_BASE 0x01c2bc00

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f227044..ae7cbb7 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -148,7 +148,11 @@ enum sunxi_gpio_number { #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4

-#define SUNXI_GPB_TWI0 2 +#define SUN4I_GPB_TWI0 2 +#define SUN4I_GPB_TWI1 2 +#define SUN5I_GPB_TWI1 2 +#define SUN4I_GPB_TWI2 2 +#define SUN5I_GPB_TWI2 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2

@@ -160,6 +164,7 @@ enum sunxi_gpio_number { #define SUNXI_GPD_LVDS0 3

#define SUN5I_GPE_SDC2 3 +#define SUN8I_GPE_TWI2 3

#define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 @@ -169,12 +174,20 @@ enum sunxi_gpio_number { #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 +#define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4

#define SUN4I_GPH_SDC1 5 +#define SUN6I_GPH_TWI0 2 +#define SUN8I_GPH_TWI0 2 +#define SUN6I_GPH_TWI1 2 +#define SUN8I_GPH_TWI1 2 +#define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2

#define SUNXI_GPI_SDC3 2 +#define SUN7I_GPI_TWI3 3 +#define SUN7I_GPI_TWI4 3

#define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 502e3c6..5bec18c 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -9,6 +9,15 @@ #include <asm/arch/cpu.h>

#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE +#ifdef SUNXI_TWI3_BASE +#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE +#endif +#ifdef SUNXI_TWI4_BASE +#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE +#endif

• /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000

This will cause us to register all possible i2c controllers for each soc, but they might very well not be hooked up to anything, and the pins of the SoC the code below will now mux to i2c may even be used for something else, so this needs to be activated by a Kconfig option (one per i2c controller).

I agree, I also had this thought on the back of my mind and wasn't sure whether to do anything about it. I'll submit v2 ASAP.

What would the preferred form for the Kconfig options be? I suggest using CONFIG_I2C1_ENABLE or CONFIG_SUNXI_I2C1_ENABLE (preferable the latter, but I don't see much SUNXI prefixing being done in board/sunxi/Kconfig).

I've no preference for the Kconfig name, as for submitting v2 ASAP, I will not merge this until Heiko has merged the first patch which will not happen until v2015.04 is released and the new merge window opens, so no hurry, unless you want to get this of your plate :)

Regards,

Hans

...

...

diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 7633d65..b3eecbb 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -276,9 +276,72 @@ int board_mmc_init(bd_t *bis)

void i2c_init_board(void) {

• sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB_TWI0);

+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); clock_twi_onoff(0, 1);

+#elif defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
• clock_twi_onoff(0, 1);

+#elif defined(CONFIG_MACH_SUN8I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
• clock_twi_onoff(0, 1);

+#endif

+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
• clock_twi_onoff(1, 1);

+#elif defined(CONFIG_MACH_SUN5I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
• clock_twi_onoff(1, 1);

+#elif defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
• clock_twi_onoff(1, 1);

+#elif defined(CONFIG_MACH_SUN8I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
• clock_twi_onoff(1, 1);

+#endif

+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
• clock_twi_onoff(2, 1);

+#elif defined(CONFIG_MACH_SUN5I)

• sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
• clock_twi_onoff(2, 1);

+#elif defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
• clock_twi_onoff(2, 1);

+#elif defined(CONFIG_MACH_SUN8I)

• sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
• sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
• clock_twi_onoff(2, 1);

+#endif

+#if defined(CONFIG_MACH_SUN6I)

• sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
• sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
• clock_twi_onoff(3, 1);

+#elif defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
• sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
• clock_twi_onoff(3, 1);

+#endif

+#if defined(CONFIG_MACH_SUN7I)

• sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
• sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
• clock_twi_onoff(4, 1);

+#endif

Idem you are muxing pins here which may be used by something else, and if they are not then they are best left as generic inputs rather then configured as i2c pins, except when we know that there actually is an i2c bus connected.

Ack

...

...

#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);

Regards,

Hans