[U-Boot] [PATCH v3 0/9] enable thumb for tegra20
Add changes necessary to enable thumb compilation for tegra20. This series includes two patches to work around a bug in gas that incorrectly optimizes short jumps in thumb mode that were posted separately. They can be dropped from this series when they are applied.
This patch series is also available from: git://github.com/arm000/u-boot.git branch: tegra-thumb-v3
Changes: v3: - rebased on top of v8 of SPL series - added linkage macro patch to _thumb1_case_uqu from Stephen Warren
Allen Martin (9): tools, config.mk: add binutils-version arm: work around assembler bug tegra20: remove inline assembly for u32 cast arm: add _thumb1_case_uqi to libgcc arm: use thumb compatible return in arm720t arm: change arm720t to armv4t arm720t: add linkage macro for relocate_code arm: use thumb interworking returns in libgcc tegra20: enable thumb build
arch/arm/config.mk | 18 ++++++++++++ arch/arm/cpu/arm720t/config.mk | 2 +- arch/arm/cpu/arm720t/start.S | 7 +++-- arch/arm/cpu/arm720t/tegra20/config.mk | 7 +++++ arch/arm/cpu/tegra20-common/warmboot_avp.c | 9 +----- arch/arm/include/asm/assembler.h | 10 +++++++ arch/arm/lib/Makefile | 1 + arch/arm/lib/_ashldi3.S | 3 +- arch/arm/lib/_ashrdi3.S | 3 +- arch/arm/lib/_divsi3.S | 15 +++++++--- arch/arm/lib/_lshrdi3.S | 3 +- arch/arm/lib/_modsi3.S | 9 +++++- arch/arm/lib/{_ashrdi3.S => _thumb1_case_uqi.S} | 36 ++++++++++------------- arch/arm/lib/_udivsi3.S | 8 +++-- arch/arm/lib/_umodsi3.S | 18 +++++++++++- arch/arm/lib/memcpy.S | 10 +++++++ arch/arm/lib/memset.S | 3 +- config.mk | 1 + include/configs/tegra20-common.h | 1 + tools/binutils-version.sh | 20 +++++++++++++ 20 files changed, 138 insertions(+), 46 deletions(-) copy arch/arm/lib/{_ashrdi3.S => _thumb1_case_uqi.S} (81%) create mode 100755 tools/binutils-version.sh
Modeled after gcc-version, add function to get binutils version.
Signed-off-by: Allen Martin amartin@nvidia.com --- config.mk | 1 + tools/binutils-version.sh | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100755 tools/binutils-version.sh
diff --git a/config.mk b/config.mk index 3dcea6a..919b77d 100644 --- a/config.mk +++ b/config.mk @@ -128,6 +128,7 @@ endif # cc-version # Usage gcc-ver := $(call cc-version) cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC)) +binutils-version = $(shell $(SHELL) $(SRCTREE)/tools/binutils-version.sh $(AS))
# # Include the make variables (CC, etc...) diff --git a/tools/binutils-version.sh b/tools/binutils-version.sh new file mode 100755 index 0000000..d4d9eb4 --- /dev/null +++ b/tools/binutils-version.sh @@ -0,0 +1,20 @@ +#!/bin/sh +# +# binutils-version [-p] gas-command +# +# Prints the binutils version of `gas-command' in a canonical 4-digit form +# such as `0222' for binutils 2.22 +# + +gas="$*" + +if [ ${#gas} -eq 0 ]; then + echo "Error: No assembler specified." + printf "Usage:\n\t$0 <gas-command>\n" + exit 1 +fi + +MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1) +MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2) + +printf "%02d%02d\n" $MAJOR $MINOR
Dear Allen Martin,
In message 1345066741-19613-2-git-send-email-amartin@nvidia.com you wrote:
Modeled after gcc-version, add function to get binutils version.
Signed-off-by: Allen Martin amartin@nvidia.com
config.mk | 1 + tools/binutils-version.sh | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100755 tools/binutils-version.sh
As this is part of a series that will go through the tegra / arm trees:
Acked-by: Wolfgang Denk wd@denx.de
Best regards,
Wolfgang Denk
On Sun, Sep 02, 2012 at 08:05:11AM -0700, Wolfgang Denk wrote:
Dear Allen Martin,
In message 1345066741-19613-2-git-send-email-amartin@nvidia.com you wrote:
Modeled after gcc-version, add function to get binutils version.
Signed-off-by: Allen Martin amartin@nvidia.com
config.mk | 1 + tools/binutils-version.sh | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100755 tools/binutils-version.sh
As this is part of a series that will go through the tegra / arm trees:
Acked-by: Wolfgang Denk wd@denx.de
I'm carrying it in this series because I hit the assembler bug that this works around, but I also posted it as a separate patch (2 patches actually, this one and "arm: work around assembler bug"). I'm fine with just carrying it in this series if that's preferred, since I seem to be the only one hitting this when I enable thumb for tegra.
-Allen
Disable sibling call optimization based on binutils version. This is to work around a bug in the assember in binutils versions < 2.22. Branches to weak symbols can be incorrectly optimized in thumb mode to a short branch (b.n instruction) that won't reach when the symbol gets preempted.
http://sourceware.org/bugzilla/show_bug.cgi?id=12532
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/config.mk | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 3f4453a..24b9d7c 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -87,3 +87,21 @@ endif ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie endif + +# +# FIXME: binutils versions < 2.22 have a bug in the assembler where +# branches to weak symbols can be incorrectly optimized in thumb mode +# to a short branch (b.n instruction) that won't reach when the symbol +# gets preempted +# +# http://sourceware.org/bugzilla/show_bug.cgi?id=12532 +# +ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +ifeq ($(GAS_BUG_12532),) +export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ + then echo y; else echo n; fi) +endif +ifeq ($(GAS_BUG_12532),y) +PLATFORM_RELFLAGS += -fno-optimize-sibling-calls +endif +endif
Dear Allen Martin,
Disable sibling call optimization based on binutils version. This is to work around a bug in the assember in binutils versions < 2.22. Branches to weak symbols can be incorrectly optimized in thumb mode to a short branch (b.n instruction) that won't reach when the symbol gets preempted.
CC Albert ... Albert, let's pull this in as a part of this series.
I'm fine with it.
http://sourceware.org/bugzilla/show_bug.cgi?id=12532
Signed-off-by: Allen Martin amartin@nvidia.com
arch/arm/config.mk | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 3f4453a..24b9d7c 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -87,3 +87,21 @@ endif ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie endif
+# +# FIXME: binutils versions < 2.22 have a bug in the assembler where +# branches to weak symbols can be incorrectly optimized in thumb mode +# to a short branch (b.n instruction) that won't reach when the symbol +# gets preempted +# +# http://sourceware.org/bugzilla/show_bug.cgi?id=12532 +# +ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +ifeq ($(GAS_BUG_12532),) +export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
- then echo y; else echo n; fi)
+endif +ifeq ($(GAS_BUG_12532),y) +PLATFORM_RELFLAGS += -fno-optimize-sibling-calls +endif +endif
Best regards, Marek Vasut
This inline assembly just converts a function address to a u32. Replace it with equivalent C code since the assembly was not thumb compatible.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/tegra20-common/warmboot_avp.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index cd01908..0a7f09f 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -51,14 +51,7 @@ void wb_start(void) /* enable JTAG & TBE */ writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
- /* Are we running where we're supposed to be? */ - asm volatile ( - "adr %0, wb_start;" /* reg: wb_start address */ - : "=r"(reg) /* output */ - /* no input, no clobber list */ - ); - - if (reg != AP20_WB_RUN_ADDRESS) + if ((u32)wb_start != AP20_WB_RUN_ADDRESS) goto do_reset;
/* Are we running with AVP? */
Add function required by some thumb switch statements
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/lib/Makefile | 1 + arch/arm/lib/_thumb1_case_uqi.S | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 arch/arm/lib/_thumb1_case_uqi.S
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index bd3b77f..a54f831 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,6 +33,7 @@ GLSOBJS += _lshrdi3.o GLSOBJS += _modsi3.o GLSOBJS += _udivsi3.o GLSOBJS += _umodsi3.o +GLSOBJS += _thumb1_case_uqi.o
GLCOBJS += div0.o
diff --git a/arch/arm/lib/_thumb1_case_uqi.S b/arch/arm/lib/_thumb1_case_uqi.S new file mode 100644 index 0000000..a4241f6 --- /dev/null +++ b/arch/arm/lib/_thumb1_case_uqi.S @@ -0,0 +1,42 @@ +/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include <linux/linkage.h> + + .force_thumb + .syntax unified +ENTRY(__gnu_thumb1_case_uqi) + push {r1} + mov r1, lr + lsrs r1, r1, #1 + lsls r1, r1, #1 + ldrb r1, [r1, r0] + lsls r1, r1, #1 + add lr, lr, r1 + pop {r1} + bx lr +ENDPROC(__gnu_thumb1_case_uqi)
Convert return from relocate_code to a thumb compatible bx instruction.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/arm720t/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 2f914e9..013da46 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -268,7 +268,7 @@ clbss_e: mov r0, r5 /* gd_t */ mov r1, r6 /* dest_addr */ /* jump to it ... */ - mov pc, lr + bx lr
_board_init_r_ofs: .word board_init_r - _start
arm720t is an armv4t not an armv4. Force some tegra initialization functions to arm mode because they contain arm only inline assembly.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/arm720t/config.mk | 2 +- arch/arm/cpu/arm720t/tegra20/config.mk | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 210c6dc..1f8aa95 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -24,7 +24,7 @@
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi +PLATFORM_CPPFLAGS += -march=armv4t -mtune=arm7tdmi # ========================================================================= # # Supply options according to compiler version diff --git a/arch/arm/cpu/arm720t/tegra20/config.mk b/arch/arm/cpu/arm720t/tegra20/config.mk index 62a31d8..af63fcb 100644 --- a/arch/arm/cpu/arm720t/tegra20/config.mk +++ b/arch/arm/cpu/arm720t/tegra20/config.mk @@ -24,3 +24,10 @@ # MA 02111-1307 USA # USE_PRIVATE_LIBGCC = yes + +# +# THUMB1 doesn't allow mrc/mcr instructions, so need to force +# these files to ARM mode +# +CFLAGS_arch/arm/cpu/tegra20-common/ap20.o += -marm +CFLAGS_arch/arm/lib/cache-cp15.o += -marm
The linker needs this to understand that the symbol is actually a function so it will generate correct thumb interworking code.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/cpu/arm720t/start.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 013da46..b110bf7 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -27,6 +27,7 @@ #include <config.h> #include <version.h> #include <asm/hardware.h> +#include <linux/linkage.h>
/* ************************************************************************* @@ -171,8 +172,7 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code -relocate_code: +ENTRY(relocate_code) mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ @@ -279,6 +279,7 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start +ENDPROC(relocate_code)
/* *************************************************************************
If CONFIG_SYS_THUMB_BUILD is enabled, use thumb interworking return instructions from libgcc routines, otherwise use ARM returns.
Signed-off-by: Allen Martin amartin@nvidia.com --- arch/arm/include/asm/assembler.h | 10 ++++++++++ arch/arm/lib/_ashldi3.S | 3 ++- arch/arm/lib/_ashrdi3.S | 3 ++- arch/arm/lib/_divsi3.S | 15 +++++++++++---- arch/arm/lib/_lshrdi3.S | 3 ++- arch/arm/lib/_modsi3.S | 9 ++++++++- arch/arm/lib/_udivsi3.S | 8 +++++--- arch/arm/lib/_umodsi3.S | 18 +++++++++++++++++- arch/arm/lib/memcpy.S | 10 ++++++++++ arch/arm/lib/memset.S | 3 ++- 10 files changed, 69 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 5e4789b..25ece01 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -13,6 +13,7 @@ * Do not include any C declarations in this file - it is included by * assembler source. */ +#include <config.h>
/* * Endian independent macros for shifting bytes within registers. @@ -58,3 +59,12 @@ * Cache alligned */ #define CALGN(code...) code + +/* + * return instruction + */ +#ifdef CONFIG_SYS_THUMB_BUILD +#define RET bx lr +#else +#define RET mov pc, lr +#endif diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/_ashldi3.S index 834ddc2..e280f26 100644 --- a/arch/arm/lib/_ashldi3.S +++ b/arch/arm/lib/_ashldi3.S @@ -25,6 +25,7 @@ along with this program; see the file COPYING. If not, write to the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */
+#include <asm/assembler.h>
#ifdef __ARMEB__ #define al r1 @@ -45,4 +46,4 @@ __aeabi_llsl: movpl ah, al, lsl r3 orrmi ah, ah, al, lsr ip mov al, al, lsl r2 - mov pc, lr + RET diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S index 671ac87..3edda9f 100644 --- a/arch/arm/lib/_ashrdi3.S +++ b/arch/arm/lib/_ashrdi3.S @@ -25,6 +25,7 @@ along with this program; see the file COPYING. If not, write to the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */
+#include <asm/assembler.h>
#ifdef __ARMEB__ #define al r1 @@ -45,4 +46,4 @@ __aeabi_lasr: movpl al, ah, asr r3 orrmi al, al, ah, lsl ip mov ah, ah, asr r2 - mov pc, lr + RET diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S index cfbadb2..ab59d78 100644 --- a/arch/arm/lib/_divsi3.S +++ b/arch/arm/lib/_divsi3.S @@ -1,3 +1,5 @@ +#include <config.h> +#include <asm/assembler.h>
.macro ARM_DIV_BODY dividend, divisor, result, curbit
@@ -116,27 +118,32 @@ __aeabi_idiv:
cmp ip, #0 rsbmi r0, r0, #0 - mov pc, lr + RET
10: teq ip, r0 @ same sign ? rsbmi r0, r0, #0 - mov pc, lr + RET
11: movlo r0, #0 moveq r0, ip, asr #31 orreq r0, r0, #1 - mov pc, lr + RET
12: ARM_DIV2_ORDER r1, r2
cmp ip, #0 mov r0, r3, lsr r2 rsbmi r0, r0, #0 - mov pc, lr + RET
Ldiv0:
str lr, [sp, #-4]! bl __div0 mov r0, #0 @ About as wrong as it could be. +#ifdef CONFIG_SYS_THUMB_BUILD + ldr lr, [sp], #4 + bx lr +#else ldr pc, [sp], #4 +#endif diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S index e7fa799..4d7784d 100644 --- a/arch/arm/lib/_lshrdi3.S +++ b/arch/arm/lib/_lshrdi3.S @@ -25,6 +25,7 @@ along with this program; see the file COPYING. If not, write to the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */
+#include <asm/assembler.h>
#ifdef __ARMEB__ #define al r1 @@ -45,4 +46,4 @@ __aeabi_llsr: movpl al, ah, lsr r3 orrmi al, al, ah, lsl ip mov ah, ah, lsr r2 - mov pc, lr + RET diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S index 539c584..9c7ce8c 100644 --- a/arch/arm/lib/_modsi3.S +++ b/arch/arm/lib/_modsi3.S @@ -1,3 +1,5 @@ +#include <config.h> +#include <asm/assembler.h>
.macro ARM_MOD_BODY dividend, divisor, order, spare
@@ -88,7 +90,7 @@ __modsi3:
10: cmp ip, #0 rsbmi r0, r0, #0 - mov pc, lr + RET
Ldiv0: @@ -96,4 +98,9 @@ Ldiv0: str lr, [sp, #-4]! bl __div0 mov r0, #0 @ About as wrong as it could be. +#ifdef CONFIG_SYS_THUMB_BUILD + ldr lr, [sp], #4 + bx lr +#else ldr pc, [sp], #4 +#endif diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S index 1309802..09a1664 100644 --- a/arch/arm/lib/_udivsi3.S +++ b/arch/arm/lib/_udivsi3.S @@ -1,3 +1,5 @@ +#include <asm/assembler.h> + /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) @@ -64,7 +66,7 @@ Loop3: bne Loop3 Lgot_result: mov r0, result - mov pc, lr + RET Ldiv0: str lr, [sp, #-4]! bl __div0 (PLT) @@ -80,7 +82,7 @@ __aeabi_uidivmod: ldmfd sp!, {r1, r2, ip, lr} mul r3, r0, r2 sub r1, r1, r3 - mov pc, lr + RET
.globl __aeabi_idivmod __aeabi_idivmod: @@ -90,4 +92,4 @@ __aeabi_idivmod: ldmfd sp!, {r1, r2, ip, lr} mul r3, r0, r2 sub r1, r1, r3 - mov pc, lr + RET diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S index 8465ef0..93eadf9 100644 --- a/arch/arm/lib/_umodsi3.S +++ b/arch/arm/lib/_umodsi3.S @@ -1,3 +1,6 @@ +#include <config.h> +#include <asm/assembler.h> + /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) @@ -19,7 +22,11 @@ curbit .req r3 beq Ldiv0 mov curbit, #1 cmp dividend, divisor +#ifdef CONFIG_SYS_THUMB_BUILD + bxcc lr +#else movcc pc, lr +#endif Loop1: @ Unless the divisor is very big, shift it up in multiples of @ four bits, since this is the amount of unwinding in the main @@ -66,19 +73,28 @@ Loop3: @ then none of the below will match, since the bit in ip will not be @ in the bottom nibble. ands overdone, overdone, #0xe0000000 +#ifdef CONFIG_SYS_THUMB_BUILD + bxeq lr +#else moveq pc, lr @ No fixups needed +#endif tst overdone, ip, ror #3 addne dividend, dividend, divisor, lsr #3 tst overdone, ip, ror #2 addne dividend, dividend, divisor, lsr #2 tst overdone, ip, ror #1 addne dividend, dividend, divisor, lsr #1 - mov pc, lr + RET Ldiv0: str lr, [sp, #-4]! bl __div0 (PLT) mov r0, #0 @ about as wrong as it could be +#ifdef CONFIG_SYS_THUMB_BUILD + ldmia sp!, {lr} + bx lr +#else ldmia sp!, {pc} +#endif .size __umodsi3 , . - __umodsi3 /* # 320 "libgcc1.S" */ /* # 421 "libgcc1.S" */ diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index f655256..1e1dbd4 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */
+#include <config.h> #include <asm/assembler.h>
#define W(instr) instr @@ -61,7 +62,11 @@ memcpy:
cmp r0, r1 +#ifdef CONFIG_SYS_THUMB_BUILD + bxeq lr +#else moveq pc, lr +#endif
enter r4, lr
@@ -149,7 +154,12 @@ memcpy: str1b r0, r4, cs, abort=21f str1b r0, ip, cs, abort=21f
+#ifdef CONFIG_SYS_THUMB_BUILD + exit r4, lr + bx lr +#else exit r4, pc +#endif
9: rsb ip, ip, #4 cmp ip, #2 diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 0cdf895..e149c46 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -9,6 +9,7 @@ * * ASM optimised string functions */ +#include <config.h> #include <asm/assembler.h>
.text @@ -123,4 +124,4 @@ memset: strneb r1, [r0], #1 tst r2, #1 strneb r1, [r0], #1 - mov pc, lr + RET
Signed-off-by: Allen Martin amartin@nvidia.com --- include/configs/tegra20-common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 1c0d235..e6d42b0 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -191,6 +191,7 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM #define CONFIG_CMD_BOOTZ +#define CONFIG_SYS_THUMB_BUILD
/* Defines for SPL */ #define CONFIG_SPL
participants (3)
-
Allen Martin -
Marek Vasut -
Wolfgang Denk