[PATCH 00/18] Synchronise LS1088A/Ten64 device tree with Linux
I am intensively working on updating the current "production" Ten64 (NXP LS1088A) firmware from v2020.07 to the latest U-Boot, with the hope of taking advantage of bootstd/bootflow and other improvements.
One desire I have is to have U-Boot "supply" the device tree which is used for EFI boot, rather than our current method of reading the DTB from a flash partition with commands (sf read etc.) and plugging that into the distroboot process.
Indeed, once we syncronise the U-Boot FDT with the Linux one, the bootflow method "Just Works" with the control FDT, without us having to plug an external FDT into the process.
(Note: the bootstd conversion for Ten64 will be coming in a later commit. The DTS on it's own is only one part of the puzzle)
The flow of this series is: - Fix a crash I found in the U-Boot FDT fixup for Layerscape
The previous U-Boot copy of the fsl-ls1088a.dts did not have direct alias to the "crypto" node, triggering a crash when FDT fixup tried to operate on it.
- Enable DM_SERIAL for Ten64 (mirrors how it was enabled for LS1088A-RDB and LS1088A-QDS recently)
- Move all U-Boot "tweaks" into a -u-boot.dtsi file. Each board will have it's own <boardname>-u-boot.dtsi, which includs the SoC-specific fsl-ls1088a-u-boot.dtsi.
- For all hardware that was in U-Boot's fsl-ls1088a.dtsi, and not in the "correct" place (under /soc), move them into /soc and adopt the Linux kernel definition.
PCIe needed special treatment as it's U-Boot binding was slightly different, as well as different compatible strings (match a different U-Boot driver) for MDIO, USB and fsl-mc among others.
At this point, Linux is able to boot on the Ten64 using U-Boot's FDT (passed to it via EFI) with major hardware (Ethernet, USB, PCIe) functional.
- Finally, copy over the U-Boot fsl-ls1088a.dtsi with the Linux kernel version. They are now bit-for-bit identical, with the U-Boot tweaks contained externally.
- Similarly for the Ten64 DTS - fsl-ls1088a-ten64.dts is now identical to the kernel version.
This builds upon the recent conversion of the LS1088A to DM_SERIAL[1]. I used a similar syncronisation for the LS1028A[2] as a guide.
[1] - "Convert LS1088A and LX2160 to DM_SERIAL" patch series https://patchwork.ozlabs.org/project/uboot/list/?series=346392&state=%2A...
[2] - "arm: dts: ls1028a: sync device tree with linux" patch series https://patchwork.ozlabs.org/project/uboot/list/?series=265457&state=%2A...
Mathew McBride (18): armv8: fsl-layerscape: check for crypto node first in fdt_fixup_remove_jr configs: ten64: enable DM_SERIAL arm: dts: fsl-ls1088a: move u-boot bootph tags into u-boot only files arm: dts: fsl-ls1088a: move memory node into U-Boot specific file pci: layerscape: add support for kernel/official fsl,ls1088a-pcie binding arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux arm: dts: fsl-ls1088a: sync PCIe controller definition with Linux arm: dts: fsl-ls1088a: match Linux FDT by disabling PCIe by default arm: dts: fsl-ls1088a: import CPU definition from Linux kernel arm: dts: fsl-ls1088a: move GPIO controller under "soc" per Linux arm: dts: fsl-ls1088a: move I2C nodes under "soc" and syncronize with Linux arm: dts: fsl-ls1088a: sync usb controller nodes with Linux arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with Linux arm: dts: fsl-ls1088a: syncronise fsl-mc definition with Linux arm: dts: fsl-ls1088a: move and sync existing bindings to be under /soc arm: dts: fsl-ls1088a: copy all missing bindings from Linux arm: dts: ten64: syncronise device tree with Linux arm: dts: ten64: fix header typo and update copyright
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 + arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi | 5 + arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi | 5 + arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi | 18 + arch/arm/dts/fsl-ls1088a-ten64.dts | 61 +- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 63 + arch/arm/dts/fsl-ls1088a.dtsi | 1216 +++++++++++++++----- configs/ten64_tfa_defconfig | 4 +- drivers/pci/pcie_layerscape_rc.c | 1 + 9 files changed, 1067 insertions(+), 310 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-u-boot.dtsi
This a problem I found while updating the U-Boot fsl-ls1088a.dtsi to match the Linux version.
fdt_fixup_remove_jr did not check whether there was a "crypto" alias in the device tree before calling more fdt_* functions, which resulted in a crash.
Fixes: a797f274 ("ARMv8/sec_firmware : Update chosen/kaslr-seed with random number")
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4f91db49ee..22ce699216 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -387,6 +387,10 @@ void fdt_fixup_remove_jr(void *blob) u64 jr_offset, used_jr; fdt32_t *reg;
+ /* Return if crypto node not found */ + if (crypto_node < 0) + return; + used_jr = sec_firmware_used_jobring_offset(); fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This a problem I found while updating the U-Boot fsl-ls1088a.dtsi to match the Linux version.
fdt_fixup_remove_jr did not check whether there was a "crypto" alias in the device tree before calling more fdt_* functions, which resulted in a crash.
Fixes: a797f274 ("ARMv8/sec_firmware : Update chosen/kaslr-seed with random number")
Signed-off-by: Mathew McBride matt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4f91db49ee..22ce699216 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -387,6 +387,10 @@ void fdt_fixup_remove_jr(void *blob) u64 jr_offset, used_jr; fdt32_t *reg;
- /* Return if crypto node not found */
- if (crypto_node < 0)
return;- used_jr = sec_firmware_used_jobring_offset(); fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
The recent series "Convert LS1088A and LX2160 to DM_SERIAL" from Ioana Ciornei provided the necessary support to enable DM_SERIAL on the Ten64 board (LS1088A).
Signed-off-by: Mathew McBride matt@traverse.com.au --- configs/ten64_tfa_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index 2396d9ef37..4e5fcddab6 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -81,7 +81,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_RX8025=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y
On 4/12/2023 3:38 PM, Mathew McBride wrote:
The recent series "Convert LS1088A and LX2160 to DM_SERIAL" from Ioana Ciornei provided the necessary support to enable DM_SERIAL on the Ten64 board (LS1088A).
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
On Wed, Apr 12, 2023 at 07:38:14AM +0000, Mathew McBride wrote:
The recent series "Convert LS1088A and LX2160 to DM_SERIAL" from Ioana Ciornei provided the necessary support to enable DM_SERIAL on the Ten64 board (LS1088A).
Signed-off-by: Mathew McBride matt@traverse.com.au
Reviewed-by: Ioana Ciornei ioana.ciornei@nxp.com
Thanks! I didn't want to touch defconfigs which I cannot directly test on the board.
This moves the bootph-all tags that were added in commit a593c1fec579 ("arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all") into a u-boot only include.
Due to the way the U-Boot device tree "tweak" system is setup[1], we need to have a per-board <boardname>-u-boot.dtsi, which will include the "fsl-ls1088a-u-boot.dtsi" tweaks.
By doing so, future updates to fsl-ls1088a.dtsi from upstream (Linux kernel) can just be copied directly into the U-Boot tree, without worrying about any extra data local to U-Boot.
Signed-off-by: Mathew McBride matt@traverse.com.au
[1] - https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#addi... The CONFIG_SYS_SOC, CONFIG_SYS_CPU and CONFIG_SYS_VENDOR values are the same for the entire Layerscape family, meaning there is no ability to create a LS1088A only file here. But we will be adding per-board tweaks later in any case. --- arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi | 5 +++++ arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi | 5 +++++ arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi | 5 +++++ arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/fsl-ls1088a.dtsi | 2 -- 5 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-u-boot.dtsi
diff --git a/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi new file mode 100644 index 0000000000..298adb849b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi new file mode 100644 index 0000000000..298adb849b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi new file mode 100644 index 0000000000..298adb849b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi new file mode 100644 index 0000000000..f59d8b184c --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +&duart0 { + bootph-all; +}; + +&duart1 { + bootph-all; +}; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 4782b83515..b094bcf67c 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -64,7 +64,6 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - bootph-all; };
duart1: serial@21c0600 { @@ -74,7 +73,6 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - bootph-all; }; };
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This moves the bootph-all tags that were added in commit a593c1fec579 ("arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all") into a u-boot only include.
Due to the way the U-Boot device tree "tweak" system is setup[1], we need to have a per-board <boardname>-u-boot.dtsi, which will include the "fsl-ls1088a-u-boot.dtsi" tweaks.
By doing so, future updates to fsl-ls1088a.dtsi from upstream (Linux kernel) can just be copied directly into the U-Boot tree, without worrying about any extra data local to U-Boot.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
The top-level "memory" node does not exist in the Linux version of the fsl-ls1088a.dtsi file. Move it to the U-Boot "tweak" file, so we can have an identical copy of fsl-ls1088a.dtsi between the projects in the end.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 8 ++++++++ arch/arm/dts/fsl-ls1088a.dtsi | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index f59d8b184c..3eb45d47cd 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -1,6 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ #include <config.h>
+/{ + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; +}; + &duart0 { bootph-all; }; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index b094bcf67c..3afd847baf 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -13,12 +13,6 @@ #address-cells = <2>; #size-cells = <2>;
- memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ - }; - gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
On 4/12/2023 3:38 PM, Mathew McBride wrote:
The top-level "memory" node does not exist in the Linux version of the fsl-ls1088a.dtsi file. Move it to the U-Boot "tweak" file, so we can have an identical copy of fsl-ls1088a.dtsi between the projects in the end.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
This allows the Layerscape PCIe RC driver to use the upstream style binding (two "reg" entries instead of four).
It is similar to the previous commit e10da1f985ad ("pci: layerscape: add official ls1028a binding support") which implemented this for the LS1028A.
Signed-off-by: Mathew McBride matt@traverse.com.au --- drivers/pci/pcie_layerscape_rc.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index 17969e2f23..6a5bf88da2 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -403,6 +403,7 @@ static const struct ls_pcie_drvdata ls1028a_drvdata = { static const struct udevice_id ls_pcie_ids[] = { { .compatible = "fsl,ls-pcie" }, { .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = (ulong)&ls1028a_drvdata }, { } };
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This allows the Layerscape PCIe RC driver to use the upstream style binding (two "reg" entries instead of four).
It is similar to the previous commit e10da1f985ad ("pci: layerscape: add official ls1028a binding support") which implemented this for the LS1028A.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
To synchronise the device tree in U-Boot with Linux, the GIC (Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised before changing any dependent components like PCIe and DPAA2/fsl-mc.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 109 +++++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 3afd847baf..05da798380 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -15,11 +15,23 @@
gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ #interrupt-cells = <3>; interrupt-controller; - interrupts = <1 9 0x4>; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; };
timer { @@ -68,6 +80,97 @@ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + stream-match-mask = <0x7C00>; + dma-coherent; + #global-interrupts = <12>; + // global secure fault + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + // combined secure + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + // global non-secure fault + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + // combined non-secure + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + // performance counter interrupts 0-7 + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + // per context interrupt, 64 interrupts + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + }; };
i2c0: i2c@2000000 {
On 4/12/2023 3:38 PM, Mathew McBride wrote:
To synchronise the device tree in U-Boot with Linux, the GIC (Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised before changing any dependent components like PCIe and DPAA2/fsl-mc.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
This moves the PCIe controller definitions under /soc and adopts the same bindings (fsl,ls1088a-pcie) as Linux. Previously, the format was different between the two versions.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 154 +++++++++++++++++++++++----------- 1 file changed, 106 insertions(+), 48 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 05da798380..71d652c818 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -81,6 +81,112 @@ status = "disabled"; };
+ pcie1: pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <256>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x20 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <24>; + num-ob-windows = <256>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + + pcie2: pcie@3500000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x28 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + + pcie3: pcie@3600000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x30 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; @@ -335,54 +441,6 @@ }; };
- pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ - 0x00 0x03480000 0x0 0x80000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x20 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ - 0x00 0x03580000 0x0 0x80000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x28 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; - - pcie3: pcie@3600000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ - 0x00 0x03680000 0x0 0x80000 /* lut registers */ - 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ - 0x30 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; - sata: sata@3200000 { compatible = "fsl,ls1088a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This moves the PCIe controller definitions under /soc and adopts the same bindings (fsl,ls1088a-pcie) as Linux. Previously, the format was different between the two versions.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
The Linux kernel fsl-ls1088a.dtsi disables (status="disabled") all PCIe controllers by default, with the bootloader (i.e U-Boot) enabling the appropriate controllers (specified by the board reset control word/RCW) by FDT fixup.
However, U-Boot needs these controllers to be enabled to be usable, which we can add in the u-boot only dtsi.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 13 +++++++++++++ arch/arm/dts/fsl-ls1088a.dtsi | 3 +++ 2 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index 3eb45d47cd..ac30b813ff 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -16,3 +16,16 @@ &duart1 { bootph-all; }; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie3 { + status = "okay"; +}; + diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 71d652c818..85316ddb66 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -104,6 +104,7 @@ <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; };
pcie_ep1: pcie-ep@3400000 { @@ -140,6 +141,7 @@ <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; };
pcie_ep2: pcie-ep@3500000 { @@ -175,6 +177,7 @@ <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; };
pcie_ep3: pcie-ep@3600000 {
On 4/12/2023 3:38 PM, Mathew McBride wrote:
The Linux kernel fsl-ls1088a.dtsi disables (status="disabled") all PCIe controllers by default, with the bootloader (i.e U-Boot) enabling the appropriate controllers (specified by the board reset control word/RCW) by FDT fixup.
However, U-Boot needs these controllers to be enabled to be usable, which we can add in the u-boot only dtsi.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
This is required for Linux to boot using the same FDT as U-Boot (such as passing the control FDT to bootefi).
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 87 +++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 85316ddb66..dc6241e20d 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -13,6 +13,93 @@ #address-cells = <2>; #size-cells = <2>;
+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* We have 2 clusters having 4 Cortex-A53 cores each */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x0>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; + }; + gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This is required for Linux to boot using the same FDT as U-Boot (such as passing the control FDT to bootefi).
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
Move the GPIO controller definitions under the "soc" and in the same relative position as the Linux kernel fsl-ls1088a.dtsi.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 88 +++++++++++++++++------------------ 1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index dc6241e20d..06237a58f4 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -168,6 +168,50 @@ status = "disabled"; };
+ gpio0: gpio@2300000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ @@ -428,50 +472,6 @@ bus-width = <4>; };
- gpio0: gpio@2300000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>;
On 4/12/2023 3:38 PM, Mathew McBride wrote:
Move the GPIO controller definitions under the "soc" and in the same relative position as the Linux kernel fsl-ls1088a.dtsi.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
U-Boot's definition for the I2C controllers did not contain any clock information. This resulted in the I2C not functioning when the U-Boot control FDT was passed to Linux.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 76 ++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 32 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 06237a58f4..bd344ba8e2 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -212,6 +212,50 @@ #interrupt-cells = <2>; };
+ i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; + pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ @@ -413,38 +457,6 @@ }; };
- i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 4>; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 4>; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 4>; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 4>; - }; - dspi: dspi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>;
On 4/12/2023 3:38 PM, Mathew McBride wrote:
U-Boot's definition for the I2C controllers did not contain any clock information. This resulted in the I2C not functioning when the U-Boot control FDT was passed to Linux.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB.
An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 8 +++++++ arch/arm/dts/fsl-ls1088a.dtsi | 36 +++++++++++++++++----------- 2 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index ac30b813ff..3a2291527c 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -29,3 +29,11 @@ status = "okay"; };
+&usb0 { + compatible = "fsl,layerscape-dwc3", "snps,dwc3"; +}; + +&usb1 { + compatible = "fsl,layerscape-dwc3", "snps,dwc3"; +}; + diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index bd344ba8e2..ca88b9e9f4 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -256,6 +256,28 @@ status = "disabled"; };
+ usb0: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; + + usb1: usb@3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; + pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ @@ -490,20 +512,6 @@ interrupts = <0 21 0x4>; /* Level high type */ };
- usb0: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - }; - - usb1: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - }; - crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <8>;
On 4/12/2023 3:38 PM, Mathew McBride wrote:
Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB.
An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
On 4/12/2023 3:38 PM, Mathew McBride wrote:
Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB.
An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
Synchronise the MDIO controller definitions with Linux, so the controllers will be usable when passing U-Boot's control FDT to Linux.
This also adds the PCS (internal controller) definitions which are not used by U-Boot.
Caveat: The kernel definition uses "fsl,fman-memac-mdio", as with other members of the Layerscape family, but U-Boot uses a different driver for the DPAA2 Family devices (LS1088/LS2088/LX2160). So we use "fsl,ls-mdio" as the first compatible string for these devices.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 12 +++ arch/arm/dts/fsl-ls1088a.dtsi | 116 +++++++++++++++++++++++---- 2 files changed, 112 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index 3a2291527c..d9d1347b0c 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -17,6 +17,18 @@ bootph-all; };
+/* MDIO controllers - U-Boot uses a different + * driver for the DPAA2 (LS/LX2) family, + * so must match fsl,ls-mdio first. + */ +&emdio1 { + compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; +}; + +&emdio2 { + compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; +}; + &pcie1 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index ca88b9e9f4..ee40a55654 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -477,6 +477,106 @@ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; }; + + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <2500000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + status = "disabled"; + }; + + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <2500000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + status = "disabled"; + }; + + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3_0: ethernet-phy@0 { + reg = <0>; + }; + + pcs3_1: ethernet-phy@1 { + reg = <1>; + }; + + pcs3_2: ethernet-phy@2 { + reg = <2>; + }; + + pcs3_3: ethernet-phy@3 { + reg = <3>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7_0: ethernet-phy@0 { + reg = <0>; + }; + + pcs7_1: ethernet-phy@1 { + reg = <1>; + }; + + pcs7_2: ethernet-phy@2 { + reg = <2>; + }; + + pcs7_3: ethernet-phy@3 { + reg = <3>; + }; + }; };
dspi: dspi@2100000 { @@ -645,20 +745,4 @@ }; }; }; - - emdio1: mdio@8B96000 { - compatible = "fsl,ls-mdio"; - reg = <0x0 0x8B96000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - emdio2: mdio@8B97000 { - compatible = "fsl,ls-mdio"; - reg = <0x0 0x8B97000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; };
On 4/12/2023 3:38 PM, Mathew McBride wrote:
Synchronise the MDIO controller definitions with Linux, so the controllers will be usable when passing U-Boot's control FDT to Linux.
This also adds the PCS (internal controller) definitions which are not used by U-Boot.
Caveat: The kernel definition uses "fsl,fman-memac-mdio", as with other members of the Layerscape family, but U-Boot uses a different driver for the DPAA2 Family devices (LS1088/LS2088/LX2160). So we use "fsl,ls-mdio" as the first compatible string for these devices.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
This moves the fsl-mc device tree definition under the /soc node, as well as adding interrupt and IOMMU definitions that were not in U-Boot before.
There are slight differences between the two bindings as we add a "simple-mfd" compatible to function under U-Boot's driver model.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-u-boot.dtsi | 12 +++ arch/arm/dts/fsl-ls1088a.dtsi | 154 +++++++++++++-------------- 2 files changed, 85 insertions(+), 81 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index d9d1347b0c..efcfdd96ae 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -29,6 +29,18 @@ compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; };
+/* DPAA2 Management Complex (MC) + * "simple-mfd" compatible used by U-Boot only, + * to allow driver model functionality. + */ +&fsl_mc { + compatible = "fsl,qoriq-mc", "simple-mfd"; + + dpmacs { + compatible = "simple-mfd"; + }; +}; + &pcie1 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index ee40a55654..8321b73f30 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -577,6 +577,79 @@ reg = <3>; }; }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ + dma-coherent; + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: ethernet@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <1>; + }; + + dpmac2: ethernet@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <2>; + }; + + dpmac3: ethernet@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <3>; + }; + + dpmac4: ethernet@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <4>; + }; + + dpmac5: ethernet@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <5>; + }; + + dpmac6: ethernet@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <6>; + }; + + dpmac7: ethernet@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <7>; + }; + + dpmac8: ethernet@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <8>; + }; + + dpmac9: ethernet@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <9>; + }; + + dpmac10: ethernet@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + }; + }; + }; };
dspi: dspi@2100000 { @@ -664,85 +737,4 @@ compatible = "arm,psci-0.2"; method = "smc"; }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc", "simple-mfd"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - compatible = "simple-mfd"; - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - status = "disabled"; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - status = "disabled"; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - status = "disabled"; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - status = "disabled"; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - status = "disabled"; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - status = "disabled"; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - status = "disabled"; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - status = "disabled"; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - status = "disabled"; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - status = "disabled"; - }; - }; - }; };
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This moves the fsl-mc device tree definition under the /soc node, as well as adding interrupt and IOMMU definitions that were not in U-Boot before.
There are slight differences between the two bindings as we add a "simple-mfd" compatible to function under U-Boot's driver model.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under the top level, until the DM_SERIAL implementation recently.
In this commit, remove any remaining devices (that were in U-Boot, but not touched by previous patches in this series) to be under /soc, updating to their upstream (Linux) bindings.
The bindings have been copied closest to their relative positions in the Linux version, so the eventual result is that the U-Boot and Linux fsl-ls1088a.dtsi will be identical.
The next commit will add the hardware bindings that were not in U-Boot.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 185 +++++++++++++++++++--------------- 1 file changed, 104 insertions(+), 81 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 8321b73f30..d5822520fb 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -159,6 +159,20 @@ status = "disabled"; };
+ dspi: spi@2100000 { + compatible = "fsl,ls1088a-dspi", + "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + spi-num-chipselects = <6>; + status = "disabled"; + }; + duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; @@ -212,6 +226,16 @@ #interrupt-cells = <2>; };
+ ifc: memory-controller@2240000 { + compatible = "fsl,ifc"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -256,6 +280,35 @@ status = "disabled"; };
+ qspi: spi@20c0000 { + compatible = "fsl,ls2080a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + status = "disabled"; + }; + + esdhc: esdhc@2140000 { + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + usb0: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; @@ -278,6 +331,57 @@ status = "disabled"; };
+ sata: sata@3200000 { + compatible = "fsl,ls1088a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x7 0x100520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + dma-coherent; + status = "disabled"; + }; + + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ @@ -652,87 +756,6 @@ }; };
- dspi: dspi@2100000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; /* Level high type */ - spi-num-chipselects = <6>; - }; - - qspi: quadspi@1550000 { - compatible = "fsl,ls1088a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - status = "disabled"; - }; - - esdhc: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - little-endian; - bus-width = <4>; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 0x4>; /* Level high type */ - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1088a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "ahci", "sata-ecc"; - interrupts = <0 133 4>; - status = "disabled"; - }; - psci { compatible = "arm,psci-0.2"; method = "smc";
On 4/12/2023 3:38 PM, Mathew McBride wrote:
Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under the top level, until the DM_SERIAL implementation recently.
In this commit, remove any remaining devices (that were in U-Boot, but not touched by previous patches in this series) to be under /soc, updating to their upstream (Linux) bindings.
The bindings have been copied closest to their relative positions in the Linux version, so the eventual result is that the U-Boot and Linux fsl-ls1088a.dtsi will be identical.
The next commit will add the hardware bindings that were not in U-Boot.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
This is effectively:
cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi
Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a.dtsi | 320 ++++++++++++++++++++++++++++++++-- 1 file changed, 304 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index d5822520fb..e5fb137ac0 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -1,18 +1,27 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * NXP ls1088a SOC common device tree source + * Device Tree Include file for NXP Layerscape-1088A family SoC. + * + * Copyright 2017-2020 NXP + * + * Harninder Rai harninder.rai@nxp.com * - * Copyright 2017, 2020-2021, 2023 NXP */ - #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> + / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>;
+ aliases { + crypto = &crypto; + rtc1 = &ftm_alarm0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -121,12 +130,73 @@ }; };
+ thermal-zones { + core-cluster { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ - <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ - <1 11 0x8>, /* Virtual PPI, active-low */ - <1 10 0x8>; /* Hypervisor PPI, active-low */ + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; };
sysclk: sysclk { @@ -136,6 +206,13 @@ clock-output-names = "sysclk"; };
+ reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -150,13 +227,105 @@ clocks = <&sysclk>; };
- duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; + dcfg: dcfg@1e00000 { + compatible = "fsl,ls1088a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + + isc: syscon@1f70000 { + compatible = "fsl,ls1088a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xf 0x0>; + }; + }; + + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; + clock-names = "sfp"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000030 + 0x00000003 0x00000037 + 0x00000004 0x0000003d + 0x00000005 0x00000044 + 0x00000006 0x0000004a + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005e + 0x0000000a 0x00000064 + 0x0000000b 0x0000006b + /* Calibration data group 2 */ + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a + /* Calibration data group 3 */ + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x00000040 + 0x00020004 0x0000004a + 0x00020005 0x00000054 + 0x00020006 0x0000005e + /* Calibration data group 4 */ + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000027 + 0x00030003 0x00000032 + 0x00030004 0x0000003e + 0x00030005 0x00000049 + 0x00030006 0x00000054 + 0x00030007 0x00000060>; + little-endian; + #thermal-sensor-cells = <1>; };
dspi: spi@2100000 { @@ -173,6 +342,15 @@ status = "disabled"; };
+ duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; @@ -582,6 +760,20 @@ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; };
+ console@8340020 { + compatible = "fsl,dpaa2-console"; + reg = <0x00000000 0x08340020 0 0x2>; + }; + + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + little-endian; + fsl,extts-fifo; + }; + emdio1: mdio@8b96000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8b96000 0x0 0x1000>; @@ -682,6 +874,86 @@ }; };
+ cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core2_watchdog: wdt@c020000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc020000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core3_watchdog: wdt@c030000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc030000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt@c100000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt@c110000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core2_watchdog: wdt@c120000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc120000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core3_watchdog: wdt@c130000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc130000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ @@ -754,10 +1026,26 @@ }; }; }; + + rcpm: power-controller@1e34040 { + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1088a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; };
- psci { - compatible = "arm,psci-0.2"; - method = "smc"; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; }; };
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This is effectively:
cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi
Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This is effectively:
cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi
Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.
Signed-off-by: Mathew McBride matt@traverse.com.au
arch/arm/dts/fsl-ls1088a.dtsi | 320 ++++++++++++++++++++++++++++++++-- 1 file changed, 304 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index d5822520fb..e5fb137ac0 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -1,18 +1,27 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
I just relized that I overlooked this. Is it fine to update this？
I could drop this line change in my local if need to keep original license.
Regards, Peng.
/*
- NXP ls1088a SOC common device tree source
- Device Tree Include file for NXP Layerscape-1088A family SoC.
- Copyright 2017-2020 NXP
- Harninder Rai harninder.rai@nxp.com
*/
- Copyright 2017, 2020-2021, 2023 NXP
- #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>;
aliases {
crypto = &crypto;rtc1 = &ftm_alarm0;};
cpus { #address-cells = <1>; #size-cells = <0>;
@@ -121,12 +130,73 @@ }; };
- thermal-zones {
core-cluster {polling-delay-passive = <1000>;polling-delay = <5000>;thermal-sensors = <&tmu 0>;trips {core_cluster_alert: core-cluster-alert {temperature = <85000>;hysteresis = <2000>;type = "passive";};core-cluster-crit {temperature = <95000>;hysteresis = <2000>;type = "critical";};};cooling-maps {map0 {trip = <&core_cluster_alert>;cooling-device =<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;};};};soc {polling-delay-passive = <1000>;polling-delay = <5000>;thermal-sensors = <&tmu 1>;trips {soc-crit {temperature = <95000>;hysteresis = <2000>;type = "critical";};};};- };
- timer { compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */<1 14 0x8>, /* Physical Non-Secure PPI, active-low */<1 11 0x8>, /* Virtual PPI, active-low */<1 10 0x8>; /* Hypervisor PPI, active-low */
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */};
pmu {
compatible = "arm,cortex-a53-pmu";interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;};
psci {
compatible = "arm,psci-0.2";method = "smc";};
sysclk: sysclk {
@@ -136,6 +206,13 @@ clock-output-names = "sysclk"; };
- reboot {
compatible = "syscon-reboot";regmap = <&reset>;offset = <0x0>;mask = <0x02>;- };
- soc { compatible = "simple-bus"; #address-cells = <2>;
@@ -150,13 +227,105 @@ clocks = <&sysclk>; };
duart0: serial@21c0500 {compatible = "fsl,ns16550", "ns16550a";reg = <0x0 0x21c0500 0x0 0x100>;
dcfg: dcfg@1e00000 {compatible = "fsl,ls1088a-dcfg", "syscon";reg = <0x0 0x1e00000 0x0 0x10000>;little-endian;};reset: syscon@1e60000 {compatible = "fsl,ls1088a-reset", "syscon";reg = <0x0 0x1e60000 0x0 0x10000>;};isc: syscon@1f70000 {compatible = "fsl,ls1088a-isc", "syscon";reg = <0x0 0x1f70000 0x0 0x10000>;little-endian;#address-cells = <1>;#size-cells = <1>;ranges = <0x0 0x0 0x1f70000 0x10000>;extirq: interrupt-controller@14 {compatible = "fsl,ls1088a-extirq";#interrupt-cells = <2>;#address-cells = <0>;interrupt-controller;reg = <0x14 4>;interrupt-map =<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;interrupt-map-mask = <0xf 0x0>;};};sfp: efuse@1e80000 {compatible = "fsl,ls1028a-sfp";reg = <0x0 0x1e80000 0x0 0x10000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";
clock-names = "sfp";};tmu: tmu@1f80000 {compatible = "fsl,qoriq-tmu";reg = <0x0 0x1f80000 0x0 0x10000>;interrupts = <0 23 0x4>;fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;fsl,tmu-calibration =/* Calibration data group 1 */<0x00000000 0x000000230x00000001 0x0000002a0x00000002 0x000000300x00000003 0x000000370x00000004 0x0000003d0x00000005 0x000000440x00000006 0x0000004a0x00000007 0x000000510x00000008 0x000000570x00000009 0x0000005e0x0000000a 0x000000640x0000000b 0x0000006b/* Calibration data group 2 */0x00010000 0x000000220x00010001 0x0000002a0x00010002 0x000000320x00010003 0x0000003a0x00010004 0x000000420x00010005 0x0000004a0x00010006 0x000000520x00010007 0x0000005a0x00010008 0x000000620x00010009 0x0000006a/* Calibration data group 3 */0x00020000 0x000000210x00020001 0x0000002b0x00020002 0x000000350x00020003 0x000000400x00020004 0x0000004a0x00020005 0x000000540x00020006 0x0000005e/* Calibration data group 4 */0x00030000 0x000000100x00030001 0x0000001c0x00030002 0x000000270x00030003 0x000000320x00030004 0x0000003e0x00030005 0x000000490x00030006 0x000000540x00030007 0x00000060>;little-endian;#thermal-sensor-cells = <1>;};
dspi: spi@2100000 {
@@ -173,6 +342,15 @@ status = "disabled"; };
duart0: serial@21c0500 {compatible = "fsl,ns16550", "ns16550a";reg = <0x0 0x21c0500 0x0 0x100>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(4)>;interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;status = "disabled";};- duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>;
@@ -582,6 +760,20 @@ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; };
console@8340020 {compatible = "fsl,dpaa2-console";reg = <0x00000000 0x08340020 0 0x2>;};ptp-timer@8b95000 {compatible = "fsl,dpaa2-ptp";reg = <0x0 0x8b95000 0x0 0x100>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(1)>;little-endian;fsl,extts-fifo;};- emdio1: mdio@8b96000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8b96000 0x0 0x1000>;
@@ -682,6 +874,86 @@ }; };
cluster1_core0_watchdog: wdt@c000000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc000000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster1_core1_watchdog: wdt@c010000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc010000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster1_core2_watchdog: wdt@c020000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc020000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster1_core3_watchdog: wdt@c030000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc030000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster2_core0_watchdog: wdt@c100000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc100000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster2_core1_watchdog: wdt@c110000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc110000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster2_core2_watchdog: wdt@c120000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc120000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};cluster2_core3_watchdog: wdt@c130000 {compatible = "arm,sp805", "arm,primecell";reg = <0x0 0xc130000 0x0 0x1000>;clocks = <&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>,<&clockgen QORIQ_CLK_PLATFORM_PLLQORIQ_CLK_PLL_DIV(16)>;clock-names = "wdog_clk", "apb_pclk";};- fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
@@ -754,10 +1026,26 @@ }; }; };
rcpm: power-controller@1e34040 {compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";reg = <0x0 0x1e34040 0x0 0x18>;#fsl,rcpm-wakeup-cells = <6>;little-endian;};ftm_alarm0: timer@2800000 {compatible = "fsl,ls1088a-ftm-alarm";reg = <0x0 0x2800000 0x0 0x10000>;fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;};
- psci {
compatible = "arm,psci-0.2";method = "smc";
- firmware {
optee {compatible = "linaro,optee-tz";method = "smc";};
On Fri, Apr 28, 2023 at 11:33:23AM +0800, Peng Fan wrote:
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This is effectively:
cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi
Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.
Signed-off-by: Mathew McBride matt@traverse.com.au
arch/arm/dts/fsl-ls1088a.dtsi | 320 ++++++++++++++++++++++++++++++++-- 1 file changed, 304 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index d5822520fb..e5fb137ac0 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -1,18 +1,27 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
I just relized that I overlooked this. Is it fine to update this？
I could drop this line change in my local if need to keep original license.
As it's part of the re-sync it's fine.
This synchronises the Linux device tree with U-Boot (cp linux/..../fsl-ls1088a-ten64.dts uboot/..../fsl-ls1088a-ten64.dts), as of Linux v6.2-rc5.
Missing from the U-Boot copy previously was the Ethernet PCS definitions (required for linking with PHY in Linux but not used by U-Boot) and various upstream fixes and formatting changes.
The board microcontroller (which doesn't have a Linux driver) has been moved to the -u-boot.dtsi, as well as the spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux).
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi | 13 +++++ arch/arm/dts/fsl-ls1088a-ten64.dts | 56 ++++++++++++---------- 2 files changed, 45 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi index 298adb849b..89566bf849 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi @@ -3,3 +3,16 @@
#include "fsl-ls1088a-u-boot.dtsi"
+/{ + aliases { + spi0 = &qspi; + }; +}; + +&i2c0 { + uc: board-controller@7e { + compatible = "traverse,ten64-controller"; + reg = <0x7e>; + }; +}; + diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts index 55a7d41fb0..d4867d6cf4 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ b/arch/arm/dts/fsl-ls1088a-ten64.dts @@ -22,7 +22,6 @@ aliases { serial0 = &duart0; serial1 = &duart1; - spi0 = &qspi; };
chosen { @@ -36,18 +35,16 @@ * external power off (e.g ATX Power Button) * asserted */ - powerdn { + button-powerdn { label = "External Power Down"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>; linux,code = <KEY_POWER>; };
/* Rear Panel 'ADMIN' button (GPIO_H) */ - admin { + button-admin { label = "ADMIN button"; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>; linux,code = <KEY_WPS_BUTTON>; }; }; @@ -55,17 +52,17 @@ leds { compatible = "gpio-leds";
- sfp1down { + led-0 { label = "ten64:green:sfp1:down"; gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; };
- sfp2up { + led-1 { label = "ten64:green:sfp2:up"; gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; };
- admin { + led-2 { label = "ten64:admin"; gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; }; @@ -95,17 +92,17 @@ /* XG1 - Upper SFP */ &dpmac1 { sfp = <&sfp_xg1>; + pcs-handle = <&pcs1>; phy-connection-type = "10gbase-r"; managed = "in-band-status"; - status = "okay"; };
/* XG0 - Lower SFP */ &dpmac2 { sfp = <&sfp_xg0>; + pcs-handle = <&pcs2>; phy-connection-type = "10gbase-r"; managed = "in-band-status"; - status = "okay"; };
/* DPMAC3..6 is GE4 to GE8 */ @@ -113,28 +110,28 @@ phy-handle = <&mdio1_phy5>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_0>; };
&dpmac4 { phy-handle = <&mdio1_phy6>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_1>; };
&dpmac5 { phy-handle = <&mdio1_phy7>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_2>; };
&dpmac6 { phy-handle = <&mdio1_phy8>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_3>; };
/* DPMAC7..10 is GE0 to GE3 */ @@ -142,28 +139,28 @@ phy-handle = <&mdio1_phy1>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_0>; };
&dpmac8 { phy-handle = <&mdio1_phy2>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_1>; };
&dpmac9 { phy-handle = <&mdio1_phy3>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_2>; };
&dpmac10 { phy-handle = <&mdio1_phy4>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_3>; };
&duart0 { @@ -234,11 +231,6 @@ compatible = "atmel,at97sc3204t"; reg = <0x29>; }; - - uc: board-controller@7e { - compatible = "traverse,ten64-controller"; - reg = <0x7e>; - }; };
&i2c2 { @@ -253,7 +245,7 @@ &i2c3 { status = "okay";
- i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9540"; #address-cells = <1>; #size-cells = <0>; @@ -273,6 +265,22 @@ }; };
+&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + &qspi { status = "okay";
On 4/12/2023 3:38 PM, Mathew McBride wrote:
This synchronises the Linux device tree with U-Boot (cp linux/..../fsl-ls1088a-ten64.dts uboot/..../fsl-ls1088a-ten64.dts), as of Linux v6.2-rc5.
Missing from the U-Boot copy previously was the Ethernet PCS definitions (required for linking with PHY in Linux but not used by U-Boot) and various upstream fixes and formatting changes.
The board microcontroller (which doesn't have a Linux driver) has been moved to the -u-boot.dtsi, as well as the spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux).
Signed-off-by: Mathew McBridematt@traverse.com.au
Reviewed-by: Peng Fan peng.fan@nxp.com
Somehow, I managed to typo our company name in the U-Boot and Linux kernel submissions.
Fix this and update the copyright year at the same time.
Signed-off-by: Mathew McBride matt@traverse.com.au --- arch/arm/dts/fsl-ls1088a-ten64.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts index d4867d6cf4..0d11440d88 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ b/arch/arm/dts/fsl-ls1088a-ten64.dts @@ -1,9 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree file for Travese Ten64 (LS1088) board + * Device Tree file for Traverse Technologies Ten64 + * (LS1088A) board * Based on fsl-ls1088a-rdb.dts * Copyright 2017-2020 NXP - * Copyright 2019-2021 Traverse Technologies + * Copyright 2019-2023 Traverse Technologies * * Author: Mathew McBride matt@traverse.com.au */
On 4/12/2023 3:38 PM, Mathew McBride wrote:
Somehow, I managed to typo our company name in the U-Boot and Linux kernel submissions.
Fix this and update the copyright year at the same time.
Signed-off-by: Mathew McBridematt@traverse.com.au
Acked-by: Peng Fan peng.fan@nxp.com
On Wed, Apr 12, 2023 at 07:38:12AM +0000, Mathew McBride wrote:
I am intensively working on updating the current "production" Ten64 (NXP LS1088A) firmware from v2020.07 to the latest U-Boot, with the hope of taking advantage of bootstd/bootflow and other improvements.
One desire I have is to have U-Boot "supply" the device tree which is used for EFI boot, rather than our current method of reading the DTB from a flash partition with commands (sf read etc.) and plugging that into the distroboot process.
Indeed, once we syncronise the U-Boot FDT with the Linux one, the bootflow method "Just Works" with the control FDT, without us having to plug an external FDT into the process.
(Note: the bootstd conversion for Ten64 will be coming in a later commit. The DTS on it's own is only one part of the puzzle)
The flow of this series is:
Fix a crash I found in the U-Boot FDT fixup for Layerscape
The previous U-Boot copy of the fsl-ls1088a.dts did not have direct alias to the "crypto" node, triggering a crash when FDT fixup tried to operate on it.
Enable DM_SERIAL for Ten64 (mirrors how it was enabled for LS1088A-RDB and LS1088A-QDS recently)
Move all U-Boot "tweaks" into a -u-boot.dtsi file. Each board will have it's own <boardname>-u-boot.dtsi, which includs the SoC-specific fsl-ls1088a-u-boot.dtsi.
For all hardware that was in U-Boot's fsl-ls1088a.dtsi, and not in the "correct" place (under /soc), move them into /soc and adopt the Linux kernel definition.
PCIe needed special treatment as it's U-Boot binding was slightly different, as well as different compatible strings (match a different U-Boot driver) for MDIO, USB and fsl-mc among others.
At this point, Linux is able to boot on the Ten64 using U-Boot's FDT (passed to it via EFI) with major hardware (Ethernet, USB, PCIe) functional.
Finally, copy over the U-Boot fsl-ls1088a.dtsi with the Linux kernel version. They are now bit-for-bit identical, with the U-Boot tweaks contained externally.
Similarly for the Ten64 DTS - fsl-ls1088a-ten64.dts is now identical to the kernel version.
This builds upon the recent conversion of the LS1088A to DM_SERIAL[1]. I used a similar syncronisation for the LS1028A[2] as a guide.
[1] - "Convert LS1088A and LX2160 to DM_SERIAL" patch series https://patchwork.ozlabs.org/project/uboot/list/?series=346392&state=%2A...
[2] - "arm: dts: ls1028a: sync device tree with linux" patch series https://patchwork.ozlabs.org/project/uboot/list/?series=265457&state=%2A...
Thanks a lot, Mathew! I really appreciate the work that you put into this series.
For the entire series:
Reviewed-by: Ioana Ciornei ioana.ciornei@nxp.com Tested-by: Ioana Ciornei ioana.ciornei@nxp.com # on LS1088A-RDB
Ioana
participants (4)
-
Ioana Ciornei -
Mathew McBride -
Peng Fan -
Tom Rini