[PATCH 0/2] sunxi: add support for Ethernet on V3s-based SoCs
This patchset adds support for Ethernet on V3s-based SoCs, adding in required clock gates, resets to the CCU driver and finally a matching configuration for the sun8i_emac driver.
Tobias Schramm (2): clk: sunxi: support Ethernet clock gates and resets on V3s-based SoCs net: sun8i_emac: add support for EMAC on V3s-based SoCs
drivers/clk/sunxi/clk_v3s.c | 6 ++++++ drivers/net/sun8i_emac.c | 7 +++++++ 2 files changed, 13 insertions(+)
Previously Ethernet clock gates and resets were missing from the V3s CCU driver. Add the required clock gates and resets for Ethernet MAC and internal Ethernet phy.
Signed-off-by: Tobias Schramm t.schramm@manjaro.org --- drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 6524c13540..0402d5ed19 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -17,6 +17,7 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
@@ -31,6 +32,8 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
+ [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), + [CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), @@ -45,12 +48,15 @@ static struct ccu_reset v3s_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_TCON0] = RESET(0x2c4, BIT(4)), [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
+ [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
The Allwinner V3s SoC and related SoCs have a fast Ethernet MAC with internal Ethernet phy. The internal phy is connected via MII and the MII is not exposed externally on SoC pins. Add support for this MAC and phy combo to the sun8i EMAC driver.
Signed-off-by: Tobias Schramm t.schramm@manjaro.org --- drivers/net/sun8i_emac.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 8bff4fe9a9..d9d1825b69 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -903,6 +903,11 @@ static const struct emac_variant emac_variant_h6 = { .support_rmii = true, };
+static const struct emac_variant emac_variant_v3s = { + .syscon_offset = 0x30, + .soc_has_internal_phy = true, +}; + static const struct udevice_id sun8i_emac_eth_ids[] = { { .compatible = "allwinner,sun8i-a83t-emac", .data = (ulong)&emac_variant_a83t }, @@ -914,6 +919,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (ulong)&emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", .data = (ulong)&emac_variant_h6 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = (ulong)&emac_variant_v3s }, { } };
On Fri, 31 May 2024 16:33:48 +0200 Tobias Schramm t.schramm@manjaro.org wrote:
Hi Tobias,
This patchset adds support for Ethernet on V3s-based SoCs, adding in required clock gates, resets to the CCU driver and finally a matching configuration for the sun8i_emac driver.
Michael already sent identical patches two weeks ago. I reviewed them already, and they are just waiting for the merge window to open.
https://lore.kernel.org/u-boot/20240513205609.1872861-1-mwalle@kernel.org/
Cheers, Andre
Tobias Schramm (2): clk: sunxi: support Ethernet clock gates and resets on V3s-based SoCs net: sun8i_emac: add support for EMAC on V3s-based SoCs
drivers/clk/sunxi/clk_v3s.c | 6 ++++++ drivers/net/sun8i_emac.c | 7 +++++++ 2 files changed, 13 insertions(+)
participants (2)
-
Andre Przywara -
Tobias Schramm