[U-Boot] [PATCH 0/4] MIPS: minor cleanups
Gabor Juhos (4): MIPS: mips32/time.c: fix checkpatch errors/warnings MIPS: mips64/interrupt.c: remove superfluous include MIPS: remove obsolete TODO items MIPS: mips32/cache.S: remove superfluous register assignment
arch/mips/cpu/mips32/cache.S | 3 +-- arch/mips/cpu/mips32/time.c | 5 +++-- arch/mips/cpu/mips64/interrupts.c | 1 - doc/README.mips | 4 ---- 4 files changed, 4 insertions(+), 9 deletions(-)
-- 1.7.10
Checking mips32/time.c with checkpatch.pl shows this:
arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required total: 1 errors, 1 warnings, 0 checks, 85 lines checked
Fix the code to make checkpatch.pl happy.
Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com --- arch/mips/cpu/mips32/time.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c index 09fc842..e9ed7fc 100644 --- a/arch/mips/cpu/mips32/time.c +++ b/arch/mips/cpu/mips32/time.c @@ -27,7 +27,8 @@ static unsigned long timestamp;
/* how many counter cycles in a jiffy */ -#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ +#define CYCLES_PER_JIFFY \ + (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
/* * timer without interrupts @@ -54,7 +55,7 @@ ulong get_timer(ulong base) } write_c0_compare(expirelo);
- return (timestamp - base); + return timestamp - base; }
void __udelay(unsigned long usec)
Nothing is used from asm/mipsregs.h.
Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com --- arch/mips/cpu/mips64/interrupts.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c index e4e9aae..87f7a9f 100644 --- a/arch/mips/cpu/mips64/interrupts.c +++ b/arch/mips/cpu/mips64/interrupts.c @@ -22,7 +22,6 @@ */
#include <common.h> -#include <asm/mipsregs.h>
void enable_interrupts(void) {
The MIPS code uses centralized u-boot.lds script already, and dynamic relocation is supported as well.
Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com --- doc/README.mips | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/doc/README.mips b/doc/README.mips index f4f770b..b28f628 100644 --- a/doc/README.mips +++ b/doc/README.mips @@ -39,8 +39,6 @@ TODOs
* Secondary cache support missing
- * Centralize the link directive files - * Initialize TLB entries redardless of their use
* R2000/R3000 class parts are not supported @@ -51,8 +49,6 @@ TODOs initialized in board specific assembler language before the cache init code is run -- that is, initialize the DRAM in lowlevel_init().
- * get rid of CONFIG_MANUAL_RELOC - * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
* support Qemu Malta
The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache.
Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register.
Signed-off-by: Gabor Juhos juhosg@openwrt.org --- arch/mips/cpu/mips32/cache.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 64dfad0..8158ea8 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -145,7 +145,6 @@ NESTED(mips_cache_reset, 0, ra) li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
@@ -180,7 +179,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t5 + move a2, t4 PTR_LA t7, mips_init_dcache jalr t7
2013/6/12 Gabor Juhos juhosg@openwrt.org:
Gabor Juhos (4): MIPS: mips32/time.c: fix checkpatch errors/warnings MIPS: mips64/interrupt.c: remove superfluous include MIPS: remove obsolete TODO items MIPS: mips32/cache.S: remove superfluous register assignment
arch/mips/cpu/mips32/cache.S | 3 +-- arch/mips/cpu/mips32/time.c | 5 +++-- arch/mips/cpu/mips64/interrupts.c | 1 - doc/README.mips | 4 ---- 4 files changed, 4 insertions(+), 9 deletions(-)
all four patches applied to u-boot-mips/next, thanks
-- Best regards, Daniel
participants (2)
-
Daniel Schwierzeck -
Gabor Juhos