[U-Boot] [PATCH 0/7] board: ti: DRA72: Add support for SR2.0 rev C evm
Hi, The following series adds support for DRA72x SoC and enables support for TI DRA72-evm rev C.
Rev C evm has a few changes w.r.t. rev A/B (SR1.0 based SoC), including newer DDR, newer ethernet PHY(2 ports enabled), very few pin mux changes, etc.
Ethernet support is a follow on series that should follow once we have base support in place.
Series based on: master 41bccb814285 spi: omap3: Fix multiple definition of 'priv' requires: https://patchwork.ozlabs.org/patch/597873/ for boot.
Bootlog: rev C: http://pastebin.ubuntu.com/15398047/ rev B: http://pastebin.ubuntu.com/15398054/
Nishanth Menon (5): ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0 ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0 ARM: OMAP5/DRA7: Split iodelay functionality into sub steps ARM: OMAP5/DRA7: Expose do_set_iodelay board: ti: DRA7: Add DRA72-rev C evm pinmux
Ravi Babu (2): ARM: DRA72x: Add support for detection of SR2.0 board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0
arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c | 68 ++++++++++---- arch/arm/cpu/armv7/omap5/hw_data.c | 16 ++++ arch/arm/cpu/armv7/omap5/hwinit.c | 3 + arch/arm/cpu/armv7/omap5/sdram.c | 44 +++++++++ arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 4 + arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 1 + board/ti/dra7xx/evm.c | 103 +++++++++++++++++++--- board/ti/dra7xx/mux_data.h | 102 +++++++++++++++------ 9 files changed, 286 insertions(+), 56 deletions(-)
From: Ravi Babu ravibabu@ti.com
Add support for detection of SR2.0 version of DRA72x family of processors.
Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 2 ++ arch/arm/cpu/armv7/omap5/hwinit.c | 3 +++ arch/arm/cpu/armv7/omap5/sdram.c | 2 ++ arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 1 + 5 files changed, 9 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 7f8c0a423bad..93d1efbca17d 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -775,6 +775,7 @@ void __weak hw_data_init(void) break;
case DRA722_ES1_0: + case DRA722_ES2_0: *prcm = &dra7xx_prcm; *dplls_data = &dra72x_dplls; *omap_vcores = &dra722_volts; @@ -807,6 +808,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: + case DRA722_ES2_0: *regs = &ioregs_dra72x_es1; break;
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 8f184df2abb7..e3ac8bbe9524 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -373,6 +373,9 @@ void init_omap_revision(void) case DRA722_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA722_ES1_0; break; + case DRA722_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = DRA722_ES2_0; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 7dc5bb7e4a4b..5cf360c41468 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -438,6 +438,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, } break; case DRA722_ES1_0: + case DRA722_ES2_0: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; @@ -670,6 +671,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) case DRA752_ES1_1: case DRA752_ES2_0: case DRA722_ES1_0: + case DRA722_ES2_0: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ sizeof(dra_bug_00339_regs[0]); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index b5b3838f4500..1eeb8d5f626f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -60,6 +60,7 @@ #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F +#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
/* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index aef31266ce9e..8c85f46db6ef 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -700,6 +700,7 @@ static inline u8 is_dra72x(void) #define DRA752_ES1_1 0x07520110 #define DRA752_ES2_0 0x07520200 #define DRA722_ES1_0 0x07220100 +#define DRA722_ES2_0 0x07220200
/* * SRAM scratch space entries
On Tue, Mar 15, 2016 at 06:09:11PM -0500, Nishanth Menon wrote:
From: Ravi Babu ravibabu@ti.com
Add support for detection of SR2.0 version of DRA72x family of processors.
Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:11PM -0500, Nishanth Menon wrote:
From: Ravi Babu ravibabu@ti.com
Add support for detection of SR2.0 version of DRA72x family of processors.
Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 93d1efbca17d..b69c0d13715a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -743,6 +743,18 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { .ctrl_ddr_ctrl_ext_0 = 0xA2000000, };
+const struct ctrl_ioregs ioregs_dra72x_es2 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x60606060, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x00000000, + .ctrl_ddrio_2 = 0x00000000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + void __weak hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -808,9 +820,11 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: - case DRA722_ES2_0: *regs = &ioregs_dra72x_es1; break; + case DRA722_ES2_0: + *regs = &ioregs_dra72x_es2; + break;
default: printf("\n INVALID OMAP REVISION ");
On Tue, Mar 15, 2016 at 06:09:12PM -0500, Nishanth Menon wrote:
Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:12PM -0500, Nishanth Menon wrote:
Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Based on data from EMIF configuration tool 1.1.1.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/sdram.c | 44 +++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 5cf360c41468..7712923d8572 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -398,6 +398,45 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { 0x0 };
+const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { + 0x04040100, + 0x006B009F, + 0x006B00A2, + 0x006B00A8, + 0x006B00A8, + 0x006B00B2, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x00600073, + 0x00600071, + 0x0060007C, + 0x0060007E, + 0x00600084, + 0x00400053, + 0x00400051, + 0x0040005C, + 0x0040005E, + 0x00400064, + 0x00800080, + 0x00800080, + 0x40010080, + 0x08102040, + 0x005B008F, + 0x005B0092, + 0x005B0098, + 0x005B0098, + 0x005B00A2, + 0x00300043, + 0x00300041, + 0x0030004C, + 0x0030004E, + 0x00300054, + 0x00000077 +}; + const struct lpddr2_mr_regs mr_regs = { .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, .mr2 = 0x6, @@ -438,10 +477,13 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, } break; case DRA722_ES1_0: - case DRA722_ES2_0: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; + case DRA722_ES2_0: + *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; + *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); + break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
On Tue, Mar 15, 2016 at 06:09:13PM -0500, Nishanth Menon wrote:
Based on data from EMIF configuration tool 1.1.1.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:13PM -0500, Nishanth Menon wrote:
Based on data from EMIF configuration tool 1.1.1.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
From: Ravi Babu ravibabu@ti.com
DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration.
Tested-by: Vishal Mahaveer vishalm@ti.com Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- board/ti/dra7xx/evm.c | 59 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 4 deletions(-)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 97174c8bb812..0461b53ba2f8 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -32,8 +32,11 @@ #include "../common/board_detect.h"
#define board_is_dra74x_evm() board_ti_is("5777xCPU") +#define board_is_dra72x_evm() board_ti_is("DRA72x-T") #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ (strncmp("H", board_ti_get_rev(), 1) <= 0) +#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \ + (strncmp("C", board_ti_get_rev(), 1) <= 0) #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ board_ti_get_emif2_size()
@@ -127,6 +130,31 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_rd_wr_exec_thresh = 0x00000305 };
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { + .sdram_config_init = 0x61862BB2, + .sdram_config = 0x61862BB2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x0000514D, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD1137824, + .sdram_tim2 = 0x30B37FE3, + .sdram_tim3 = 0x409F8AD8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0824400E, + .emif_ddr_phy_ctlr_1 = 0x0E24400E, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, + .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, + .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, + .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { .sdram_config_init = 0x61851ab2, .sdram_config = 0x61851ab2, @@ -203,7 +231,11 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) } break; case DRA722_ES1_0: - *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + case DRA722_ES2_0: + if (ram_size < CONFIG_MAX_MEM_MAPPED) + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + else + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; break; default: *regs = &emif1_ddr3_532_mhz_1cs; @@ -234,6 +266,18 @@ const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { .is_ma_present = 0x1 };
+/* + * DRA722 EVM EMIF1 2GB CONFIGURATION + * EMIF1 4 devices of 512Mb x 8 Micron + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80700100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { u64 ram_size; @@ -250,8 +294,13 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) *dmm_lisa_regs = &lisa_map_dra7_1536MB; break; case DRA722_ES1_0: + case DRA722_ES2_0: default: - *dmm_lisa_regs = &lisa_map_2G_x_2; + if (ram_size < CONFIG_MAX_MEM_MAPPED) + *dmm_lisa_regs = &lisa_map_2G_x_2; + else + *dmm_lisa_regs = &lisa_map_2G_x_4; + break; } }
@@ -324,8 +373,10 @@ void do_board_detect(void)
if (board_is_dra74x_evm()) { bname = "DRA74x EVM"; - /* If EEPROM is not populated */ + } else if (board_is_dra72x_evm()) { + bname = "DRA72x EVM"; } else { + /* If EEPROM is not populated */ if (is_dra72x()) bname = "DRA72x EVM"; else @@ -614,7 +665,7 @@ static inline void vtt_regulator_enable(void) return;
/* Do not enable VTT for DRA722 */ - if (omap_revision() == DRA722_ES1_0) + if (is_dra72x()) return;
/*
On Tue, Mar 15, 2016 at 06:09:14PM -0500, Nishanth Menon wrote:
From: Ravi Babu ravibabu@ti.com
DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration.
Tested-by: Vishal Mahaveer vishalm@ti.com Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:14PM -0500, Nishanth Menon wrote:
From: Ravi Babu ravibabu@ti.com
DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration.
Tested-by: Vishal Mahaveer vishalm@ti.com Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation.
While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c | 64 +++++++++++++++++----- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 2 + 2 files changed, 52 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c index 9fa6e6991f0e..744950f01bd9 100644 --- a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c +++ b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c @@ -166,16 +166,14 @@ static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, return 0; }
-void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, - struct iodelay_cfg_entry const *iodelay, - int niodelays) +int __recalibrate_iodelay_start(void) { int ret = 0;
/* IO recalibration should be done only from SRAM */ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); - return; + return -1; }
/* unlock IODELAY CONFIG registers */ @@ -191,23 +189,27 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, goto err;
ret = update_delay_mechanism((*ctrl)->iodelay_config_base); - if (ret) - goto err;
- /* Configure Mux settings */ - do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); +err: + return ret; +}
- /* Configure Manual IO timing modes */ - ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); - if (ret) - goto err; +void __recalibrate_iodelay_end(int ret) +{
- ret = isolate_io(DEISOLATE_IO); + /* IO recalibration should be done only from SRAM */ + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { + puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); + return; + } + + if (!ret) + ret = isolate_io(DEISOLATE_IO);
-err: /* lock IODELAY CONFIG registers */ writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + CFG_REG_8_OFFSET); + /* * UART cannot be used during IO recalibration sequence as IOs are in * isolation. So error handling and debug prints are done after @@ -232,7 +234,41 @@ err: case ERR_FPDE: puts("IODELAY: FPDE calculation failed\n"); break; + case -1: + puts("IODELAY: Wrong Context call?\n"); + break; default: debug("IODELAY: IO delay recalibration successfully completed\n"); } + + return; +} + +void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* IO recalibration should be done only from SRAM */ + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { + puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); + return; + } + + ret = __recalibrate_iodelay_start(); + if (ret) + goto err; + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + +err: + __recalibrate_iodelay_end(ret); + } diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index 4cd0a3cc80d0..0de8a800c1a2 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -83,5 +83,7 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, struct iodelay_cfg_entry const *iodelay, int niodelays); +int __recalibrate_iodelay_start(void); +void __recalibrate_iodelay_end(int ret);
#endif
On Tue, Mar 15, 2016 at 06:09:15PM -0500, Nishanth Menon wrote:
Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation.
While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:15PM -0500, Nishanth Menon wrote:
Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation.
While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
do_set_iodelay can now be used from board files based on needs of the platforms variation they have.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c | 4 ++-- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c index 744950f01bd9..87987308aced 100644 --- a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c +++ b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c @@ -138,8 +138,8 @@ static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde) return reg; }
-static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, - int niodelays) +int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, + int niodelays) { struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array; u32 reg, cpde, fpde, i; diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index 0de8a800c1a2..c99700403914 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -86,4 +86,6 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, int __recalibrate_iodelay_start(void); void __recalibrate_iodelay_end(int ret);
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, + int niodelays); #endif
On Tue, Mar 15, 2016 at 06:09:16PM -0500, Nishanth Menon wrote:
do_set_iodelay can now be used from board files based on needs of the platforms variation they have.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:16PM -0500, Nishanth Menon wrote:
do_set_iodelay can now be used from board files based on needs of the platforms variation they have.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side.
Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon.
Signed-off-by: Nishanth Menon nm@ti.com --- board/ti/dra7xx/evm.c | 44 ++++++++++++++++--- board/ti/dra7xx/mux_data.h | 102 +++++++++++++++++++++++++++++++------------- 2 files changed, 110 insertions(+), 36 deletions(-)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 0461b53ba2f8..d975f8c575ab 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -398,16 +398,29 @@ void set_muxconf_regs_essential(void) #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { - struct pad_conf_entry const *pads; + struct pad_conf_entry const *pads, *delta_pads = NULL; struct iodelay_cfg_entry const *iodelay; - int npads, niodelays; + int npads, niodelays, delta_npads = 0; + int ret;
switch (omap_revision()) { case DRA722_ES1_0: - pads = dra72x_core_padconf_array; - npads = ARRAY_SIZE(dra72x_core_padconf_array); - iodelay = dra72_iodelay_cfg_array; - niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array); + case DRA722_ES2_0: + pads = dra72x_core_padconf_array_common; + npads = ARRAY_SIZE(dra72x_core_padconf_array_common); + if (board_is_dra72x_revc_or_later()) { + delta_pads = dra72x_rgmii_padconf_array_revc; + delta_npads = + ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); + iodelay = dra72_iodelay_cfg_array_revc; + niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); + } else { + delta_pads = dra72x_rgmii_padconf_array_revb; + delta_npads = + ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); + iodelay = dra72_iodelay_cfg_array_revb; + niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); + } break; case DRA752_ES1_0: case DRA752_ES1_1: @@ -427,7 +440,24 @@ void recalibrate_iodelay(void) RGMII1_ID_MODE_N_MASK); break; } - __recalibrate_iodelay(pads, npads, iodelay, niodelays); + /* Setup I/O isolation */ + ret = __recalibrate_iodelay_start(); + if (ret) + goto err; + + /* Do the muxing here */ + do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); + + /* Now do the weird minor deltas that should be safe */ + if (delta_npads) + do_set_mux32((*ctrl)->control_padconf_core_base, + delta_pads, delta_npads); + + /* Setup IOdelay configuration */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); +err: + /* Closeup.. remove isolation */ + __recalibrate_iodelay_end(ret); } #endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 6db11a2bbb88..34a05dd6bd86 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -12,7 +12,7 @@
#include <asm/arch/mux_dra7xx.h>
-const struct pad_conf_entry dra72x_core_padconf_array[] = { +const struct pad_conf_entry dra72x_core_padconf_array_common[] = { {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ @@ -104,37 +104,11 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = { {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ - {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ - {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ - {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ - {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ - {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ - {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ - {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ - {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ - {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ - {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ - {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ - {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */ - {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */ - {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */ - {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */ - {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */ - {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */ - {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */ - {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */ - {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */ - {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */ - {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */ - {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ - {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */ - {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */ {MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */ {MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ @@ -160,7 +134,6 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = { {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ - {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ @@ -188,6 +161,65 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = { {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ };
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = { + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */ + {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */ + {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */ +}; + +const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = { + {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */ + {RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */ + {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ +}; + const struct pad_conf_entry early_padconf[] = { #if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ @@ -201,7 +233,7 @@ const struct pad_conf_entry early_padconf[] = { };
#ifdef CONFIG_IODELAY_RECALIBRATION -const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = { +const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = { {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */ {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */ {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */ @@ -236,6 +268,18 @@ const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = { {0x188, 0, 0}, /* CFG_GPMC_A18_OUT */ {0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */ }; + +const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = { + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */ + {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */ + {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ +}; + #endif
const struct pad_conf_entry dra74x_core_padconf_array[] = {
On Tue, Mar 15, 2016 at 06:09:17PM -0500, Nishanth Menon wrote:
Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side.
Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Tue, Mar 15, 2016 at 06:09:17PM -0500, Nishanth Menon wrote:
Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side.
Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Wednesday 16 March 2016 04:39 AM, Nishanth Menon wrote:
Hi, The following series adds support for DRA72x SoC and enables support for TI DRA72-evm rev C.
Rev C evm has a few changes w.r.t. rev A/B (SR1.0 based SoC), including newer DDR, newer ethernet PHY(2 ports enabled), very few pin mux changes, etc.
Ethernet support is a follow on series that should follow once we have base support in place.
Series based on: master 41bccb814285 spi: omap3: Fix multiple definition of 'priv' requires: https://patchwork.ozlabs.org/patch/597873/ for boot.
Bootlog: rev C: http://pastebin.ubuntu.com/15398047/ rev B: http://pastebin.ubuntu.com/15398054/
Whole series looks good to me. Reviewed-by: Lokesh Vutla lokeshvutla@ti.com
Thanks and regards, Lokesh
Nishanth Menon (5): ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0 ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0 ARM: OMAP5/DRA7: Split iodelay functionality into sub steps ARM: OMAP5/DRA7: Expose do_set_iodelay board: ti: DRA7: Add DRA72-rev C evm pinmux
Ravi Babu (2): ARM: DRA72x: Add support for detection of SR2.0 board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0
arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c | 68 ++++++++++---- arch/arm/cpu/armv7/omap5/hw_data.c | 16 ++++ arch/arm/cpu/armv7/omap5/hwinit.c | 3 + arch/arm/cpu/armv7/omap5/sdram.c | 44 +++++++++ arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 4 + arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 1 + board/ti/dra7xx/evm.c | 103 +++++++++++++++++++--- board/ti/dra7xx/mux_data.h | 102 +++++++++++++++------ 9 files changed, 286 insertions(+), 56 deletions(-)
participants (3)
-
Lokesh Vutla -
Nishanth Menon -
Tom Rini