[PATCH] arm: mxs: Clear CPSR V bit to activate low vectors
The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0xffff0000, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which is located at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump to low vectors on exception instead, and therefore run the U-Boot exception handling code.
Signed-off-by: Marek Vasut marex@denx.de --- Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Fabio Estevam festevam@gmail.com Cc: Lukasz Majewski lukma@denx.de Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 3 +++ arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 4 ++++ 2 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 4d21e3df76e..d64a8328b04 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -85,6 +85,9 @@ void mx28_fixup_vt(uint32_t start_addr) /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); } + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); }
#ifdef CONFIG_ARCH_MISC_INIT diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5598c552ab9..4a7dfc6a2ae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/sections.h> +#include <asm/system.h> #include <linux/compiler.h>
#include "mxs_init.h" @@ -104,6 +105,9 @@ static void mxs_spl_fixup_vectors(void)
/* cppcheck-suppress nullPointer */ memcpy(0x0, &_start, 0x60); + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); }
static void mxs_spl_console_init(void)
On Sat, 29 Jul 2023 15:30:10 +0200 Marek Vasut marex@denx.de wrote:
The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0xffff0000, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which is located at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump to low vectors on exception instead, and therefore run the U-Boot exception handling code.
Signed-off-by: Marek Vasut marex@denx.de
Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Fabio Estevam festevam@gmail.com Cc: Lukasz Majewski lukma@denx.de Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/arm926ejs/mxs/mxs.c | 3 +++ arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 4 ++++ 2 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 4d21e3df76e..d64a8328b04 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -85,6 +85,9 @@ void mx28_fixup_vt(uint32_t start_addr) /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); }
- /* Make sure ARM core points to low vectors */
- set_cr(get_cr() & ~CR_V);
}
#ifdef CONFIG_ARCH_MISC_INIT diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5598c552ab9..4a7dfc6a2ae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/sections.h> +#include <asm/system.h> #include <linux/compiler.h>
#include "mxs_init.h" @@ -104,6 +105,9 @@ static void mxs_spl_fixup_vectors(void)
/* cppcheck-suppress nullPointer */ memcpy(0x0, &_start, 0x60);
- /* Make sure ARM core points to low vectors */
- set_cr(get_cr() & ~CR_V);
}
static void mxs_spl_console_init(void)
Reviewed-by: Lukasz Majewski lukma@denx.de
Best regards,
Lukasz Majewski
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Hi Marek, Lukasz,
On 31.07.23 10:06, Lukasz Majewski wrote:
On Sat, 29 Jul 2023 15:30:10 +0200 Marek Vasut marex@denx.de wrote:
The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0xffff0000, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which is located at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump to low vectors on exception instead, and therefore run the U-Boot exception handling code.
Signed-off-by: Marek Vasut marex@denx.de
Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: Fabio Estevam festevam@gmail.com Cc: Lukasz Majewski lukma@denx.de Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/arm926ejs/mxs/mxs.c | 3 +++ arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 4 ++++ 2 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 4d21e3df76e..d64a8328b04 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -85,6 +85,9 @@ void mx28_fixup_vt(uint32_t start_addr) /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); }
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V); }
#ifdef CONFIG_ARCH_MISC_INIT
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5598c552ab9..4a7dfc6a2ae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/sections.h> +#include <asm/system.h> #include <linux/compiler.h>
#include "mxs_init.h" @@ -104,6 +105,9 @@ static void mxs_spl_fixup_vectors(void)
/* cppcheck-suppress nullPointer */ memcpy(0x0, &_start, 0x60);
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V); }
static void mxs_spl_console_init(void)
Reviewed-by: Lukasz Majewski lukma@denx.de
Thanks for raising my attention to this older patch, but it breaks exaclty the xea board:
+{standard input}: Assembler messages: +{standard input}:214: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode +{standard input}:249: Error: selected processor does not support `mcr p15,0,r3,c1,c0,0' in Thumb mode +{standard input}:157: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode +{standard input}:188: Error: selected processor does not support `mcr p15,0,r3,c1,c0,0' in Thumb mode
Can you check it ?
Regards, Stefano
participants (3)
-
Lukasz Majewski -
Marek Vasut -
Stefano Babic