From: Igal Liberman igall@marvell.com

Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions.

This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman igall@marvell.com Signed-off-by: Konstantin Porotchkin kostap@marvell.com Cc: Pali Rohár pali@kernel.org Cc: Marek Behun marek.behun@nic.cz Cc: Konstantin Porotchkin kostap@marvell.com --- v2: - 3720-db & 3720-espressobin: Fix PHY0 & PHY1 to use USB on PHY0 and PEX on PHY1

arch/arm/dts/armada-3720-db.dts | 8 +- arch/arm/dts/armada-3720-espressobin.dts | 12 +- arch/arm/dts/armada-3720-turris-mox.dts | 12 +- arch/arm/dts/armada-3720-uDPU.dts | 23 ++-- arch/arm/dts/armada-7040-db-nand.dts | 24 ++-- arch/arm/dts/armada-7040-db.dts | 22 ++-- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 30 ++--- arch/arm/dts/armada-8040-db.dts | 24 ++-- arch/arm/dts/armada-8040-mcbin.dts | 27 +++-- arch/arm/dts/armada-8040-puzzle-m801.dts | 32 ++--- arch/arm/dts/cn9130-crb-A.dts | 16 +-- arch/arm/dts/cn9130-crb-B.dts | 16 +-- board/CZ.NIC/turris_mox/turris_mox.c | 8 +- drivers/phy/marvell/comphy_a3700.c | 70 +++++------ drivers/phy/marvell/comphy_core.c | 14 +-- drivers/phy/marvell/comphy_cp110.c | 124 +++++++++++--------- drivers/phy/marvell/comphy_mux.c | 10 +- include/dt-bindings/comphy/comphy_data.h | 90 +++++++------- 18 files changed, 288 insertions(+), 274 deletions(-)

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 1b1b66b94de6..42e7ddd25c55 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -70,13 +70,13 @@

&comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; }; };

diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 96a4b3d95b88..d86d8f0b63cf 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -83,18 +83,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; };

phy2 { - phy-type = <PHY_TYPE_SATA0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA0>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 974270cc8c68..8e0ebf508d44 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -73,18 +73,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_3_125G>; };

phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 7f4b8222f4af..4b30f3cea8c7 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -108,18 +108,19 @@

&comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; - phy1 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_3_125G>; - }; - - phy2 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; - }; };

&eth0 { diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts index f249c71f6561..ccf470b317f1 100644 --- a/arch/arm/dts/armada-7040-db-nand.dts +++ b/arch/arm/dts/armada-7040-db-nand.dts @@ -129,33 +129,33 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; };

phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 6037f12f0e9f..f475fb361071 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -122,32 +122,32 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; };

phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; };

phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; };

phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; };

diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 86df6ac0b202..ce5832c2fbd7 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -160,22 +160,22 @@ * Lane 5: Not connected */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; };

@@ -272,25 +272,25 @@ * Lane 5: SGMII2 - Connected to Topaz switch */ phy0 { - phy-type = <PHY_TYPE_SATA1>; - phy-invert = <PHY_POLARITY_RXD_INVERT>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-invert = <COMPHY_POLARITY_RXD_INVERT>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; };

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index a2b7c992a406..1edfaab682eb 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -89,22 +89,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; };

@@ -188,22 +188,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_PEX1>; + phy-type = <COMPHY_TYPE_PEX1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; };

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index b0a36e328bc9..98a582df26fe 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -171,22 +171,22 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; };

@@ -286,22 +286,23 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SGMII3>; + phy-type = <COMPHY_TYPE_SGMII3>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index ff46ce50cbc7..0becc4ff0d34 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -220,24 +220,24 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; };

@@ -367,23 +367,23 @@ * Lane 5: SGMII2 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; }; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts index fa21ef314cba..5c5e0fb2eb1e 100644 --- a/arch/arm/dts/cn9130-crb-A.dts +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -15,29 +15,29 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy4 { - phy-type = <PHY_TYPE_SFI>; - phy-speed = <PHY_SPEED_10_3125G>; + phy-type = <COMPHY_TYPE_SFI>; + phy-speed = <COMPHY_SPEED_10_3125G>; };

phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; };

diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts index 7cb587ada826..6041084a2c87 100644 --- a/arch/arm/dts/cn9130-crb-B.dts +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -15,29 +15,29 @@

&cp0_comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; };

phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; };

phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; };

phy3 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; };

phy4 { - phy-type = <PHY_TYPE_SFI>; - phy-speed = <PHY_SPEED_10_3125G>; + phy-type = <COMPHY_TYPE_SFI>; + phy-speed = <COMPHY_SPEED_10_3125G>; };

phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; };

diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 486680a49e88..15cbf92550e6 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -216,13 +216,13 @@ int comphy_update_map(struct comphy_map *serdes_map, int count)

if (sfpindex >= 0 && swindex >= 0) { if (sfpindex < swindex) - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; else - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; } else if (sfpindex >= 0) { - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; } else if (swindex >= 0) { - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; }

return 0; diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 12523d18a805..06822d1d12e0 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -17,33 +17,33 @@ DECLARE_GLOBAL_DATA_PTR;

struct comphy_mux_data a3700_comphy_mux_data[] = { -/* Lane 0 */ + /* Lane 0 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0 }, - { PHY_TYPE_SGMII1, 0x0 }, - { PHY_TYPE_USB3_HOST0, 0x1 }, - { PHY_TYPE_USB3_DEVICE, 0x1 } + { COMPHY_TYPE_UNCONNECTED, 0x0 }, + { COMPHY_TYPE_SGMII1, 0x0 }, + { COMPHY_TYPE_USB3_HOST0, 0x1 }, + { COMPHY_TYPE_USB3_DEVICE, 0x1 } } }, -/* Lane 1 */ + /* Lane 1 */ { 3, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SGMII0, 0x0}, - { PHY_TYPE_PEX0, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SGMII0, 0x0}, + { COMPHY_TYPE_PEX0, 0x1} } }, -/* Lane 2 */ + /* Lane 2 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SATA0, 0x0}, - { PHY_TYPE_USB3_HOST0, 0x1}, - { PHY_TYPE_USB3_DEVICE, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SATA0, 0x0}, + { COMPHY_TYPE_USB3_HOST0, 0x1}, + { COMPHY_TYPE_USB3_DEVICE, 0x1} } }, }; @@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 10. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);

/* @@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert) /* * 0. Check the Polarity invert bits */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) data |= bs_txd_inv;

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) data |= bs_rxd_inv;

reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); @@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 9. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);

/* @@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) * Set Soft ID for Host mode (Device mode works with Hard ID * detection) */ - if (type == PHY_TYPE_USB3_HOST0) { + if (type == COMPHY_TYPE_USB3_HOST0) { /* * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) * clear BIT1: set SOFT_ID = Host @@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) * comparison to 3.125 Gbps values. These register values are * stored in "sgmii_phy_init_fix" array. */ - if ((speed != PHY_SPEED_1_25G) && - (sgmii_phy_init_fix[fix_idx].addr == addr)) { + if (speed != COMPHY_SPEED_1_25G && + sgmii_phy_init_fix[fix_idx].addr == addr) { /* Use new value */ val = sgmii_phy_init_fix[fix_idx].value; if (fix_idx < fix_arr_sz) @@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide * COMPHY bit rate */ - if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ + if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x8 << rf_gen_rx_sel_shift) | (0x8 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select);

- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ + } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x6 << rf_gen_rx_sel_shift) | (0x6 << rf_gen_tx_sel_shift), @@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * registers are OK. */ debug("Running C-DPI phy init %s mode\n", - speed == PHY_SPEED_3_125G ? "2G5" : "1G"); + speed == COMPHY_SPEED_3_125G ? "2G5" : "1G"); if (get_ref_clk() == 40) comphy_sgmii_phy_init(lane, speed);

@@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 18. Check the PHY Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);

- if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);

/* @@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, comphy_map->type, comphy_map->invert);

switch (comphy_map->type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break;

- case PHY_TYPE_PEX0: + case COMPHY_TYPE_PEX0: ret = comphy_pcie_power_up(comphy_map->speed, comphy_map->invert); break;

- case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, comphy_map->type, comphy_map->speed, comphy_map->invert); break;

- case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: ret = comphy_sgmii_power_up(lane, comphy_map->speed, comphy_map->invert); break;

- case PHY_TYPE_SATA0: + case COMPHY_TYPE_SATA0: ret = comphy_sata_power_up(comphy_map->invert); break;

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index cffceb1395bb..f1f061d7c116 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -29,7 +29,7 @@ static const char *get_speed_string(u32 speed) "6.25 Gbps", "10.31 Gbps" };

- if (speed < 0 || speed > PHY_SPEED_MAX) + if (speed < 0 || speed > COMPHY_SPEED_MAX) return "invalid";

return speed_strings[speed]; @@ -46,7 +46,7 @@ static const char *get_type_string(u32 type) "RXAUI0", "RXAUI1", "SFI", "IGNORE" };

- if (type < 0 || type > PHY_TYPE_MAX) + if (type < 0 || type > COMPHY_TYPE_MAX) return "invalid";

return type_strings[type]; @@ -59,7 +59,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,

for (lane = 0; lane < chip_cfg->comphy_lanes_count; lane++, comphy_map_data++) { - if (comphy_map_data->speed == PHY_SPEED_INVALID) { + if (comphy_map_data->speed == COMPHY_SPEED_INVALID) { printf("Comphy-%d: %-13s\n", lane, get_type_string(comphy_map_data->type)); } else { @@ -136,16 +136,16 @@ static int comphy_probe(struct udevice *dev) continue;

comphy_map_data[lane].speed = fdtdec_get_int( - blob, subnode, "phy-speed", PHY_TYPE_INVALID); + blob, subnode, "phy-speed", COMPHY_TYPE_INVALID); comphy_map_data[lane].type = fdtdec_get_int( - blob, subnode, "phy-type", PHY_SPEED_INVALID); + blob, subnode, "phy-type", COMPHY_SPEED_INVALID); comphy_map_data[lane].invert = fdtdec_get_int( - blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); + blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT); comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, "clk-src"); comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, "end_point"); - if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { + if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a323de7c76d0..e4ab90121c74 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -74,35 +74,47 @@ struct utmi_phy_data { * Eth_port_0 that include (SGMII0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ - {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ - {PHY_TYPE_SATA0, 0x4} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ - {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII1, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 0 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, + {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 2 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, + {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 3 */ + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, + {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 4 */ + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, + {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, + {COMPHY_TYPE_SGMII1, 0x1} } }, + /* Lane 5 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, };

struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, - {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ - {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ - {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ + /* Lane 0 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2}, + {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 2 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 3 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 4 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } }, + /* Lane 5 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } }, };

static u32 polling_with_timeout(void __iomem *addr, u32 val, @@ -868,9 +880,9 @@ static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); /* Fix the type after check the PHY and PIPE configuration */ for (lane = 0; lane < comphy_max_count; lane++) { - if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && - (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) - serdes_map[lane].type = PHY_TYPE_UNCONNECTED; + if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) && + (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED)) + serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED; } }

@@ -895,7 +907,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, /* Check if the first 4 lanes configured as By-4 */ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; lane++, ptr_comphy_map++) { - if (ptr_comphy_map->type != PHY_TYPE_PEX0) + if (ptr_comphy_map->type != COMPHY_TYPE_PEX0) break; pcie_width++; } @@ -912,14 +924,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, pcie_width = 1; } switch (ptr_comphy_map->type) { - case PHY_TYPE_UNCONNECTED: - case PHY_TYPE_IGNORE: + case COMPHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_IGNORE: continue; break; - case PHY_TYPE_PEX0: - case PHY_TYPE_PEX1: - case PHY_TYPE_PEX2: - case PHY_TYPE_PEX3: + case COMPHY_TYPE_PEX0: + case COMPHY_TYPE_PEX1: + case COMPHY_TYPE_PEX2: + case COMPHY_TYPE_PEX3: mode = COMPHY_FW_PCIE_FORMAT(pcie_width, ptr_comphy_map->clk_src, COMPHY_PCIE_MODE, @@ -928,30 +940,30 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: + case COMPHY_TYPE_SATA2: + case COMPHY_TYPE_SATA3: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, mode); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: "); debug("SGMII PHY speed in lane %d is invalid,", lane); debug(" set PHY speed to 1.25G\n"); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; }

/* @@ -965,12 +977,12 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII2: + case COMPHY_TYPE_SGMII3: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; }

mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, @@ -980,7 +992,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SFI: + case COMPHY_TYPE_SFI: mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, COMPHY_UNIT_ID0, ptr_comphy_map->speed); @@ -988,8 +1000,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: ret = comphy_rxauii_power_up(lane, hpipe_base_addr, comphy_base_addr); break; @@ -1001,9 +1013,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, if (ret == 0) { /* * If interface wans't initialized, set the lane to - * PHY_TYPE_UNCONNECTED state. + * COMPHY_TYPE_UNCONNECTED state. */ - ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; + ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED; pr_err("PLL is not locked - Failed to initialize lane %d\n", lane); } diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 98327557a899..aaef736b75dd 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -15,7 +15,7 @@ * description: this function passes over the COMPHY lanes and check if the type * is valid for specific lane. If the type is not valid, * the function update the struct and set the type of the lane as - * PHY_TYPE_UNCONNECTED + * COMPHY_TYPE_UNCONNECTED */ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes) @@ -28,7 +28,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { /* Don't check ignored COMPHYs */ - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue;

mux_opt = mux_data->mux_values; @@ -43,8 +43,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, debug("lane number %d, had invalid type %d\n", lane, comphy_map_data->type); debug("set lane %d as type %d\n", lane, - PHY_TYPE_UNCONNECTED); - comphy_map_data->type = PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED); + comphy_map_data->type = COMPHY_TYPE_UNCONNECTED; } else { debug("lane number %d, has type %d\n", lane, comphy_map_data->type); @@ -88,7 +88,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,

for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue;

/* diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 08544fa758bf..7d62dcf7fa51 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -6,53 +6,53 @@ #ifndef _COMPHY_DATA_H_ #define _COMPHY_DATA_H_

-#define PHY_SPEED_1_25G 0 -#define PHY_SPEED_1_5G 1 -#define PHY_SPEED_2_5G 2 -#define PHY_SPEED_3G 3 -#define PHY_SPEED_3_125G 4 -#define PHY_SPEED_5G 5 -#define PHY_SPEED_5_15625G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 -#define PHY_SPEED_INVALID 0xff +#define COMPHY_SPEED_1_25G 0 +#define COMPHY_SPEED_1_5G 1 +#define COMPHY_SPEED_2_5G 2 +#define COMPHY_SPEED_3G 3 +#define COMPHY_SPEED_3_125G 4 +#define COMPHY_SPEED_5G 5 +#define COMPHY_SPEED_5_15625G 6 +#define COMPHY_SPEED_6G 7 +#define COMPHY_SPEED_6_25G 8 +#define COMPHY_SPEED_10_3125G 9 +#define COMPHY_SPEED_MAX 10 +#define COMPHY_SPEED_INVALID 0xff

-#define PHY_TYPE_UNCONNECTED 0 -#define PHY_TYPE_PEX0 1 -#define PHY_TYPE_PEX1 2 -#define PHY_TYPE_PEX2 3 -#define PHY_TYPE_PEX3 4 -#define PHY_TYPE_SATA0 5 -#define PHY_TYPE_SATA1 6 -#define PHY_TYPE_SATA2 7 -#define PHY_TYPE_SATA3 8 -#define PHY_TYPE_SGMII0 9 -#define PHY_TYPE_SGMII1 10 -#define PHY_TYPE_SGMII2 11 -#define PHY_TYPE_SGMII3 12 -#define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3 14 -#define PHY_TYPE_USB3_HOST0 15 -#define PHY_TYPE_USB3_HOST1 16 -#define PHY_TYPE_USB3_DEVICE 17 -#define PHY_TYPE_XAUI0 18 -#define PHY_TYPE_XAUI1 19 -#define PHY_TYPE_XAUI2 20 -#define PHY_TYPE_XAUI3 21 -#define PHY_TYPE_RXAUI0 22 -#define PHY_TYPE_RXAUI1 23 -#define PHY_TYPE_SFI 24 -#define PHY_TYPE_IGNORE 25 -#define PHY_TYPE_MAX 26 -#define PHY_TYPE_INVALID 0xff +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PEX0 1 +#define COMPHY_TYPE_PEX1 2 +#define COMPHY_TYPE_PEX2 3 +#define COMPHY_TYPE_PEX3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SATA2 7 +#define COMPHY_TYPE_SATA3 8 +#define COMPHY_TYPE_SGMII0 9 +#define COMPHY_TYPE_SGMII1 10 +#define COMPHY_TYPE_SGMII2 11 +#define COMPHY_TYPE_SGMII3 12 +#define COMPHY_TYPE_QSGMII 13 +#define COMPHY_TYPE_USB3 14 +#define COMPHY_TYPE_USB3_HOST0 15 +#define COMPHY_TYPE_USB3_HOST1 16 +#define COMPHY_TYPE_USB3_DEVICE 17 +#define COMPHY_TYPE_XAUI0 18 +#define COMPHY_TYPE_XAUI1 19 +#define COMPHY_TYPE_XAUI2 20 +#define COMPHY_TYPE_XAUI3 21 +#define COMPHY_TYPE_RXAUI0 22 +#define COMPHY_TYPE_RXAUI1 23 +#define COMPHY_TYPE_SFI 24 +#define COMPHY_TYPE_IGNORE 25 +#define COMPHY_TYPE_MAX 26 +#define COMPHY_TYPE_INVALID 0xff

-#define PHY_POLARITY_NO_INVERT 0 -#define PHY_POLARITY_TXD_INVERT 1 -#define PHY_POLARITY_RXD_INVERT 2 -#define PHY_POLARITY_ALL_INVERT \ - (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT \ + (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)

#define UTMI_PHY_TO_USB3_HOST0 0 #define UTMI_PHY_TO_USB3_HOST1 1