[U-Boot-Users] Enabling Cache in MPC5200
Hi, I am using a LITE5200 evaluation board, and am not able to enable the cache. The execution hangs in these calls. void EnableInstCache(void) { __asm(" mfspr r5,1008"); __asm(" ori r5,r5,0x00008800");// # Set the ICE and ICFI bit __asm(" andi. r6,r5,0x0000F7FF");// # clear the ICFI bit for the final store __asm(" mtspr 1008,r5"); __asm(" isync"); __asm(" isync"); __asm(" isync"); __asm(" isync"); __asm(" sync"); __asm(" mtspr 1008,r6");// # Do the final store __asm(" isync"); __asm(" sync");
}
void EnableDataCache(void) { __asm(" mfspr r5,1008"); __asm(" ori r5,r5,0x00004400");// # Set the ICE and ICFI bit __asm(" andi. r6,r5,0x0000FBFF");// # clear the ICFI bit for the final store __asm(" mtspr 1008,r5"); __asm(" isync"); __asm(" isync"); __asm(" isync"); __asm(" isync"); __asm(" sync"); __asm(" mtspr 1008,r6");// # Do the final store __asm(" isync"); __asm(" sync");
} What could be the problem? Thanks -San
Hi San,
I am using a LITE5200 evaluation board, and am not able to enable the cache. The execution hangs in these calls. void EnableInstCache(void) {
[...]
}
void EnableDataCache(void) {
[...]
} What could be the problem?
It might be one of our favourites, i.e. wrong ram initialization. When enabling the caches, the CPU generates burst accesses for the first time. It is pretty common (on this mailing list) that not quite correctly initialized RAM works for single beat but fails for bursts. So my advice would be to check the RAM init.
Is is really a standard lite5200 board that you use?
Cheers Detlev
Thanks Detlev for the reply.
Its a "standard lite5200" from Freescale. The cache gets enabled in some boards and not in some. 2 out of 4 boards we have, has this issue. I will check my RAM initialisation. Any more pointers will be helpful.
-San
Detlev Zundel wrote:
Hi San,
I am using a LITE5200 evaluation board, and am not able to enable the cache. The execution hangs in these calls. void EnableInstCache(void) {
[...]
}
void EnableDataCache(void) {
[...]
} What could be the problem?
It might be one of our favourites, i.e. wrong ram initialization. When enabling the caches, the CPU generates burst accesses for the first time. It is pretty common (on this mailing list) that not quite correctly initialized RAM works for single beat but fails for bursts. So my advice would be to check the RAM init.
Is is really a standard lite5200 board that you use?
Cheers Detlev
-- The best way to predict the future is to invent it. -- Alan Kay -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de
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