--- board/cta5000s/Makefile | 50 +++ board/cta5000s/config.mk | 30 ++ board/cta5000s/cta5000s.c | 575 +++++++++++++++++++++++++++++++++++ include/configs/cta5000s.h | 723 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1378 insertions(+), 0 deletions(-) create mode 100644 board/cta5000s/Makefile create mode 100644 board/cta5000s/config.mk create mode 100644 board/cta5000s/cta5000s.c create mode 100644 include/configs/cta5000s.h

diff --git a/board/cta5000s/Makefile b/board/cta5000s/Makefile new file mode 100644 index 0000000..be7e213 --- /dev/null +++ b/board/cta5000s/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cta5000s/config.mk b/board/cta5000s/config.mk new file mode 100644 index 0000000..5fca8c7 --- /dev/null +++ b/board/cta5000s/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd. yuli@arabellasw.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Rattler series boards by Analogue & Micro +# + +TEXT_BASE = 0xFE000000 diff --git a/board/cta5000s/cta5000s.c b/board/cta5000s/cta5000s.c new file mode 100644 index 0000000..0fe6da2 --- /dev/null +++ b/board/cta5000s/cta5000s.c @@ -0,0 +1,575 @@ +/* + * + * Aztek Networks CTA5000S board u-boot board support + * + * Copyright 2007 Aztek Networks, Inc. + * + * Authors: Scott Mann smann@azteknetworks.net + * jblack jblack@azteknetworks.com + * + * Based on: U-Boot configuration for Analogue&Micro Rattler boards. + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen yuli@arabellasw.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + */ + +#include <common.h> +#include <mpc8260.h> +#include <asm/cpm_8260.h> +#include <ioports.h> +#include <configs/cta5000s.h> + +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <libfdt_env.h> +#include <fdt_support.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +/* See include/configs/cta5000s.h for CFG_* settings + * All values in the following tables taken from + * chapter 6 of the cta Programmer's Guide + */ + +/* table is used by cpu/mpc8260/cpu_init.c */ +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + {/*conf ppar, psor, pdir, podr, pdat */ + /* PA31 */ {CFG_FCC1, 1, 1, 0, 0, 0}, + /* FCC1 MII COL */ + /* PA30 */ {CFG_FCC1, 1, 1, 0, 0, 0}, + /* FCC1 MII CRS */ + /* PA29 */ {CFG_FCC1, 1, 1, 1, 0, 0}, + /* FCC1 MII TX_ER */ + /* PA28 */ {CFG_FCC1, 1, 1, 1, 0, 0}, + /* FCC1 MII TX_EN */ + /* PA27 */ {CFG_FCC1, 1, 1, 0, 0, 0}, + /* FCC1 MII RX_DV */ + /* PA26 */ {CFG_FCC1, 1, 1, 0, 0, 0}, + /* FCC1 MII RX_ER */ + /* PA25 */ {CFG_AZ_RY_BY, 0, 0, 0, 0, 0}, + /* Rdy/Bsy flash */ + /* PA24 */ {CFG_AZ_FPGA, 0, 0, 0, 1, 1}, + /* FPGAINIT */ + /* PA23 */ {CFG_AZ_FPGA, 0, 0, 1, 0, 1}, + /* FPGAPROGRW */ + /* PA22 */ {CFG_AZ_FPGA, 0, 0, 1, 0, 1}, + /* FPGAPGM */ + /* PA21 */ {CFG_FCC1, 1, 0, 1, 0, 0}, + /* FCC1 MII TxD[3] */ + /* PA20 */ {CFG_FCC1, 1, 0, 1, 0, 0}, + /* FCC1 MII TxD[2] */ + /* PA19 */ {CFG_FCC1, 1, 0, 1, 0, 0}, + /* FCC1 MII TxD[1] */ + /* PA18 */ {CFG_FCC1, 1, 0, 1, 0, 0}, + /* FCC1 MII TxD[0] */ + /* PA17 */ {CFG_FCC1, 1, 0, 0, 0, 0}, + /* FCC1 MII RxD[0] */ + /* PA16 */ {CFG_FCC1, 1, 0, 0, 0, 0}, + /* FCC1 MII RxD[1] */ + /* PA15 */ {CFG_FCC1, 1, 0, 0, 0, 0}, + /* FCC1 MII RxD[2] */ + /* PA14 */ {CFG_FCC1, 1, 0, 0, 0, 0}, + /* FCC1 MII RxD[3] */ + /* PA13 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLLTIECLR */ + /* PA12 */ {CFG_AZ_PLL, 0, 0, 1, 0, 1}, + /* PLLSEL1 */ + /* PA11 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLLSEL0 */ + /* PA10 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLLTIEEN */ + /* PA9 */ {CFG_AZ_FAN, 1, 0, 0, 0, 0}, + /* FAN GOOD */ + /* PA8 */ {CFG_AZ_FAN, 1, 0, 1, 0, 0}, + /* FAN OFF */ + /* PA7 */ {CFG_AZ_CF, 0, 0, 0, 0, 0}, + /* CF car detect 1 */ + /* PA6 */ {CFG_AZ_CF, 0, 0, 0, 0, 0}, + /* CF car detect 2 */ + /* PA5 */ {CFG_AZ_EXALM, 0, 0, 0, 0, 0}, + /* Ext Alarm 0 */ + /* PA4 */ {CFG_AZ_EXALM, 0, 0, 0, 0, 0}, + /* Ext Alarm 1 */ + /* PA3 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0}, + /* CLK19 for MCC2 */ + /* PA2 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0}, + /* CLK20 for MCC2 */ + /* PA1 */ {CFG_AZ_FPGA, 0, 0, 0, 0, 0}, + /* FPGA busy */ + /* PA0 */ {CFG_AZ_FPGA, 0, 0, 0, 0, 0} + /* FPGA done */ + }, + + /* Port B */ + { /*conf ppar, psor, pdir, podr, pdat */ + /* PB31 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TXDB2 */ + /* PB30 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RXDB2 */ + /* PB29 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RSYNCB2 */ + /* PB28 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TSYNCB2 */ + /* PB27 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TXDC2 */ + /* PB26 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RXDC2 */ + /* PB25 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TSYNCC2 */ + /* PB24 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RSYNCC2 */ + /* PB23 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TXDD2 */ + /* PB22 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RXDD2 */ + /* PB21 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TSYNCD2 */ + /* PB20 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RSYNCD2 */ + /* PB19 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLL RESET */ + /* PB18 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0}, + /* PLL LOCK input */ + /* PB17 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* CLK17 MCC2 */ + /* PB16 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* CLK18 MCC2 */ + /* PB15 */ {CFG_AZ_SCC2, 1, 0, 0, 0, 0}, + /* SCC2 RXD */ + /* PB14 */ {CFG_AZ_SCC3, 1, 0, 0, 0, 0}, + /* SCC3 RXD */ + /* PB13 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0}, + /* PLL Normal input */ + /* PB12 */ {CFG_AZ_SCC2, 1, 1, 1, 0, 0}, + /* SCC2 TXD */ + /* PB11 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0}, + /* PLL Holdover */ + /* PB10 */ {CFG_AZ_PLL, 0, 0, 0, 0, 0}, + /* PLL Free run */ + /* PB9 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLL Fast Lock */ + /* PB8 */ {CFG_AZ_SCC3, 1, 0, 1, 0, 0}, + /* SCC3 TXD */ + /* PB7 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TXDA2 */ + /* PB6 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RXDA2 */ + /* PB5 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 TSYNCA2 */ + /* PB4 */ {CFG_AZ_MCC2, 1, 1, 0, 0, 0}, + /* MCC2 L1 RSYNCA2 */ + /* PB3 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}, + /* not available */ + /* PB2 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}, + /* not available */ + /* PB1 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}, + /* not available */ + /* PB0 */ {CFG_AZ_NA, 0, 0, 0, 0, 0} + /* not available */ + }, + + /* Port C */ + { /*conf ppar, psor, pdir, podr, pdat */ + /* PC31 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC30 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC29 */ {CFG_AZ_SCC2, 1, 0, 0, 0, 0}, + /* CLK3 SCC2 */ + /* PC28 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC27 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC26 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC25 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC24 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC23 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC22 */ {CFG_FCC1, 1, 0, 0, 0, 0}, + /* TxClk (CLK10) */ + /* PC21 */ {CFG_FCC1, 1, 0, 0, 0, 0}, + /* RxClk (CLK11) */ + /* PC20 */ {CFG_AZ_SCC2, 1, 0, 0, 0, 0}, + /* CLK12 SCC2 */ + /* PC19 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0}, + /* CLK13 MCC2 */ + /* PC18 */ {CFG_AZ_MCC2, 1, 0, 0, 0, 0}, + /* TxClk (CLK14) */ + /* PC17 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC16 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC15 */ {CFG_AZ_SCC1, 0, 0, 0, 0, 0}, + /* CTS for SCC1 */ + /* PC14 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC13 */ {CFG_AZ_FAN, 0, 0, 0, 0, 0}, + /* FAN present */ + /* PC12 */ {CFG_AZ_ESA, 0, 0, 0, 0, 0}, + /* ESA Relay good */ + /* PC11 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0}, + /* CTS for SCC3 */ + /* PC10 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0}, + /* CD for SCC3 */ + /* PC9 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0}, + /* CI for SCC3 */ + /* PC8 */ {CFG_AZ_SCC3, 0, 0, 0, 0, 0}, + /* DSR for SCC3 */ + /* PC7 */ {CFG_AZ_MDM, 0, 0, 1, 0, 0}, + /* MDM Reset */ + /* PC6 */ {CFG_AZ_MDM, 0, 0, 1, 0, 1}, + /* MDM CTR */ + /* PC5 */ {CFG_AZ_FAN, 0, 0, 1, 0, 1}, + /* FAN EE CS */ + /* PC4 */ {CFG_AZ_ESA, 1, 0, 0, 0, 0}, + /* ESA On */ + /* PC3 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PC2 */ {CFG_AZ_ADC, 0, 0, 0, 0, 1}, + /* ADC EOC IRQ */ + /* PC1 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLL MSEL1 */ + /* PC0 */ {CFG_AZ_PLL, 0, 0, 1, 0, 0}, + /* PLL MSEL0 */ + }, + + /* Port D */ + { /*conf ppar, psor, pdir, podr, pdat */ + /* PD31 */ {CFG_AZ_SCC1, 1, 0, 0, 0, 0}, + /* SCC1 RxD */ + /* PD30 */ {CFG_AZ_SCC1, 1, 1, 1, 0, 0}, + /* SCC1 TxD */ + /* PD29 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* SCC1 RTSnot used */ + /* PD28 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD27 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD26 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD25 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD24 */ {CFG_AZ_MEZZ, 0, 0, 0, 0, 0}, + /* Mezz present */ + /* PD23 */ {CFG_AZ_SCC3, 0, 0, 1, 0, 1}, + /* RTS SCC3 */ + /* PD22 */ {CFG_AZ_TSI, 0, 0, 1, 0, 0}, + /* TSI reset */ + /* PD21 */ {CFG_AZ_BP, 0, 0, 1, 0, 1}, + /* BP EE CS */ + /* PD20 */ {CFG_AZ_ADC, 0, 0, 1, 0, 1}, + /* ADC SEL */ + /* PD19 */ {CFG_AZ_UN, 0, 0, 1, 0, 1}, + /* unused */ + /* PD18 */ {CFG_AZ_SPI, 1, 1, 0, 0, 0}, + /* SPI CLK */ + /* PD17 */ {CFG_AZ_SPI, 1, 1, 0, 0, 0}, + /* SPI MOSI */ + /* PD16 */ {CFG_AZ_SPI, 1, 1, 0, 0, 0}, + /* SPI MISO */ + /* PD15 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD14 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD13 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD12 */ {CFG_AZ_UN, 0, 0, 1, 0, 1}, + /* unused */ + /* PD11 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD10 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD9 */ {CFG_AZ_SMC1, 1, 0, 1, 0, 0}, + /* SMC1 TXD */ + /* PD8 */ {CFG_AZ_SMC1, 1, 0, 0, 0, 0}, + /* SMC1 RXD */ + /* PD7 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD6 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD5 */ {CFG_AZ_UN, 0, 0, 1, 0, 0}, + /* unused */ + /* PD4 */ {CFG_AZ_FPGA, 0, 0, 1, 0, 1}, + /* FPGA PGMCS */ + /* PD3 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}, + /* not available */ + /* PD2 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}, + /* not available */ + /* PD1 */ {CFG_AZ_NA, 0, 0, 0, 0, 0}, + /* not available */ + /* PD0 */ {CFG_AZ_NA, 0, 0, 0, 0, 0} + /* not available */ + } +}; + +uint cta_upm_table[] = { + + /* Read single-beat (RSS) 0x00 */ + CTA_UPM_READ_CYCLE_RAM_WORD_0, + CTA_UPM_READ_CYCLE_RAM_WORD_1, + CTA_UPM_READ_CYCLE_RAM_WORD_2, + CTA_UPM_READ_CYCLE_RAM_WORD_3, + CTA_UPM_READ_CYCLE_RAM_WORD_4, + CTA_UPM_READ_CYCLE_RAM_WORD_5, + CTA_UPM_READ_CYCLE_RAM_WORD_6, + CTA_UPM_READ_CYCLE_RAM_WORD_7, + + /* Read burst (RBS) 0x08 */ + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + + /* 0x10 */ + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + + /* Write single-beat (WSS) 0x18 */ + CTA_UPM_WRITE_CYCLE_RAM_WORD_0, + CTA_UPM_WRITE_CYCLE_RAM_WORD_1, + CTA_UPM_WRITE_CYCLE_RAM_WORD_2, + CTA_UPM_WRITE_CYCLE_RAM_WORD_3, + CTA_UPM_WRITE_CYCLE_RAM_WORD_4, + CTA_UPM_WRITE_CYCLE_RAM_WORD_5, + CTA_UPM_WRITE_CYCLE_RAM_WORD_6, + UNUSED, + + /* Write burst (WBS) 0x20 */ + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + + /* Refresh timer (PTS) 0x30 */ + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + UNUSED, + + /* Exception condition (EXS) 0x3C */ + UNUSED, + UNUSED, + UNUSED, + UNUSED +}; + +long int initdram (int board_type) +{ + long int msize = CFG_SDRAM_SIZE; + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr = (vu_char *) CFG_SDRAM_BASE; + uchar c = 0xFF; + uint psdmr = CFG_PSDMR; + int i; + + immap->im_siu_conf.sc_ppc_acr = CFG_PPC_ACR; + immap->im_siu_conf.sc_ppc_alrh = CFG_PPC_ALRH; + immap->im_siu_conf.sc_tescr1 = CFG_TESCR1; + memctl->memc_mptpr = CFG_MPTPR; + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + /* Precharge all banks */ + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) { + *ramaddr = c; + } + /* Mode Register write */ + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + *ramaddr = c; +#endif /* !CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int board_early_init_f (void) +{ + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + uint table_size = sizeof (cta_upm_table) / sizeof (cta_upm_table[0]); + + /* Aztek CTA clock configuration settings */ + + immap->im_siu_conf.sc_sypcr = CFG_SYPCR; + immap->im_siu_conf.sc_swsr = CFG_SWSR; + immap->im_siu_conf.sc_ppc_acr = (unsigned char)CFG_PPC_ACR; + immap->im_siu_conf.sc_ppc_alrh = CFG_PPC_ALRH; + immap->im_siu_conf.sc_ppc_alrl = CFG_PPC_ALRL; + immap->im_siu_conf.sc_lcl_acr = (unsigned char)CFG_LCL_ACR; + immap->im_siu_conf.sc_lcl_alrh = CFG_LCL_ALRH; + immap->im_siu_conf.sc_lcl_alrl = CFG_LCL_ALRL; + immap->im_siu_conf.sc_tescr1 = CFG_TESCR1; + immap->im_siu_conf.sc_tescr2 = CFG_TESCR2; + immap->im_siu_conf.sc_ltescr1 = CFG_LTESCR1; + immap->im_siu_conf.sc_ltescr2 = CFG_LTESCR2; + immap->im_siu_conf.sc_pdtea = CFG_PDTEA; + immap->im_siu_conf.sc_pdtem = (unsigned char)CFG_PDTEM; + immap->im_siu_conf.sc_ldtea = CFG_LDTEA; + immap->im_siu_conf.sc_ldtem = (unsigned char)CFG_LDTEM; + + /* Aztek additional memory controller/upm settings */ + memctl->memc_mamr = CFG_CTA_MAMR_PRELIM; + memctl->memc_mbmr = CFG_CTA_MBMR_PRELIM; + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psdmr = CFG_PSDMR; + memctl->memc_psrt = CFG_PSRT; + memctl->memc_lsdmr = CFG_LSDMR; + memctl->memc_lsrt = CFG_LSRT; + + upmconfig (UPMA, cta_upm_table, table_size); + upmconfig (UPMB, cta_upm_table, table_size); + + return 0; +} + +int checkboard (void) +{ + /* the fpga status pins on PORT A GPIO register */ + uint status = 0; + uint *fpgaStatus = (uint *) 0xf0010d10; + int i = 100000; + + /* wait until the init done pin is ready */ + do { + if (!(FPGA_BUSY && *fpgaStatus)) + i--; + if (i == 0) + break; + + status = FPGA_DONE && *fpgaStatus; + } while (status == 0); + + uchar *fpgaVersion = (uchar *) 0x2002001f; + + printf ("Manuf: Aztek Networks, Inc.\n"); + printf ("Board: CTA5000S\n"); + + if (i == 0) + printf ("FPGA: did not initialize\n"); + else + printf ("FPGA: %d \n", *fpgaVersion); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +/* + * update "memory" property in the blob + */ +void ft_blob_update (void *blob, bd_t * bd) +{ + int ret; + + ret = fdt_fixup_memory (blob, + (u64) bd->bi_memstart, (u64) bd->bi_memsize); + + if (ret < 0) { + printf ("ft_blob_update): cannot set /memory/reg " + "property err:%s\n", fdt_strerror (ret)); + } + +} + +void ft_board_setup (void *blob, bd_t * bd) +{ + ft_cpu_setup (blob, bd); + ft_blob_update (blob, bd); +} +#endif +/* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#if defined (CONFIG_STATUS_LED) + +int misc_init_r (void) +{ + __led_init (0, 0); + return 0; +} + +void __led_toggle (led_id_t _msk) +{ + + *((uchar *) (CFG_LED_BASE)) ^= (0x30); + +} + +void __led_init (led_id_t _msk, int st) +{ + + *((uchar *) (CFG_LED_BASE)) = 0x20; +} + +void __led_set (led_id_t _msk, int _st) +{ + + if ((_st == STATUS_LED_ON)) + *((uchar *) (CFG_LED_BASE)) |= 0x10; + else + *((uchar *) (CFG_LED_BASE)) &= ~(0x10); + +} +#endif diff --git a/include/configs/cta5000s.h b/include/configs/cta5000s.h new file mode 100644 index 0000000..9b60038 --- /dev/null +++ b/include/configs/cta5000s.h @@ -0,0 +1,723 @@ +/* + * + * Aztek Networks CTA5000S board u-boot board support + * + * Copyright 2007 Aztek Networks, Inc. + * + * Authors: Scott Mann smann@azteknetworks.net + * jblack jblack@azteknetworks.com + * + * Based on: U-Boot configuration for Analogue&Micro Rattler boards. + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen yuli@arabellasw.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC8260 1 +#define CONFIG_CPM2 1 /* Has a CPM2 */ +#define CONFIG_CTA5000S 1 +#define CPU_ID_STR "MPC8250" + +#define CONFIG_MISC_INIT_R + +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define STATUS_LED_BIT 0x10 +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#define CFG_LED_BASE 0x2002000E + +/* in Hz - this is actually the bus speed. CPU speed is determined by + * bus speed and multiplier (which is 2). Core speed is 132MHz and CPM + * is also 132MHz + */ +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 +#endif + +/* + * Flat Device Tree setup + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,8250@0" +#define OF_SOC "soc@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a00" + +/* + * Debug Features + */ +/* remember to undef for prime time */ +#undef DEBUG +/* Causes an infinite loop to run that allows time for attaching gdb */ +#undef CONFIG_GDB_ENTRY_POINT + +/* run the cta5000s init code from flash */ +/* look in include/common.h for more initialization options */ +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* Allow serial number and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#undef CONFIG_CONS_ON_SMC /* Console is not on SMC */ +#define CONFIG_CONS_ON_SCC /* Console is on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SCC1 is used for console */ + +#define CONFIG_BAUDRATE 115200 +/* + * based on a 1.03MHZ BRG Input Clock + * 0.070% error on the low end, 0.536% error on the high end + */ +#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#ifdef CONFIG_ETHER_ON_FCC + +#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ + +#if (CONFIG_ETHER_INDEX == 1) + +/* - Rx clock is CLK11 + * - Tx clock is CLK10 + * - BDs/buffers on 60x bus + * - Full duplex + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +/*#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)*/ +#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#elif (CONFIG_ETHER_INDEX == 2) + +/* - Rx clock is CLK15 + * - Tx clock is CLK14 + * - BDs/buffers on 60x bus + * - Full duplex + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_INDEX */ + +#undef CONFIG_MII /* MII PHY management */ +#undef CONFIG_BITBANGMII /* Bit-banged MDIO interface */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ + else iop->pdat &= ~0x00800000 + +#define MIIDELAY udelay(1) + +/* + * dont want gratuitous arp packets at power up to cause + * duplicate MAC issues in manufacturing +*/ +#define CONFIG_ETHADDR 00:00:00:01:01:01 +#endif /* CONFIG_ETHER_ON_FCC */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Supported Commands +*/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_BSP /* Board Specific functions */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#undef CONFIG_CMD_DIAG /* Diagnostics */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#undef CONFIG_CMD_EEPROM /* EEPROM read/write support */ +#define CONFIG_CMD_ENV /* saveenv */ +#undef CONFIG_CMD_EXT2 /* EXT2 Support */ +#undef CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_IDE /* IDE harddisk support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_IMMAP /* IMMR dump support */ +#define CONFIG_CMD_IRQ /* irqinfo */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_PORTIO /* Port I/O */ +#define CONFIG_CMD_REGINFO /* Register dump */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#undef CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ +#undef CONFIG_CMD_SPI /* SPI utility */ +#undef CONFIG_CMD_KGDB + +/* + * I2C + */ +/* EEPROM Configuration */ +/* enable I2C and select the hardware/software driver */ +#if defined(CONFIG_CMD_I2C) +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_I2C_CMD_TREE +#define I2C_PORT 3 /* pins are on Port D */ +#endif + +/* + * SPI + */ +#if defined(CONFIG_CMD_SPI) +#define CONFIG_SPI +#define CONFIG_HARD_SPI +#define CONFIG_MPC8XXX_SPI +#endif + +/* + * FPGA Control +*/ + +#if defined(CONFIG_CMD_FPGA) +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_COUNT 1 +#endif +#define FPGA_DONE 0x80000000 +#define FPGA_BUSY 0x40000000 + + + +/* + * Whatever CFG_RESET_ADDRESS is set to, it needs to be invalid + * so that it will cause a machine check and thus a reset + * 0xC0000000 is invalid (see cta Programmers guide v3) + */ +#define CFG_RESET_ADDRESS 0xC0000000 + +/* ide disk partitions */ +#if defined(CONFIG_CMD_IDE) +#define CONFIG_ISO_PARTITION +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR 0x20000000 +#define CFG_ATA_DATA_OFFSET 0x00000000 +#define CFG_ATA_REG_OFFSET 0x00000000 +#define CFG_ATA_ALT_OFFSET 0x00010000 +#endif + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_BOOTCOMMAND /* autoboot command */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"" \ + " to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ipaddr=192.168.1.10\0" \ + "serverip=192.168.1.20\0" \ + "gatewayip=192.168.1.1\0" \ + "netmask=255.255.255.0\0" \ + "rootpath=/opt/eldk/4.1/ppc_82xx\0" \ + "bootfile=uImage-2.6.19.2-nfs\0" \ + "kernel_addr=fe050000\0" \ + "ramdisk_addr=fe150000\0" \ + "hostname=5000S\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_nfs" + +/* + * Debugging Support + */ +#if defined(CONFIG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif +/* include support for bzip2 compressed images */ +#define CONFIG_BZIP2 +#undef CONFIG_WATCHDOG /* disable cpu specific watchdog */ + +/* + * Command Line Support + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ + +/* + * Debugging Support + */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03000000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * CFG_FLASH_BASE is the boot flash base address + */ +#define CFG_FLASH_PROTECTION 1 /* Real (hardware) sectors protection */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */ + +#define CFG_DIRECT_FLASH_TFTP + +#if defined(CONFIG_CMD_JFFS2) +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS +#define CFG_JFFS2_SORT_FRAGMENTS + +/* + * JFFS2 partitions + * + */ + +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cta5000s-0" +#define MTDPARTS_DEFAULT "mtdparts=cta5000s-0:256k(u-boot)," \ + "64k(env),1344k(kernel),-(frdisk)\0" +#define CFG_JFFS2_FIRST_SECTOR 29 +#define CFG_JFFS2_FIRST_BANK 1 +#define CFG_JFFS_SINGLE_PART 1 +#endif /* CFG_CMD_JFFS2 */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ + +#define CFG_ENV_IS_IN_FLASH + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (64 * 1024) /* Reserve 32 kB for env */ +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_SIZE 2 /* 2MB of boot flash */ +#endif /* CFG_ENV_IS_IN_FLASH */ + +#define CFG_IMMR 0xF0000000 +#define CFG_UHW_IMMR 0xF000 /* upper half word */ + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size/bytes reserved for initial */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 64 /* in MB */ + +/* + * Hard reset configuration word + * BIT Neumonic Value + * 0 EARB 0 External Arbitration is disabled + * 1 EXMC 0 External Memory Controller is not present + * 2 CDIS 0 Core is Active + * 3 EBM 0 External Bus mode + * 4-5 BPS 10 16 Bit Boot Port Size + * 6 CIP 1 Exceptions are vectored to 0x000n_nnnn + * 7 ISPS 0 Internal Port Size + * 8-9 L2CPC 01 L2 Cache Pins + * 10-11 DPPC 01 Data Parity pin + * 12 0 Reserved + * 13-15 ISB 100 Internal Space Base Select is 0xF000_0000 + * 16 BMS 1 Boot Memory Space, LOMEM, 0x0000_0000 + * 17 BBD 0 Bus Busy Disable + * 18-19 MMR 00 Mask Masters Request + * 20-21 LBPC 00 Local Bus Pin Configuration + * 22-23 APPC 11 Address Parity Pin Configuration + * 24-25 CS10PC 01 CS10 Pin Configuration + * 26 ALD_EN 0 CP Auto load is disabled + * 27 0 Reserved + * 28-31 MODCK_H 101 Clock Reset, (PCI_MODE pin is high) + * +*/ + +#define CFG_HRCW_MASTER (HRCW_BPS10 |\ + HRCW_CIP |\ + HRCW_L2CPC01 |\ + HRCW_DPPC01 |\ + HRCW_ISB100 |\ + HRCW_BMS |\ + HRCW_APPC11 |\ + HRCW_CS10PC01 |\ + HRCW_MODCK_H0101) + +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) +#define CFG_HID2 0 + +/************************************************************************** + * SIUMCR, SIU Memory Config. Register. + * This register should be initialized prior to making any of the memory + * spaces valid. Other regeisters in this list are related to the system + * clock. + *************************************************************************/ +#define CFG_SIUMCR 0x25340000 +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_SWSR 0x0000 +#define CFG_BCR 0x00000000 +#define CFG_PPC_ACR 0x02 +#define CFG_PPC_ALRH 0x01234567 +#define CFG_PPC_ALRL 0x89ABCDEF +#define CFG_LCL_ACR 0x02 +#define CFG_LCL_ALRH 0x01234567 +#define CFG_LCL_ALRL 0x89ABCDEF +#define CFG_TESCR1 0x00000000 +#define CFG_TESCR2 0x00000000 +#define CFG_LTESCR2 0x00000000 +#define CFG_LTESCR1 0x00000000 +#define CFG_PDTEA 0x00000000 +#define CFG_PDTEM 0x00 +#define CFG_LDTEA 0x00000000 +#define CFG_LDTEM 0x00 +/* SCCR_DFBR01 is 0x00000001 see cpu/mpc8260.c */ +#define CFG_SCCR SCCR_DFBRG01 + +/* Aztek values */ +#define CFG_RMR 0x00000000 +#define CFG_TMCNTSC 0x00000000 +#define CFG_PISCR 0x00000000 +#define CFG_RCCR 0 + +/* + * From live sys: PSDMR = 0xa4b70000, but RedBoot halMemoryMap.h reports + * value below as "initial" + */ +#define CFG_PSDMR 0xc34da4b6 +#define CFG_PSRT 0x1e +#define CFG_LSDMR 0x00008f00 +#define CFG_LSRT 0x8f +#define CFG_MPTPR 0x1f00 + +/************************************************************************** + * Memory Map From CT Programmers Guide + * -------------------------------------------- + * Address Range Bytes Data Bus Bits Function + * 0x00000000 - 0x01FFFFFF 0x04000000 64 SDRAM + * 0x20000000 - 0x20000010 0x00000010 16 Compact Flash, task + * file access (IO) + * 0x20010000 - 0x20010010 0x00000010 16 CompactFlash, + * alternate status & + * device control (CTRL) + * 0x20020000 - 0x200200FF 0x00000100 8 FPGA + * 0x20030000 - 0x200300FF 0x00000100 8 CPU CPLD + * 0x20040000 - 0x20041FFF 0x00002000 8 Framer Block + * 0x20050000 - 0x20057FFF 0x00008000 16 TSI + * 0xF0000000 - 0xF001FFFF 0x00020000 Various Internal Memory + * 0xFE000000 - 0xFE1FFFFF 0x00200000 16 Boot FLASH + *************************************************************************/ + +/* Base Address definitions */ +#define CFG_COMPACT_FLASH_IO_BASE (0x20000000) +#define CFG_COMPACT_FLASH_CTRL_BASE (0x20010000) +#define CFG_FPGA_BASE (0x20020000) +#define CFG_CPU_CPLD_BASE (0x20030000) +#define CFG_FRAMER_BASE (0x20040000) +#define CFG_TSI_BASE (0x20050000) + +/* Boot flash memory space */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_SCY_2_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/* 1 bank of SDRAM on 60x bus */ +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_DECC_ECC |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM ((MEG_TO_AM(CFG_SDRAM_SIZE) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +/* Compact Flash Control Registers + */ +#define CFG_BR2_PRELIM ((CFG_COMPACT_FLASH_CTRL_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_UPMB |\ + BRx_V) + +#define CFG_OR2_PRELIM (ORxU_AM_MSK |\ + ORxU_BCTLD |\ + ORxU_BI |\ + ORxU_EHTR_1IDLE) + +/* Compact Flash IO memory + */ +#define CFG_BR3_PRELIM ((CFG_COMPACT_FLASH_IO_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_UPMB |\ + BRx_V) + +#define CFG_OR3_PRELIM (ORxU_AM_MSK |\ + ORxU_BCTLD |\ + ORxU_BI |\ + ORxU_EHTR_1IDLE) + +/* FPGA memory + */ +#define CFG_BR4_PRELIM ((CFG_FPGA_BASE & BRx_BA_MSK) |\ + BRx_MS_GPCM_P |\ + BRx_PS_8 |\ + BRx_V) + +#define CFG_OR4_PRELIM (ORxG_AM_MSK |\ + ORxG_SCY_1_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/* CPU CPLD memory space + */ +#define CFG_BR5_PRELIM ((CFG_CPU_CPLD_BASE & BRx_BA_MSK) |\ + BRx_MS_GPCM_P |\ + BRx_PS_8 |\ + BRx_V) + +#define CFG_OR5_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_1_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + + +/* Framer memory space + */ +#define CFG_BR6_PRELIM ((CFG_FRAMER_BASE & BRx_BA_MSK) |\ + BRx_MS_GPCM_P |\ + BRx_PS_8 |\ + BRx_V) + +#define CFG_OR6_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_8_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/* Time Slot Interchange + */ +#define CFG_BR7_PRELIM ((CFG_TSI_BASE & BRx_BA_MSK)|\ + BRx_MS_GPCM_P |\ + BRx_PS_16 |\ + BRx_V) + +#define CFG_OR7_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_6_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +#define CFG_CTA_MAMR_PRELIM (MxMR_BSEL |\ + MxMR_OP_NORM |\ + MxMR_AMx_TYPE_0 |\ + MxMR_DSx_1_CYCL |\ + MxMR_RLFx_16X |\ + MxMR_WLFx_16X |\ + MxMR_TLFx_16X) + +/* Note: UPM B has same configuration as UPM A + */ +#define CFG_CTA_MBMR_PRELIM (CFG_CTA_MAMR_PRELIM) + +/************************************************************************ + * Initial values for UPM RAM, for compactFlash read cycles + * Both compactFlash memory spaces use the same timing. + * + * The values for UPM RAM are described in the CTA Programmer's Guide. + ***********************************************************************/ +#define CTA_UPM_READ_CYCLE_NUM_RAM_WORDS (8) +#define CTA_UPM_WRITE_CYCLE_NUM_RAM_WORDS (7) + +#define CTA_UPM_READ_CYCLE_RAM_WORD_0 (0xcffffc00) +#define CTA_UPM_READ_CYCLE_RAM_WORD_1 (0x0fffff00) +#define CTA_UPM_READ_CYCLE_RAM_WORD_2 (0x0ffffc00) +#define CTA_UPM_READ_CYCLE_RAM_WORD_3 (0x0ff3c800) +#define CTA_UPM_READ_CYCLE_RAM_WORD_4 (0x0ff3c800) +#define CTA_UPM_READ_CYCLE_RAM_WORD_5 (0x0ff3fc84) +#define CTA_UPM_READ_CYCLE_RAM_WORD_6 (0x0ffffc00) +#define CTA_UPM_READ_CYCLE_RAM_WORD_7 (0x2ffffc01) + +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_0 (0xcffffc00) +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_1 (0x0fffff00) +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_2 (0x0ffffc00) +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_3 (0x0ffcfc80) +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_4 (0x0ffcfc80) +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_5 (0x0ffffc00) +#define CTA_UPM_WRITE_CYCLE_RAM_WORD_6 (0x3ffffc05) +#define UNUSED 0xFFFFFFFF + +/* + * Some Aztek specific CTA defines + * - used in cta5000s.c + * - initial values in cta5000s.c all from Ch. 6 of + * cta Progammers Manual rev 3 + */ +#define CFG_AZ_FPGA 1 +#define CFG_AZ_CF 1 +#define CFG_AZ_FAN 1 +#define CFG_AZ_ADC 1 +#define CFG_AZ_RY_BY 1 +#define CFG_AZ_EXALM 1 +#define CFG_AZ_ESA 1 +#define CFG_AZ_MDM 1 +#define CFG_AZ_PLL 1 +#define CFG_AZ_SPI 1 +#define CFG_AZ_TSI 1 +#define CFG_AZ_MEZZ 1 +#define CFG_AZ_BP 1 +#define CFG_AZ_SCC1 1 +#define CFG_AZ_SCC2 0 +#define CFG_AZ_SCC3 1 +#define CFG_AZ_SMC1 0 +#define CFG_AZ_MCC1 0 +#define CFG_AZ_MCC2 1 +#define CFG_AZ_NA 0 /* not available */ +#define CFG_AZ_UN 0 /* unused */ + +#endif /* __CONFIG_H */

On Wednesday 14 May 2008, Jim Black wrote:

---

CREDITS | 12 ++++++++++++ MAINTAINERS | 8 ++++++++ MAKEALL | 1 + Makefile | 3 +++ 4 files changed, 24 insertions(+), 0 deletions(-)

<snip>

+++ b/MAINTAINERS @@ -50,6 +50,10 @@ Jerry Van Baren gerald.vanbaren@smiths-aerospace.com

sacsng MPC8260

+Jim Black jblack@azteknetworks.com

• cta5000s MPC8250

Oliver Brown obrown@adventnetworks.com

gw8260 MPC8260 @@ -194,6 +198,10 @@ Howard Gray mvsensor@matrix-vision.de

MVS1 MPC823

+Jeffrey Haemer jhaemer@azteknetworks.com

• cta5000s MPC8250

Two maintainers for one board? This could cause problems. I suggest that you internally decide who will be "officially" responsible.

Thanks.

Best regards, Stefan

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