[PATCH 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay
Clock delay in RGMII is required for some boards. This patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and CONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting proper bits in PORT_REG_PHYS_CTRL register.
Cc: Chris Packham judge.packham@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Anatolij Gustschin agust@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Pawel Dembicki paweldembicki@gmail.com --- drivers/net/phy/mv88e61xx.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 5aff7ed397..889327639d 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -94,6 +94,8 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14) #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) @@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) PORT_REG_PHYS_CTRL_SPD1000; }
- if (port == CONFIG_MV88E61XX_CPU_PORT) + if (port == CONFIG_MV88E61XX_CPU_PORT) { val |= PORT_REG_PHYS_CTRL_LINK_VALUE | PORT_REG_PHYS_CTRL_LINK_FORCE; +#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY) + val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY; +#endif +#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY) + val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY; +#endif + }
return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, val);
This patch add MV88E6171 id to driver data.
Tested on Checkpoint L-50 board.
Cc: Chris Packham judge.packham@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Anatolij Gustschin agust@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Pawel Dembicki paweldembicki@gmail.com --- drivers/net/phy/mv88e61xx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 889327639d..e0b648a54e 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -180,6 +180,7 @@ #define PORT_SWITCH_ID_6071 0x0710 #define PORT_SWITCH_ID_6096 0x0980 #define PORT_SWITCH_ID_6097 0x0990 +#define PORT_SWITCH_ID_6171 0x1710 #define PORT_SWITCH_ID_6172 0x1720 #define PORT_SWITCH_ID_6176 0x1760 #define PORT_SWITCH_ID_6220 0x2200 @@ -997,6 +998,7 @@ static int mv88e61xx_probe(struct phy_device *phydev) switch (priv->id) { case PORT_SWITCH_ID_6096: case PORT_SWITCH_ID_6097: + case PORT_SWITCH_ID_6171: case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: case PORT_SWITCH_ID_6240: @@ -1152,6 +1154,17 @@ static struct phy_driver mv88e61xx_driver = { .shutdown = &genphy_shutdown, };
+static struct phy_driver mv88e617x_driver = { + .name = "Marvell MV88E617x", + .uid = 0x01410e70, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + static struct phy_driver mv88e609x_driver = { .name = "Marvell MV88E609x", .uid = 0x1410c89, @@ -1177,6 +1190,7 @@ static struct phy_driver mv88e6071_driver = { int phy_mv88e61xx_init(void) { phy_register(&mv88e61xx_driver); + phy_register(&mv88e617x_driver); phy_register(&mv88e609x_driver); phy_register(&mv88e6071_driver);
On Sat, Apr 11, 2020 at 09:28:24PM +0200, Pawel Dembicki wrote:
Clock delay in RGMII is required for some boards. This patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and CONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting proper bits in PORT_REG_PHYS_CTRL register.
Cc: Chris Packham judge.packham@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Anatolij Gustschin agust@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Pawel Dembicki paweldembicki@gmail.com
drivers/net/phy/mv88e61xx.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 5aff7ed397..889327639d 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -94,6 +94,8 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14) #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) @@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) PORT_REG_PHYS_CTRL_SPD1000; }
- if (port == CONFIG_MV88E61XX_CPU_PORT)
- if (port == CONFIG_MV88E61XX_CPU_PORT) { val |= PORT_REG_PHYS_CTRL_LINK_VALUE | PORT_REG_PHYS_CTRL_LINK_FORCE;
+#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY)
val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;+#endif +#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY)
val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;+#endif
}
return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, val);
Two problems. First, you cannot add new CONFIG symbols that are not in Kconfig. Second, similar to Chris' comment in "net: mvgbe: add support for differ PHY addresses" this should likely come via the device tree I suspect. Thanks!
participants (2)
-
Pawel Dembicki -
Tom Rini