[U-Boot] [PATCH v2 1/8] imx: mx6 correct is_soc_rev usage
is_soc_rev should return a bool value, so use "==", but not "-", change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0). This patch also add space between "&" for cpu_type(rev) macro.
Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: new patch
arch/arm/imx-common/timer.c | 4 ++-- arch/arm/include/asm/arch-mx6/sys_proto.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index e522990..c12556a 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -44,8 +44,8 @@ static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && - (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) + (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) return 1;
return 0; diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c583291..9756708 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -12,7 +12,7 @@ #include "../arch-imx/cpu.h"
#define soc_rev() (get_cpu_rev() & 0xFF) -#define is_soc_rev(rev) (soc_rev() - rev) +#define is_soc_rev(rev) (soc_rev() == rev)
u32 get_nr_cpus(void); u32 get_cpu_rev(void); @@ -20,7 +20,7 @@ u32 get_cpu_speed_grade_hz(void); u32 get_cpu_temp_grade(int *minc, int *maxc);
/* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12)&0xff) +#define cpu_type(rev) (((rev) >> 12) & 0xff)
/* both macros return/take MXC_CPU_ constants */ #define get_cpu_type() (cpu_type(get_cpu_rev()))
The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor |
We also need to account for Major Lower.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: split from PATCH v1 2/8. This piece code should be in a single patch.
arch/arm/cpu/armv7/mx6/soc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index b21bd03..29de624 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); + u32 major;
if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) }
} + major = ((reg >> 8) & 0xff); reg &= 0xff; /* mx6 silicon revision */ - return (type << 12) | (reg + 0x10); + return (type << 12) | (reg + (0x10 * (major + 1))); }
/*
On 11/06/2015 12:30, Peng Fan wrote:
The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor |
We also need to account for Major Lower.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2: split from PATCH v1 2/8. This piece code should be in a single patch.
arch/arm/cpu/armv7/mx6/soc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index b21bd03..29de624 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff);
u32 major;
if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog);
@@ -79,8 +80,9 @@ u32 get_cpu_rev(void) }
}
- major = ((reg >> 8) & 0xff); reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
- return (type << 12) | (reg + (0x10 * (major + 1)));
}
/*
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: Split from PATCH v1 2/8, use soc_rev but not is_soc_rev
arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + arch/arm/include/asm/arch-mx6/sys_proto.h | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 0d38d45..35a324c 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -312,6 +312,7 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 +#define CHIP_REV_2_0 0x20 #ifndef CONFIG_MX6SX #define IRAM_SIZE 0x00040000 #else diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 9756708..28c77a4 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const);
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_2_0)) + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()
On 11/06/2015 12:30, Peng Fan wrote:
Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2: Split from PATCH v1 2/8, use soc_rev but not is_soc_rev
arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + arch/arm/include/asm/arch-mx6/sys_proto.h | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 0d38d45..35a324c 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -312,6 +312,7 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 +#define CHIP_REV_2_0 0x20 #ifndef CONFIG_MX6SX #define IRAM_SIZE 0x00040000 #else diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 9756708..28c77a4 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const);
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \(soc_rev() >= CHIP_REV_2_0))/*
- Initializes on-chip ethernet controllers.
- to override, implement board_eth_init()
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
In c files, use runtime check and discard #ifdef.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference, only used in header files for different bits. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: 1. Remove #ifdef, but use runtime check 2. A few bit definitions are introduced in c files, because to other platforms the macro will make compilation fail, also there are no other places refer the bit macro definitions.
arch/arm/cpu/armv7/mx6/clock.c | 33 ++++++++++++++++++++++---------- arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 33 +++++++++++++++++--------------- include/configs/mx6_common.h | 3 +++ 4 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ae99945..0d862b2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -323,10 +323,13 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) - if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) - return MXC_HCLK; /* OSC 24Mhz */ -#endif + if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || + is_mx6dqp()) { +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ + } + perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1); @@ -337,10 +340,14 @@ static u32 get_uart_clk(void) u32 reg, uart_podf; u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) - if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) - freq = MXC_HCLK; -#endif + + if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || + is_mx6dqp()) { +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) + if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) + freq = MXC_HCLK; + } + reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
@@ -352,8 +359,14 @@ static u32 get_cspi_clk(void) u32 reg, cspi_podf;
reg = __raw_readl(&imx_ccm->cscdr2); - reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; - cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + + if (is_mx6dqp()) { +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) + if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) + return MXC_HCLK / (cspi_podf + 1); + }
return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 29de624..bcfa2f6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val) static void clear_mmdc_ch_mask(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */ - writel(0, &mxc_ccm->ccdr); + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + writel(reg, &mxc_ccm->ccdr); }
static void init_bandgap(void) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 887d048..2ff1005 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -113,7 +113,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP)) #define MXC_CCM_CCR_OSCNT_MASK 0x7F #else #define MXC_CCM_CCR_OSCNT_MASK 0xFF @@ -123,6 +123,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +#ifdef CONFIG_MX6QP +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) +#endif
/* Define the bits in register CSR */ #define MXC_CCM_CSR_COSC_READY (1 << 5) @@ -196,7 +199,11 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 #ifndef CONFIG_MX6SX +#ifdef CONFIG_MX6QP +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) +#else #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) +#endif #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) #endif
@@ -230,7 +237,6 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 #endif #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 #endif #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F @@ -244,15 +250,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP)) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 +#endif #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 -#else -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 -#endif
/* Define the bits in register CSCDR1 */ #ifndef CONFIG_MX6SX @@ -273,15 +276,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #endif -#ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#else #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F -#ifdef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#endif -#endif #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */ @@ -316,10 +311,17 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) + +#ifdef CONFIG_MX6QP +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x7) << 15) +#else #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) #endif +#endif #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) @@ -384,6 +386,7 @@ struct mxc_ccm_reg { /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 + /* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 50370e1..b5de280 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -30,6 +30,9 @@
#define CONFIG_MP #define CONFIG_MXC_GPT_HCLK +#ifdef CONFIG_MX6QP +#define CONFIG_MX6Q +#endif
#define CONFIG_SYS_NO_FLASH
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
In c files, use runtime check and discard #ifdef.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference, only used in header files for different bits. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2:
- Remove #ifdef, but use runtime check
- A few bit definitions are introduced in c files, because to other platforms the macro will make compilation fail, also there are no other places refer the bit macro definitions.
arch/arm/cpu/armv7/mx6/clock.c | 33 ++++++++++++++++++++++---------- arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 33 +++++++++++++++++--------------- include/configs/mx6_common.h | 3 +++ 4 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ae99945..0d862b2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -323,10 +323,13 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */-#endif
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
is_mx6dqp()) {+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
I am missing why the define is set here and dropped from crm_regs.h. This makes the defines split between code (clock.c) and header (crm_regs.h), and make harder to read and to find them.
I am also missing if the goal to have runtime checked is really reached. The MX6QuadPlus is (please correct me if I am wrong) pin compatible with Quad. If it is, we lose the possibility to have a single binary for all SOC variants that a board can mount.
This is more evident for the code you surround with #ifdef CONFIG_MX6QP - I mean, it is fully ok if you add new defines to crm_regs.h: they do not conflict with the old ones. But if you redefine some of them, the SOC must be decided at compile time. Having a single binary (of course, for SOC variants where it is possible) is a feture we get with big efforts and we should not remove it.
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)return MXC_HCLK; /* OSC 24Mhz */}
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
@@ -337,10 +340,14 @@ static u32 get_uart_clk(void) u32 reg, uart_podf; u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;-#endif
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
is_mx6dqp()) {+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)freq = MXC_HCLK;- }
- reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
@@ -352,8 +359,14 @@ static u32 get_cspi_clk(void) u32 reg, cspi_podf;
reg = __raw_readl(&imx_ccm->cscdr2);
- reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
- cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;- if (is_mx6dqp()) {
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)return MXC_HCLK / (cspi_podf + 1);}
return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
} diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 29de624..bcfa2f6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val) static void clear_mmdc_ch_mask(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg;
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- writel(0, &mxc_ccm->ccdr);
- reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
- writel(reg, &mxc_ccm->ccdr);
}
static void init_bandgap(void) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 887d048..2ff1005 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -113,7 +113,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP)) #define MXC_CCM_CCR_OSCNT_MASK 0x7F #else #define MXC_CCM_CCR_OSCNT_MASK 0xFF @@ -123,6 +123,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +#ifdef CONFIG_MX6QP +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) +#endif
/* Define the bits in register CSR */ #define MXC_CCM_CSR_COSC_READY (1 << 5) @@ -196,7 +199,11 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 #ifndef CONFIG_MX6SX +#ifdef CONFIG_MX6QP +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) +#else #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) +#endif #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) #endif
@@ -230,7 +237,6 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 #endif #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 #endif #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F @@ -244,15 +250,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP)) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 +#endif #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 -#else -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 -#endif
/* Define the bits in register CSCDR1 */ #ifndef CONFIG_MX6SX @@ -273,15 +276,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #endif -#ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#else #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F -#ifdef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#endif -#endif #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */ @@ -316,10 +311,17 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
+#ifdef CONFIG_MX6QP +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x7) << 15) +#else #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) #endif +#endif
This is an example about my concerns I tried to explain above.
Best regards, Stefano Babic
Hi Stefano,
On Sat, Jun 27, 2015 at 06:44:25PM +0200, Stefano Babic wrote:
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes.
In c files, use runtime check and discard #ifdef.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference, only used in header files for different bits. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2:
- Remove #ifdef, but use runtime check
- A few bit definitions are introduced in c files, because to other platforms the macro will make compilation fail, also there are no other places refer the bit macro definitions.
arch/arm/cpu/armv7/mx6/clock.c | 33 ++++++++++++++++++++++---------- arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- arch/arm/include/asm/arch-mx6/crm_regs.h | 33 +++++++++++++++++--------------- include/configs/mx6_common.h | 3 +++ 4 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ae99945..0d862b2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -323,10 +323,13 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */-#endif
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
is_mx6dqp()) {+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
I am missing why the define is set here and dropped from crm_regs.h. This makes the defines split between code (clock.c) and header (crm_regs.h), and make harder to read and to find them.
I am also missing if the goal to have runtime checked is really reached. The MX6QuadPlus is (please correct me if I am wrong) pin compatible with Quad. If it is, we lose the possibility to have a single binary for all SOC variants that a board can mount.
This is more evident for the code you surround with #ifdef CONFIG_MX6QP
- I mean, it is fully ok if you add new defines to crm_regs.h: they do
not conflict with the old ones. But if you redefine some of them, the SOC must be decided at compile time. Having a single binary (of course, for SOC variants where it is possible) is a feture we get with big efforts and we should not remove it.
Will move the macros to crm_regs.h.
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)return MXC_HCLK; /* OSC 24Mhz */}
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
@@ -337,10 +340,14 @@ static u32 get_uart_clk(void) u32 reg, uart_podf; u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;-#endif
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
is_mx6dqp()) {+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)freq = MXC_HCLK;- }
- reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
@@ -352,8 +359,14 @@ static u32 get_cspi_clk(void) u32 reg, cspi_podf;
reg = __raw_readl(&imx_ccm->cscdr2);
- reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
- cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;- if (is_mx6dqp()) {
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)return MXC_HCLK / (cspi_podf + 1);}
return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
} diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 29de624..bcfa2f6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val) static void clear_mmdc_ch_mask(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg;
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- writel(0, &mxc_ccm->ccdr);
- reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
- writel(reg, &mxc_ccm->ccdr);
}
static void init_bandgap(void) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 887d048..2ff1005 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -113,7 +113,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP)) #define MXC_CCM_CCR_OSCNT_MASK 0x7F #else #define MXC_CCM_CCR_OSCNT_MASK 0xFF @@ -123,6 +123,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +#ifdef CONFIG_MX6QP +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) +#endif
/* Define the bits in register CSR */ #define MXC_CCM_CSR_COSC_READY (1 << 5) @@ -196,7 +199,11 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 #ifndef CONFIG_MX6SX +#ifdef CONFIG_MX6QP +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) +#else #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) +#endif #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) #endif
@@ -230,7 +237,6 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 #endif #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 #endif #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F @@ -244,15 +250,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#ifdef CONFIG_MX6SX +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP)) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 +#endif #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 -#else -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 -#endif
/* Define the bits in register CSCDR1 */ #ifndef CONFIG_MX6SX @@ -273,15 +276,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #endif -#ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#else #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F -#ifdef CONFIG_MX6SX -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#endif -#endif #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */ @@ -316,10 +311,17 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
+#ifdef CONFIG_MX6QP +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x7) << 15) +#else #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) #endif +#endif
This is an example about my concerns I tried to explain above.
Best regards, Stefano Babic
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================
Regards, Peng.
--
From: "Ye.Li" B37916@freescale.com
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP.
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: None
arch/arm/cpu/armv7/mx6/hab.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c index 8dee595..bf7dbf0 100644 --- a/arch/arm/cpu/armv7/mx6/hab.c +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -252,7 +252,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) * do cache flushes. don't think any * exist, so we ignore them. */ - writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); + if (!is_mx6dqp()) + writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); } else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) { writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Bypass QoS for IPU and increase bankwidth threshold for PRE to get better performance for video.
Signed-off-by: Peng Fan Peng.Fan@freescale.com Signed-off-by: Brown Oliver B37094@freescale.com Signed-off-by: Ye.Li B37916@freescale.com ---
Changes v2: 1. runtime check 2. introduce ipu qos settings for better performance
arch/arm/cpu/armv7/mx6/clock.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 0d862b2..7106df0 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -862,6 +862,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) }
#ifndef CONFIG_MX6SX +static void ipu_qos_setting(void) +{ + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000010, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000010, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000010, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000010, 0x00bb0814); +} + void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -869,7 +893,22 @@ void enable_ipu_clock(void) reg = readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); + + if (is_mx6dqp()) { +#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) + reg = readl(&mxc_ccm->CCGR6); + reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK; + writel(reg, &mxc_ccm->CCGR6); + + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU2_IPU_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* See Network Interconnect Bus for detailed info */ + ipu_qos_setting(); + } } + #endif /***************************************************/
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Bypass QoS for IPU and increase bankwidth threshold for PRE to get better performance for video.
Signed-off-by: Peng Fan Peng.Fan@freescale.com Signed-off-by: Brown Oliver B37094@freescale.com Signed-off-by: Ye.Li B37916@freescale.com
Changes v2:
- runtime check
- introduce ipu qos settings for better performance
arch/arm/cpu/armv7/mx6/clock.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 0d862b2..7106df0 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -862,6 +862,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) }
#ifndef CONFIG_MX6SX +static void ipu_qos_setting(void) +{
- /* Bypass IPU1 QoS generator */
- writel(0x00000002, 0x00bb048c);
- /* Bypass IPU2 QoS generator */
- writel(0x00000002, 0x00bb050c);
- /* Bandwidth THR for of PRE0 */
- writel(0x00000200, 0x00bb0690);
- /* Bandwidth THR for of PRE1 */
- writel(0x00000200, 0x00bb0710);
- /* Bandwidth THR for of PRE2 */
- writel(0x00000200, 0x00bb0790);
- /* Bandwidth THR for of PRE3 */
- writel(0x00000200, 0x00bb0810);
- /* Saturation THR for of PRE0 */
- writel(0x00000010, 0x00bb0694);
- /* Saturation THR for of PRE1 */
- writel(0x00000010, 0x00bb0714);
- /* Saturation THR for of PRE2 */
- writel(0x00000010, 0x00bb0794);
- /* Saturation THR for of PRE */
- writel(0x00000010, 0x00bb0814);
+}
Sorry, but this is very difficult to read. I guess you want to set the QOS for IPU, but then without accessing to the GPR in the iomux. Anyway, you are accessing directly with offset and value to internal registers. Please add structures to access these registers and/or functions if the offset must be computed
void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -869,7 +893,22 @@ void enable_ipu_clock(void) reg = readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3);
- if (is_mx6dqp()) {
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
I will suggest, as this as other ones are new defines, that you put all of them where they belong (crm_regs.h), surrounding with comments explaining that are defined for the QuadPlus.
Best regards, Stefano Babic
Hi Peng,
On Thu, Jun 11, 2015 at 7:30 AM, Peng Fan Peng.Fan@freescale.com wrote:
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Bypass QoS for IPU and increase bankwidth threshold for PRE to get better performance for video.
Shouldn't this initialization be part of the kernel?
1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800)
CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 26C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 4096 MiB MMC: FSL_SDHC: 0 No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0
Signed-off-by: Robin Gong b38343@freescale.com Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: 1. Remove unused macro in current upstream uboot. 2. setup_fec, remove non 6qp code. Add comments for gpr setting. 3. mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged.
board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++++++++++++++++++++++++++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 29 ++++-- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 175 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 0000000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include <config.h> + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 + +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x12420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x00bb0008 0x00000004 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index b76e4eb..ab7d018 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-int board_eth_init(bd_t *bis) +static void setup_fec(void) { + if (is_mx6dqp()) { + /* + * select ENET MAC0 TX clock from PLL + */ + imx_iomux_set_gpr_register(5, 9, 1, 1); + enable_fec_anatop_clock(ENET_125MHZ); + } + setup_iomux_enet(); +} + +int board_eth_init(bd_t *bis) +{ + setup_fec();
return cpu_eth_init(bis); } @@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) int power_init_board(void) { struct pmic *p; - unsigned int ret; + unsigned int value;
p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM); - if (ret < 0) - return ret; + if (is_mx6dqp()) { + /* set SW2 staby volatage 0.975V*/ + pmic_reg_read(p, PFUZE100_SW2STBY, &value); + value &= ~0x3f; + value |= 0x17; + pmic_reg_write(p, PFUZE100_SW2STBY, value); + }
- return 0; + return pfuze_mode_init(p, APS_PFM); }
#ifdef CONFIG_CMD_BMODE diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig new file mode 100644 index 0000000..0ad23cf --- /dev/null +++ b/configs/mx6qpsabreauto_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP" +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 2260344..6ac64e6 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -12,7 +12,10 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_CONSOLE_DEV "ttymxc3" -#if defined CONFIG_MX6Q + +#if defined CONFIG_MX6QP +#define CONFIG_DEFAULT_FDT_FILE "imx6qp-sabreauto.dtb" +#elif defined CONFIG_MX6Q #define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb" #elif defined CONFIG_MX6DL #define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb"
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
- Add DDR script for mx6qpsabreauto board.
- On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
- On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800)
CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 26C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 4096 MiB MMC: FSL_SDHC: 0 No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0
Signed-off-by: Robin Gong b38343@freescale.com Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2:
- Remove unused macro in current upstream uboot.
- setup_fec, remove non 6qp code. Add comments for gpr setting.
- mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged.
board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++++++++++++++++++++++++++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 29 ++++-- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 175 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 0000000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/*
- Copyright (C) 2015 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- Refer doc/README.imximage for more details about how-to configure
- and create imximage boot image
- The syntax is taken as close as possible with the kwbimage
- */
+/* image version */
+#define __ASSEMBLY__ +#include <config.h>
+IMAGE_VERSION 2
+/*
- Boot Device : one of spi, sd, eimnor, nand, sata:
- spinor: flash_offset: 0x0400
- nand: flash_offset: 0x0400
- sata: flash_offset: 0x0400
- sd/mmc: flash_offset: 0x0400
- eimnor: flash_offset: 0x1000
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x12420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x00bb0008 0x00000004 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF
+/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index b76e4eb..ab7d018 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-int board_eth_init(bd_t *bis) +static void setup_fec(void) {
- if (is_mx6dqp()) {
/** select ENET MAC0 TX clock from PLL*/imx_iomux_set_gpr_register(5, 9, 1, 1);enable_fec_anatop_clock(ENET_125MHZ);- }
To be sure I have not misunderstood the other patches: this is ok and this is what I am expecting. Code checks the SOC and provides a different action for QP or Quad or..
But if some parts are defined at compile time, the check is losing its original meaning and the behavior is already defined at build time.
setup_iomux_enet(); +}
+int board_eth_init(bd_t *bis) +{
setup_fec();
return cpu_eth_init(bis);
} @@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) int power_init_board(void) { struct pmic *p;
- unsigned int ret;
unsigned int value;
p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
return ret;
- if (is_mx6dqp()) {
/* set SW2 staby volatage 0.975V*/pmic_reg_read(p, PFUZE100_SW2STBY, &value);value &= ~0x3f;value |= 0x17;pmic_reg_write(p, PFUZE100_SW2STBY, value);- }
- return 0;
- return pfuze_mode_init(p, APS_PFM);
}
#ifdef CONFIG_CMD_BMODE diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig new file mode 100644 index 0000000..0ad23cf --- /dev/null +++ b/configs/mx6qpsabreauto_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP" +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 2260344..6ac64e6 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -12,7 +12,10 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_CONSOLE_DEV "ttymxc3" -#if defined CONFIG_MX6Q
+#if defined CONFIG_MX6QP +#define CONFIG_DEFAULT_FDT_FILE "imx6qp-sabreauto.dtb" +#elif defined CONFIG_MX6Q #define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb" #elif defined CONFIG_MX6DL #define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb"
The same here
Best regards, Stefano Babic
Hi Stefano,
On Sat, Jun 27, 2015 at 07:08:14PM +0200, Stefano Babic wrote:
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
- Add DDR script for mx6qpsabreauto board.
- On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
- On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800)
CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 26C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 4096 MiB MMC: FSL_SDHC: 0 No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0
Signed-off-by: Robin Gong b38343@freescale.com Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2:
- Remove unused macro in current upstream uboot.
- setup_fec, remove non 6qp code. Add comments for gpr setting.
- mx6qp.cfg is still same with v1. The settings is from IC and passed memory ddr stress test. Since we current have no plan to add SPL, so leave settings unchanged.
board/freescale/mx6qsabreauto/mx6qp.cfg | 143 ++++++++++++++++++++++++++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 29 ++++-- configs/mx6qpsabreauto_defconfig | 5 + include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 175 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg create mode 100644 configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg new file mode 100644 index 0000000..0370636 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg @@ -0,0 +1,143 @@ +/*
- Copyright (C) 2015 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- Refer doc/README.imximage for more details about how-to configure
- and create imximage boot image
- The syntax is taken as close as possible with the kwbimage
- */
+/* image version */
+#define __ASSEMBLY__ +#include <config.h>
+IMAGE_VERSION 2
+/*
- Boot Device : one of spi, sd, eimnor, nand, sata:
- spinor: flash_offset: 0x0400
- nand: flash_offset: 0x0400
- sata: flash_offset: 0x0400
- sd/mmc: flash_offset: 0x0400
- eimnor: flash_offset: 0x1000
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x12420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x00bb0008 0x00000004 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF
+/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index b76e4eb..ab7d018 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-int board_eth_init(bd_t *bis) +static void setup_fec(void) {
- if (is_mx6dqp()) {
/** select ENET MAC0 TX clock from PLL*/imx_iomux_set_gpr_register(5, 9, 1, 1);enable_fec_anatop_clock(ENET_125MHZ);- }
To be sure I have not misunderstood the other patches: this is ok and this is what I am expecting. Code checks the SOC and provides a different action for QP or Quad or..
But if some parts are defined at compile time, the check is losing its original meaning and the behavior is already defined at build time.
is_mx6dqp is runtime checking, it's behavior is not defined at build time. There are some places which has the macro, #ifdef CONFIG_MX6QP, but all in header files, not in xx.c files.
setup_iomux_enet(); +}
+int board_eth_init(bd_t *bis) +{
setup_fec();
return cpu_eth_init(bis);
} @@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) int power_init_board(void) { struct pmic *p;
- unsigned int ret;
unsigned int value;
p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
return ret;
- if (is_mx6dqp()) {
/* set SW2 staby volatage 0.975V*/pmic_reg_read(p, PFUZE100_SW2STBY, &value);value &= ~0x3f;value |= 0x17;pmic_reg_write(p, PFUZE100_SW2STBY, value);- }
- return 0;
- return pfuze_mode_init(p, APS_PFM);
}
#ifdef CONFIG_CMD_BMODE diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig new file mode 100644 index 0000000..0ad23cf --- /dev/null +++ b/configs/mx6qpsabreauto_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6QP" +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 2260344..6ac64e6 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -12,7 +12,10 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONFIG_CONSOLE_DEV "ttymxc3" -#if defined CONFIG_MX6Q
+#if defined CONFIG_MX6QP +#define CONFIG_DEFAULT_FDT_FILE "imx6qp-sabreauto.dtb" +#elif defined CONFIG_MX6Q #define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb" #elif defined CONFIG_MX6DL #define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb"
The same here
Since this is board header files, different SOCs needs different dtbs. The behavior is defined at build time. I think it is not good to add such piece of code in board file: int board_late_init() { if (is_mx6dqp()) setenv(fdt_file, "imx6qp-sabreauto.dtb") /* Just an example */ } So I prefer to use "#if defined CONFIG_MX6QP" in board header file.
Best regards, Stefano Babic
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================
Regards, Peng --
Hi Peng,
On 29/06/2015 04:05, Peng Fan wrote:
To be sure I have not misunderstood the other patches: this is ok and this is what I am expecting. Code checks the SOC and provides a different action for QP or Quad or..
But if some parts are defined at compile time, the check is losing its original meaning and the behavior is already defined at build time.
is_mx6dqp is runtime checking, it's behavior is not defined at build time. There are some places which has the macro, #ifdef CONFIG_MX6QP, but all in header files, not in xx.c files.
Exactly, this is what I mean - here there is a runtime check, but this can be vanified by some #ifdef in header.
The same here
Since this is board header files, different SOCs needs different dtbs. The behavior is defined at build time.
You're wrong. We accepted some code to detect at runtime which is the correct DTB to be selected. In fact, one goal is to have a single kernel as image, using the correct DTB to select the hardware.
This work if we have the same U-Boot is running on different SOC variants. If U-Boot is hardcoded, why do we need to detect the right DTB ? It could be also hard-coded.
I think it is not good to add such piece of code in board file: int board_late_init() { if (is_mx6dqp()) setenv(fdt_file, "imx6qp-sabreauto.dtb") /* Just an example */
It must be checked if fdt_file is already set, because the customer can decide to use its own, but well, yes, this is done by other boards - check in code.
} So I prefer to use "#if defined CONFIG_MX6QP" in board header file.
There is an important goal: having a single U-Boot image running on boards that can have different (pin compatible) SOCs. We get this managing the different layout of the IOMUXC, that was maybe the most difficult part - why do we go back when we can't ?
Best regards, Stefano Babic
Hi Stefano,
On Mon, Jun 29, 2015 at 09:26:10AM +0200, Stefano Babic wrote:
Hi Peng,
On 29/06/2015 04:05, Peng Fan wrote:
To be sure I have not misunderstood the other patches: this is ok and this is what I am expecting. Code checks the SOC and provides a different action for QP or Quad or..
But if some parts are defined at compile time, the check is losing its original meaning and the behavior is already defined at build time.
is_mx6dqp is runtime checking, it's behavior is not defined at build time. There are some places which has the macro, #ifdef CONFIG_MX6QP, but all in header files, not in xx.c files.
Exactly, this is what I mean - here there is a runtime check, but this can be vanified by some #ifdef in header.
The same here
Since this is board header files, different SOCs needs different dtbs. The behavior is defined at build time.
You're wrong. We accepted some code to detect at runtime which is the correct DTB to be selected. In fact, one goal is to have a single kernel as image, using the correct DTB to select the hardware.
This work if we have the same U-Boot is running on different SOC variants. If U-Boot is hardcoded, why do we need to detect the right DTB ? It could be also hard-coded.
I think it is not good to add such piece of code in board file: int board_late_init() { if (is_mx6dqp()) setenv(fdt_file, "imx6qp-sabreauto.dtb") /* Just an example */
It must be checked if fdt_file is already set, because the customer can decide to use its own, but well, yes, this is done by other boards - check in code.
} So I prefer to use "#if defined CONFIG_MX6QP" in board header file.
There is an important goal: having a single U-Boot image running on boards that can have different (pin compatible) SOCs. We get this managing the different layout of the IOMUXC, that was maybe the most difficult part - why do we go back when we can't ?
Get you. I saw the code in gw_ventana.c to detect the DTB at runtime. To imx6q/qp/dl sabreauto board, there is no place to store info such as ventana_board_info. But this is a good point that gw_ventana use the way to do runtime check, which can make one image goal for pin compatible SOCs.
To the i.mx6qp board patch, I can use this way to remove the DTB related #ifdefs, use the way that gw_ventana uses. Will split the current patch into two, one to refacotr the current code to use runtime DTB detect, the second one is to add i.mx6qp support.
Best regards, Stefano Babic
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================
Regards, Peng. --
Hi Peng,
On 29/06/2015 10:06, Peng Fan wrote:
There is an important goal: having a single U-Boot image running on boards that can have different (pin compatible) SOCs. We get this managing the different layout of the IOMUXC, that was maybe the most difficult part - why do we go back when we can't ?
Get you. I saw the code in gw_ventana.c to detect the DTB at runtime. To imx6q/qp/dl sabreauto board, there is no place to store info such as ventana_board_info. But this is a good point that gw_ventana use the way to do runtime check, which can make one image goal for pin compatible SOCs.
Right - and this will be appreciate by sabreauto customers, who should not deal with several U-Boot images. And maybe asking why board is not booting after installing the wrong one.
To the i.mx6qp board patch, I can use this way to remove the DTB related #ifdefs, use the way that gw_ventana uses. Will split the current patch into two, one to refacotr the current code to use runtime DTB detect, the second one is to add i.mx6qp support.
It looks like a nice plan ;-).
Best regards, Stefano Babic
On Mon, Jun 29, 2015 at 5:06 AM, Peng Fan b51431@freescale.com wrote:
Get you. I saw the code in gw_ventana.c to detect the DTB at runtime.
I would suggest using the approach done at mx6cuboxi to detect the DTB at runtime: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=205d58699b157df75f1aa0b363ea...
Regards,
Fabio Estevam
On Mon, Jun 29, 2015 at 09:02:20AM -0300, Fabio Estevam wrote:
On Mon, Jun 29, 2015 at 5:06 AM, Peng Fan b51431@freescale.com wrote:
Get you. I saw the code in gw_ventana.c to detect the DTB at runtime.
I would suggest using the approach done at mx6cuboxi to detect the DTB at runtime: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=205d58699b157df75f1aa0b363ea...
Fabio, Thanks, good suggestion.
Regards,
Fabio Estevam
Regards, Peng. --
Hi Peng,
On Thu, Jun 11, 2015 at 7:30 AM, Peng Fan Peng.Fan@freescale.com wrote:
- Add DDR script for mx6qpsabreauto board.
- On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
- On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800)
CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
Please make it to display i.MX6QP instead.
Regards,
Fabio Estevam
To resolve USB camera bandwidth issue, increase the priority to make peripheral can fetch data from memory in time. Recommended AQoS setting from IC team value for peripheral and only on imx6qp.
The address is: 0xbb0608, the value is: 0x80000201
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com ---
Changes v2: improve comments
arch/arm/cpu/armv7/mx6/soc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bcfa2f6..e3e1494 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -424,6 +424,14 @@ int arch_cpu_init(void)
init_src();
+ /* + * To resolve USB camera bandwidth issue, increase the priority + * to make pheripheral can fetch data from memory in time. Recommended + * AQoS setting from IC team value for peripheral and only on imx6qp. + */ + if (is_mx6dqp()) + writel(0x80000201, 0xbb0608); + return 0; }
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
To resolve USB camera bandwidth issue, increase the priority to make peripheral can fetch data from memory in time. Recommended AQoS setting from IC team value for peripheral and only on imx6qp.
The address is: 0xbb0608, the value is: 0x80000201
Signed-off-by: Ye.Li B37916@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com
Changes v2: improve comments
arch/arm/cpu/armv7/mx6/soc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bcfa2f6..e3e1494 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -424,6 +424,14 @@ int arch_cpu_init(void)
init_src();
- /*
* To resolve USB camera bandwidth issue, increase the priority* to make pheripheral can fetch data from memory in time. Recommended* AQoS setting from IC team value for peripheral and only on imx6qp.*/- if (is_mx6dqp())
writel(0x80000201, 0xbb0608);
See my prevoius comment: no magic data, provide structures and code for that.
Best regards, Stefano Babic
Hi Peng,
On 11/06/2015 12:30, Peng Fan wrote:
is_soc_rev should return a bool value, so use "==", but not "-", change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0). This patch also add space between "&" for cpu_type(rev) macro.
Signed-off-by: Peng Fan Peng.Fan@freescale.com
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
participants (4)
-
Fabio Estevam -
Peng Fan -
Peng Fan -
Stefano Babic