Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add a build rule and binman definition for this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

Makefile | 6 ++++++ arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/dts/coreboot-u-boot.dtsi | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+) create mode 100644 arch/x86/dts/coreboot-u-boot.dtsi

diff --git a/Makefile b/Makefile index b8a4b5058a..a6db812f6d 100644 --- a/Makefile +++ b/Makefile @@ -926,6 +926,9 @@ ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),) ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom endif +ifeq ($(CONFIG_SYS_COREBOOT)$(CONFIG_SPL),yy) +ALL-$(CONFIG_BINMAN) += u-boot-x86-with-spl.bin +endif

# Build a combined spl + u-boot image for sunxi ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy) @@ -1611,6 +1614,9 @@ u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE endif endif

+u-boot-x86-with-spl.bin: spl/u-boot-spl.bin u-boot.bin FORCE + $(call if_changed,binman) + ifneq ($(CONFIG_TEGRA),) ifneq ($(CONFIG_BINMAN),) # Makes u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index c8e6a889d0..497d6284ac 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -25,5 +25,6 @@ config SYS_COREBOOT imply FS_CBFS imply CBMEM_CONSOLE imply X86_TSC_READ_BASE + select BINMAN if X86_64

endif diff --git a/arch/x86/dts/coreboot-u-boot.dtsi b/arch/x86/dts/coreboot-u-boot.dtsi new file mode 100644 index 0000000000..38efc48d83 --- /dev/null +++ b/arch/x86/dts/coreboot-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#include <config.h> + +/ { + binman { + filename = "u-boot-x86-with-spl.bin"; + u-boot-spl { + }; + u-boot { + offset = <0x10000>; + }; + }; +};

At present SPL only works on bare-metal builds. With a few tweaks it can be used for coreboot also.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/lib/spl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 95a89c072d..212b4d596d 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -63,7 +63,7 @@ static int x86_spl_init(void) * is not needed. We could make this a CONFIG option or perhaps * place it immediately below CONFIG_SYS_TEXT_BASE. */ - char *ptr = (char *)0x110000; + __maybe_unused char *ptr = (char *)0x110000; #else struct udevice *punit; #endif @@ -111,7 +111,8 @@ static int x86_spl_init(void) __func__, ret); }

-#ifndef CONFIG_TPL +#ifndef CONFIG_SYS_COREBOOT +# ifndef CONFIG_TPL memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);

/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ @@ -140,7 +141,7 @@ static int x86_spl_init(void) return ret; } mtrr_commit(true); -#else +# else ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit); if (ret) debug("Could not find PUNIT (err=%d)\n", ret); @@ -148,6 +149,7 @@ static int x86_spl_init(void) ret = set_max_freq(); if (ret) debug("Failed to set CPU frequency (err=%d)\n", ret); +# endif #endif

return 0; @@ -162,7 +164,7 @@ void board_init_f(ulong flags) debug("Error %d\n", ret); panic("x86_spl_init fail"); } -#ifdef CONFIG_TPL +#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT) gd->bd = malloc(sizeof(*gd->bd)); if (!gd->bd) { printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));

Make a few adjustments to allow us to build an SPL image for coreboot.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/Makefile | 4 +++- arch/x86/cpu/coreboot/Makefile | 8 +++++++- arch/x86/cpu/coreboot/coreboot.c | 3 ++- arch/x86/cpu/coreboot/coreboot_spl.c | 12 ++++++++++++ arch/x86/cpu/intel_common/Makefile | 2 ++ arch/x86/cpu/x86_64/cpu.c | 2 ++ 6 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 307267a8fb..ee0499f5d7 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o obj-$(CONFIG_QFW) += qfw_cpu.o +ifndef CONFIG_SYS_COREBOOT +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o +endif ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o endif diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 35b15bb1da..605f90304e 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -11,8 +11,14 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se.

+ifndef CONFIG_SPL obj-y += car.o +endif +ifdef CONFIG_SPL_BUILD +obj-y += coreboot_spl.o +else +obj-y += sdram.o +endif obj-y += coreboot.o obj-y += tables.o -obj-y += sdram.o obj-y += timestamp.o diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 0c4c6348d1..624caf67a6 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -27,7 +27,8 @@ int arch_cpu_init(void)

timestamp_init();

- return x86_cpu_init_f(); + return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : + x86_cpu_init_f(); }

int checkcpu(void) diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c new file mode 100644 index 0000000000..36661871e9 --- /dev/null +++ b/arch/x86/cpu/coreboot/coreboot_spl.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + */ + +#include <common.h> +#include <init.h> + +int dram_init(void) +{ + return 0; +} diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 1736bd2b53..374803b876 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o

ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SYS_COREBOOT obj-y += cpu_from_spl.o endif endif +endif diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 90925e46ea..4b64339f25 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -53,6 +53,7 @@ int misc_init_r(void) return 0; }

+#ifndef CONFIG_SYS_COREBOOT int checkcpu(void) { return 0; @@ -62,6 +63,7 @@ int print_cpuinfo(void) { return 0; } +#endif

int x86_cpu_reinit_f(void) {

Add a build for running 64-bit U-Boot from coreboot (which is 32-bit). This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.

Coreboot boots into SPL and then SPL boots into U-Boot.

This allows running 64-bit EFI images on x86. Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

board/coreboot/coreboot/MAINTAINERS | 7 +++++ configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++ doc/board/coreboot/coreboot.rst | 10 ++++++ 3 files changed, 65 insertions(+) create mode 100644 configs/coreboot64_defconfig

diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 188906b080..a05673bb0b 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/coreboot/coreboot/ F: include/configs/chromebook_link.h F: configs/coreboot_defconfig + +COREBOOT64 BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot64_defconfig diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig new file mode 100644 index 0000000000..80353b8eb3 --- /dev/null +++ b/configs/coreboot64_defconfig @@ -0,0 +1,48 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0x1120000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_PRE_CON_BUF_ADDR=0x100000 +CONFIG_X86_RUN_64BIT=y +CONFIG_VENDOR_COREBOOT=y +CONFIG_TARGET_COREBOOT=y +CONFIG_SPL_TEXT_BASE=0x1110000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="coreboot" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_PCI_PNP is not set +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index fd974229eb..9c44c025a4 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot: At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. + +64-bit U-Boot +------------- + +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This +produces an image which can be booted from coreboot (32-bit). Internally it +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It +can be useful for running UEFI applications, for example. + +This has only been lightly tested.