From: Michael Trimarchi michael@amarulasolutions.com

This will improve code readabilty

Signed-off-by: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Shyam Saini shyam.saini@amarulasolutions.com --- Changelogs: V1->V2: none V2->V3: Fix use of clrsetbits_le32 and setbits_le32 functions V3->V4: Rebase to original series's patch 2 and 3 V4->V5: Use correct clear bit function V5->V6: Use one single function same as clrsetbits_le32 and make everything logically correct --- arch/arm/mach-sunxi/dram_sun8i_a33.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 63e18f17d0..36c46096a5 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -145,12 +145,8 @@ static void auto_set_timing_para(struct dram_para *para) reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); writel(reg_val, &mctl_ctl->dramtmg5); /* Set two rank timing and exit self-refresh timing */ - reg_val = readl(&mctl_ctl->dramtmg8); - reg_val &= ~(0xff << 8); - reg_val &= ~(0xff << 0); - reg_val |= (0x33 << 8); - reg_val |= (0x10 << 0); - writel(reg_val, &mctl_ctl->dramtmg8); + clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0), + (0x33 << 8) | (0x10 << 0)); /* Set phy interface time */ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | (wr_latency << 0);