[U-Boot] [PATCH] MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
These boards were meaning to deploy this value:
#define LCRR_DBYP 0x80000000
but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual.
According to the documentation, LCRR_DBYP should be used as:
PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less.
So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows:
Between 66 and 133, the DLL is enabled with an override workaround.
In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index d127137..532d32a 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -275,7 +275,7 @@ local_bus_init(void) lbc->lcrr &= (~0x80000000); /* DLL Enabled */
} else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ udelay(200);
/* diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 48ede98..3361614 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -273,7 +273,7 @@ local_bus_init(void) lbc->lcrr &= (~0x80000000); /* DLL Enabled */
} else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ udelay(200);
/*
On Dec 16, 2011, at 4:31 PM, Paul Gortmaker wrote:
These boards were meaning to deploy this value:
#define LCRR_DBYP 0x80000000
but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual.
According to the documentation, LCRR_DBYP should be used as:
PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less.
So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows:
Between 66 and 133, the DLL is enabled with an override workaround.In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
applied to 85xx
- k
participants (2)
-
Kumar Gala -
Paul Gortmaker