[U-Boot] [PATCH v2] mx6cuboxi: Fix the reset delay for the AR8035 PHY

From: Fabio Estevam fabio.estevam@nxp.com
Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional:
Booting from net ... FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4
This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization.
As per the AR8035 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied."
So do as suggested and keep the reset low for 10ms.
Also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros PHY can be loaded as per Troy Kisky's suggestion.
Signed-off-by: Fabio Estevam fabio.estevam@nxp.com --- Changes since v1: - Fix the issue in a single patch by adding an extra udelay(100) as suggested by Troy.
board/solidrun/mx6cuboxi/mx6cuboxi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index fc37f1e..18b08d1 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -143,8 +143,9 @@ static void setup_iomux_enet(void) SETUP_IOMUX_PADS(enet_pads);
gpio_direction_output(ETH_PHY_RESET, 0); - mdelay(2); + mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); + udelay(100); }
int board_phy_config(struct phy_device *phydev)

On Mon, Jan 04, 2016 at 09:38:08PM -0200, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@nxp.com
Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional:
Booting from net ... FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4
This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization.
As per the AR8035 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied."
So do as suggested and keep the reset low for 10ms.
Also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros PHY can be loaded as per Troy Kisky's suggestion.
Signed-off-by: Fabio Estevam fabio.estevam@nxp.com
Repeated my test from V1, still passes (and takes a while for the initial BOOTP reply):
Tested-by: Tom Rini trini@konsulko.com

On Mon, Jan 4, 2016 at 10:33 PM, Tom Rini trini@konsulko.com wrote:
Repeated my test from V1, still passes (and takes a while for the initial BOOTP reply):
Tested-by: Tom Rini trini@konsulko.com
Thanks for testing it, Tom.
Stefano,
Please apply this one for 2016.01, thanjs.
participants (2)
-
Fabio Estevam
-
Tom Rini