[U-Boot] [PATCH 0/9] TS-7800 port for U-Boot
The TS-7800 is an Orion5x implementation by Technologic Systems.
Albert, Wolfgang -
Thanks for reviewing my patch series and sorry for the delay in updating it.
Changelog: - Fixed all checkpatch errors. - Updated copyright year. - Renamed CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT and introduced new CONFIG_SKIP_LOWLEVEL_INIT that skips only lowlevel_init. - Documented machine type ID workaround in the README. - Removed "ddr" from name of orion5x_ddr_addr_decode_registers. - Allow the environment to override the MAC even if CONFIG_PRESERVE_LOCAL_MAC is set.
Michael Spang (9): arm926ej-s: Invalidate instruction cache in flush_cache mvgbe: Support preserving the existing MAC address orion5x: Increase maximum bank size to 128M orion5x: Fix wrong address in orion5x_sdram_bar ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s Add board support for TS-7800 Add NAND support for TS-7800 Add README for TS-7800
MAKEALL | 1 + Makefile | 2 +- README | 8 +- arch/arm/cpu/arm1136/start.S | 6 +- arch/arm/cpu/arm720t/start.S | 2 +- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/start.S | 6 +- arch/arm/cpu/arm925t/start.S | 2 +- arch/arm/cpu/arm926ejs/at91/Makefile | 2 + arch/arm/cpu/arm926ejs/davinci/Makefile | 2 + arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 + arch/arm/cpu/arm926ejs/orion5x/dram.c | 6 +- arch/arm/cpu/arm926ejs/start.S | 9 +- arch/arm/cpu/arm946es/start.S | 4 +- arch/arm/cpu/arm_intcm/start.S | 4 +- arch/arm/cpu/armv7/start.S | 2 +- arch/arm/cpu/lh7a40x/start.S | 2 +- arch/arm/cpu/s3c44b0/start.S | 2 +- arch/arm/cpu/sa1100/start.S | 2 +- arch/arm/include/asm/arch-orion5x/cpu.h | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 3 +- arch/arm/lib/cache.c | 2 + board/ns9750dev/lowlevel_init.S | 6 +- board/technologic/ts7800/Makefile | 46 ++++++ board/technologic/ts7800/ts7800.c | 36 +++++ boards.cfg | 1 + doc/README.ts7800 | 84 ++++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++ drivers/net/mvgbe.c | 20 +++ include/common.h | 2 +- include/configs/SMN42.h | 2 +- include/configs/a320evb.h | 2 +- include/configs/afeb9260.h | 2 +- include/configs/armadillo.h | 2 +- include/configs/aspenite.h | 2 +- include/configs/at91cap9adk.h | 2 +- include/configs/at91rm9200dk.h | 12 +- include/configs/at91rm9200ek.h | 6 +- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9261ek.h | 2 +- include/configs/at91sam9263ek.h | 4 +- include/configs/at91sam9m10g45ek.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/cmc_pu2.h | 4 +- include/configs/colibri_pxa270.h | 2 +- include/configs/cpuat91.h | 6 +- include/configs/csb637.h | 4 +- include/configs/da830evm.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/davinci_dm355evm.h | 2 +- include/configs/davinci_dm355leopard.h | 2 +- include/configs/davinci_dm365evm.h | 2 +- include/configs/davinci_dm6467evm.h | 2 +- include/configs/davinci_dvevm.h | 6 +- include/configs/davinci_schmoogie.h | 2 +- include/configs/davinci_sffsdr.h | 2 +- include/configs/davinci_sonata.h | 6 +- include/configs/dkb.h | 2 +- include/configs/dnp1110.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/ea20.h | 2 +- include/configs/evb4510.h | 2 +- include/configs/gcplus.h | 4 +- include/configs/guruplug.h | 2 +- include/configs/hawkboard.h | 2 +- include/configs/integratorap.h | 2 +- include/configs/integratorcp.h | 6 +- include/configs/kb9202.h | 2 +- include/configs/km_arm.h | 2 +- include/configs/lpc2292sodimm.h | 2 +- include/configs/meesc.h | 2 +- include/configs/mp2usb.h | 4 +- include/configs/mv88f6281gtw_ge.h | 2 +- include/configs/mx31pdk.h | 2 +- include/configs/nhk8815.h | 2 +- include/configs/openrd_base.h | 2 +- include/configs/otc570.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pm9g45.h | 2 +- include/configs/pxa255_idp.h | 2 +- include/configs/rd6281a.h | 2 +- include/configs/sbc2410x.h | 2 +- include/configs/sbc35_a9g20.h | 2 +- include/configs/shannon.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/tegra2-common.h | 2 +- include/configs/tny_a9260.h | 2 +- include/configs/top9000.h | 2 +- include/configs/ts7800.h | 193 +++++++++++++++++++++++ include/configs/tx25.h | 2 +- include/configs/zipitz2.h | 2 +- 95 files changed, 585 insertions(+), 117 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 doc/README.ts7800 create mode 100644 drivers/mtd/nand/ts7800_nand.c create mode 100644 include/configs/ts7800.h
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); + /* invalidate icache for coherence with cleaned dcache */ + asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); #endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void);
Hi Michael, Curiously, have any idea how to test cache stuff?
2011/3/18 Michael Spang mspang@csclub.uwaterloo.ca:
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
- /* invalidate icache for coherence with cleaned dcache */
- asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void); -- 1.7.2.3
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 3/19/11, arden jay arden.jay@gmail.com wrote:
Hi Michael, Curiously, have any idea how to test cache stuff?
I don't have any good suggestions for testing cache stuff in general, but this one is pretty easy to test if you have the board in question. Because U-Boot is loaded *as if it were linux* by the manufacturer's bootloader, the initial location of U-Boot is the same as where we ultimately load the Linux kernel. Without this patch the symptom is the failure of Linux to start from U-Boot.
Michael
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache. It then should have cache miss, and forces to reload the instruction from memory?
Why it will have problem while U-boot & Kernel at the same memory location?
2011/3/20 Michael Spang mspang@csclub.uwaterloo.ca:
On 3/19/11, arden jay arden.jay@gmail.com wrote:
Hi Michael, Curiously, have any idea how to test cache stuff?
I don't have any good suggestions for testing cache stuff in general, but this one is pretty easy to test if you have the board in question. Because U-Boot is loaded *as if it were linux* by the manufacturer's bootloader, the initial location of U-Boot is the same as where we ultimately load the Linux kernel. Without this patch the symptom is the failure of Linux to start from U-Boot.
Michael
Le 03/20/11 06:36, arden jay a écrit :
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache. It then should have cache miss, and forces to reload the instruction from memory? Why it will have problem while U-boot& Kernel at the same memory location?
The error in your assumption is the "it then should have cache miss". A cache won't have a cache miss if it has already been fetched and not yet been invalidated, and the i-cache won't magically invalidate just because you do data writes at the location where the i-cache was fetched from; you end up with an i-cache that pretends to be valid but no longer matches the main memory content.
Amicalement,
Hi Albert,
I got it, thanks your explaination.
2011/3/20 Albert ARIBAUD albert.aribaud@free.fr:
Le 03/20/11 06:36, arden jay a écrit :
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache. It then should have cache miss, and forces to reload the instruction from memory? Why it will have problem while U-boot& Kernel at the same memory location?
The error in your assumption is the "it then should have cache miss". A cache won't have a cache miss if it has already been fetched and not yet been invalidated, and the i-cache won't magically invalidate just because you do data writes at the location where the i-cache was fetched from; you end up with an i-cache that pretends to be valid but no longer matches the main memory content.
Amicalement,
Albert.
On 3/20/11, arden jay arden.jay@gmail.com wrote:
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache. It then should have cache miss, and forces to reload the instruction from memory?
Why it will have problem while U-boot & Kernel at the same memory location?
If the instruction fetch misses the cache, then it works fine. That's why invalidating solves the problem. The problem is that it hits, but returns the wrong instructions. The code from U-Boot is loaded into the icache when U-Boot is started (before it is relocated) and some of it is still in the icache when we execute linux. So the CPU ends up fetching the wrong instructions.
On ARM if code is stored to RAM, then the modified addresses must be manually invalidated in the instruction cache. The hardware does not do this for us.
Michael
Hi Arden,
On Sunday 20 March 2011 08:00 AM, arden jay wrote:
Hi Michael, Curiously, have any idea how to test cache stuff?
Recently I did some cache testing. Here is the technique I used for data-cache:
To test flush: * Write a known pattern to a region of memory * Flush the region * Invalidate the region * Read back the region and see if you get the original pattern. If the flush was effective you will see the original data.
To test Invalidate: * Write a known pattern to a region of memory * Invalidate the region immediately * Read back the region and see if you get the original pattern. You should *not* be seeing the expected pattern for the entire region if the invalidate was successful.
Similar tests can be done for the I-cache, but maybe a little more tedious.
I agree that these tests may not be 100% fool-proof - for instance what if both invalidate and flush didn't work in the first case. But these should at least catch very obvious errors and can be used in combination with other techniques to make sure that your cache operations are indeed working.
Additionally, there was a JTAG debugger technique that I found quite useful. If your processor supports a technique called DAP(Debug Access Port or Dual Access Port, I am not sure) then a debugger like Lauterbach can view memory in two modes, one the normal or CPU mode and the other DAP mode. In normal mode the memory is dumped as if it is viewed from the CPU, so it goes through the cache and you see the cache contents if the area in question is in cache. In DAP mode the real memory contents are dumped. Comparing these two you can see whether cache and memory are coherent for a given area. It worked quite well with Lauterbach and OMAP4.
br, Aneesh
2011/3/18 Michael Spangmspang@csclub.uwaterloo.ca:
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by: Michael Spangmspang@csclub.uwaterloo.ca
arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
/* invalidate icache for coherence with cleaned dcache */asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));-- 1.7.2.3
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi Michael, Thanks, it is the key point: "The problem is that it hits, but returns the wrong instructions."
Hi Aneesh, Thanks for your sharing, it makes sense to check that way.
2011/3/21 Aneesh V aneesh@ti.com:
Hi Arden,
On Sunday 20 March 2011 08:00 AM, arden jay wrote:
Hi Michael, Curiously, have any idea how to test cache stuff?
Recently I did some cache testing. Here is the technique I used for data-cache:
To test flush:
- Write a known pattern to a region of memory
- Flush the region
- Invalidate the region
- Read back the region and see if you get the original pattern. If the
flush was effective you will see the original data.
To test Invalidate:
- Write a known pattern to a region of memory
- Invalidate the region immediately
- Read back the region and see if you get the original pattern. You
should *not* be seeing the expected pattern for the entire region if the invalidate was successful.
Similar tests can be done for the I-cache, but maybe a little more tedious.
I agree that these tests may not be 100% fool-proof - for instance what if both invalidate and flush didn't work in the first case. But these should at least catch very obvious errors and can be used in combination with other techniques to make sure that your cache operations are indeed working.
Additionally, there was a JTAG debugger technique that I found quite useful. If your processor supports a technique called DAP(Debug Access Port or Dual Access Port, I am not sure) then a debugger like Lauterbach can view memory in two modes, one the normal or CPU mode and the other DAP mode. In normal mode the memory is dumped as if it is viewed from the CPU, so it goes through the cache and you see the cache contents if the area in question is in cache. In DAP mode the real memory contents are dumped. Comparing these two you can see whether cache and memory are coherent for a given area. It worked quite well with Lauterbach and OMAP4.
br, Aneesh
2011/3/18 Michael Spangmspang@csclub.uwaterloo.ca:
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by: Michael Spangmspang@csclub.uwaterloo.ca
arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
- /* invalidate icache for coherence with cleaned dcache */
- asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void); -- 1.7.2.3
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
(although this patch is more than two *years* old, it never got properly answered to. I am doing so here to make sure future readers know why it was not applied and won't be.)
Hi Michael,
On Thu, 17 Mar 2011 15:46:55 -0400, Michael Spang mspang@csclub.uwaterloo.ca wrote:
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
- /* invalidate icache for coherence with cleaned dcache */
- asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void);
This patch has obviously not been applied, and won't be, because of two reasons: i) overwriting part of U-Boot when loading the kernel is a bug which should not be papered over, and ii) if we had to do this anyway, the right place to do it would have been where the issue might occur, that is, in the OS boot sequence, not in the cache handling functions.
Apologies for not properly answering in due time.
Amicalement,
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot.
Michael
On Mon, Jul 29, 2013 at 3:19 AM, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(although this patch is more than two *years* old, it never got properly answered to. I am doing so here to make sure future readers know why it was not applied and won't be.)
Hi Michael,
On Thu, 17 Mar 2011 15:46:55 -0400, Michael Spang mspang@csclub.uwaterloo.ca wrote:
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
/* invalidate icache for coherence with cleaned dcache */asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void);
This patch has obviously not been applied, and won't be, because of two reasons: i) overwriting part of U-Boot when loading the kernel is a bug which should not be papered over, and ii) if we had to do this anyway, the right place to do it would have been where the issue might occur, that is, in the OS boot sequence, not in the cache handling functions.
Apologies for not properly answering in due time.
Amicalement,
Albert.
Hi Michael,
On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang mspang@csclub.uwaterloo.ca wrote:
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot.
Thanks for this pointing out this scenario, which is correct, although it was not raised in the original bug description.
I begs however the question whether anything from re-relocation can survive in the icache from between the moment the relocation starts and the moment the OS is given transfer to. IOW, was this issue actually met?
Anyway I stand by my statement that even if there is an issue to fix, this patch fixes it in the wrong place.
Michael
Amicalement,
On Mon, Jul 29, 2013 at 10:09 AM, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hi Michael,
On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang mspang@csclub.uwaterloo.ca wrote:
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot.
Thanks for this pointing out this scenario, which is correct, although it was not raised in the original bug description.
I begs however the question whether anything from re-relocation can survive in the icache from between the moment the relocation starts and the moment the OS is given transfer to. IOW, was this issue actually met?
Yes, I had boot failures without this patch on the device I was porting to (TS-7800). It happened consistently.
Anyway I stand by my statement that even if there is an issue to fix, this patch fixes it in the wrong place.
Ok, that's fair. I was hoping to repost this series someday and will take that into account.
Michael
The MVGBE driver either gets the MAC from the environment, or invents one. This allows the driver to leave the existing address alone in case it is initialized before U-Boot starts.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- drivers/net/mvgbe.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index c701f43..bab55b3 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -380,6 +380,22 @@ static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) }
/* + * port_uc_addr_get - This function gets the port unicast address. + */ +static void port_uc_addr_get(struct mvgbe_registers *regs, u8 * p_addr) +{ + u32 mac_l = MVGBE_REG_RD(regs->macal); + u32 mac_h = MVGBE_REG_RD(regs->macah); + + p_addr[0] = (mac_h >> 24); + p_addr[1] = (mac_h >> 16); + p_addr[2] = (mac_h >> 8); + p_addr[3] = (mac_h >> 0); + p_addr[4] = (mac_l >> 8); + p_addr[5] = (mac_l >> 0); +} + +/* * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. */ static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) @@ -719,6 +735,9 @@ error1: }
while (!eth_getenv_enetaddr(s, dev->enetaddr)) { +#if defined(CONFIG_PRESERVE_LOCAL_MAC) + port_uc_addr_get(dmvgbe->regs, dmvgbe->dev.enetaddr); +#else /* Generate Private MAC addr if not set */ dev->enetaddr[0] = 0x02; dev->enetaddr[1] = 0x50; @@ -734,6 +753,7 @@ error1: dev->enetaddr[4] = get_random_hex(); dev->enetaddr[5] = get_random_hex(); #endif +#endif eth_setenv_enetaddr(s, dev->enetaddr); }
Dear Michael Spang,
In message 1300391223-11879-3-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The MVGBE driver either gets the MAC from the environment, or invents one. This allows the driver to leave the existing address alone in case it is initialized before U-Boot starts.
Who or what would be doing that?
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {+#if defined(CONFIG_PRESERVE_LOCAL_MAC)
port_uc_addr_get(dmvgbe->regs, dmvgbe->dev.enetaddr);+#else
For consistency, should this not be
port_uc_addr_get(dmvgbe->regs, dev->enetaddr);
?
/* Generate Private MAC addr if not set */ dev->enetaddr[0] = 0x02; dev->enetaddr[1] = 0x50;@@ -734,6 +753,7 @@ error1: dev->enetaddr[4] = get_random_hex(); dev->enetaddr[5] = get_random_hex(); #endif +#endif eth_setenv_enetaddr(s, dev->enetaddr); }
And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to the README.
Best regards,
Wolfgang Denk
On Sun, Apr 24, 2011 at 6:50 PM, Wolfgang Denk wd@denx.de wrote:
And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to the README.
We have something similar already on Freescale parts, but it does sometimes cause problems. If the environment ethaddr is already set, it is left alone. Otherwise, the MAC address is read from EEPROM.
So we could use CONFIG_PRESERVE_LOCAL_MAC to alter this behavior (i.e. always use the EEPROM). However, the current default is already CONFIG_PRESERVE_LOCAL_MAC, so can we change this to something like CONFIG_OVERRIDE_LOCAL_MAC?
On Mon, Apr 25, 2011 at 7:37 AM, Tabi Timur-B04825 B04825@freescale.com wrote:
On Sun, Apr 24, 2011 at 6:50 PM, Wolfgang Denk wd@denx.de wrote:
And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to the README.
We have something similar already on Freescale parts, but it does sometimes cause problems. If the environment ethaddr is already set, it is left alone. Otherwise, the MAC address is read from EEPROM.
So we could use CONFIG_PRESERVE_LOCAL_MAC to alter this behavior (i.e. always use the EEPROM). However, the current default is already CONFIG_PRESERVE_LOCAL_MAC, so can we change this to something like CONFIG_OVERRIDE_LOCAL_MAC?
I don't think the option you want is the same. If there's a MAC in the environment, I want to use it. Otherwise, I want U-Boot to leave the MAC alone because the manufacturer assigned MAC was written to the interface's registers before U-Boot started.
Michael
On Tuesday, April 26, 2011 00:23:47 Michael Spang wrote:
On Mon, Apr 25, 2011 at 7:37 AM, Tabi Timur-B04825 wrote:
On Sun, Apr 24, 2011 at 6:50 PM, Wolfgang Denk wrote:
And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to the README.
We have something similar already on Freescale parts, but it does sometimes cause problems. If the environment ethaddr is already set, it is left alone. Otherwise, the MAC address is read from EEPROM.
So we could use CONFIG_PRESERVE_LOCAL_MAC to alter this behavior (i.e. always use the EEPROM). However, the current default is already CONFIG_PRESERVE_LOCAL_MAC, so can we change this to something like CONFIG_OVERRIDE_LOCAL_MAC?
I don't think the option you want is the same. If there's a MAC in the environment, I want to use it. Otherwise, I want U-Boot to leave the MAC alone because the manufacturer assigned MAC was written to the interface's registers before U-Boot started.
so implement this in your board file in misc_init_r or board_eth_init. have the code do something like: uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { /* ... read current MAC out of the driver's registers ... */ eth_setenv_enetaddr("ethaddr", enetaddr); }
then you dont need ugly config hacks in random drivers -mike
Mike Frysinger wrote:
so implement this in your board file in misc_init_r or board_eth_init. have the code do something like: uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { /* ... read current MAC out of the driver's registers ... */ eth_setenv_enetaddr("ethaddr", enetaddr); }
then you dont need ugly config hacks in random drivers
This is a feature that could be applied to the e1000 drivers. The current situation is a mess. Some drivers ignore the environment, some of them always use it. This should probably be standardized.
On Sat, Apr 30, 2011 at 10:34, Tabi Timur-B04825 wrote:
Mike Frysinger wrote:
so implement this in your board file in misc_init_r or board_eth_init. have the code do something like: uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { /* ... read current MAC out of the driver's registers ... */ eth_setenv_enetaddr("ethaddr", enetaddr); }
then you dont need ugly config hacks in random drivers
This is a feature that could be applied to the e1000 drivers. The current situation is a mess. Some drivers ignore the environment, some of them always use it. This should probably be standardized.
it is standardized already. no driver should be touching the environment. it should only ever use its own eth_device->enetaddr. the common eth code already takes care of syncing the env and that member.
also, please fix your e-mailer to properly wrap long lines. -mike
On Sun, Apr 24, 2011 at 7:50 PM, Wolfgang Denk wd@denx.de wrote:
Dear Michael Spang,
In message 1300391223-11879-3-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The MVGBE driver either gets the MAC from the environment, or invents one. This allows the driver to leave the existing address alone in case it is initialized before U-Boot starts.
Who or what would be doing that?
The manufacturer's bootloader runs first, and cannot easily be replaced. So U-Boot is loaded second, after the MAC is already set.
while (!eth_getenv_enetaddr(s, dev->enetaddr)) { +#if defined(CONFIG_PRESERVE_LOCAL_MAC)
- port_uc_addr_get(dmvgbe->regs, dmvgbe->dev.enetaddr);
+#else
For consistency, should this not be
port_uc_addr_get(dmvgbe->regs, dev->enetaddr);
?
Yes.
/* Generate Private MAC addr if not set */ dev->enetaddr[0] = 0x02; dev->enetaddr[1] = 0x50; @@ -734,6 +753,7 @@ error1: dev->enetaddr[4] = get_random_hex(); dev->enetaddr[5] = get_random_hex(); #endif +#endif eth_setenv_enetaddr(s, dev->enetaddr); }
And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to the README.
Ok I'll add:
CONFIG_PRESERVE_LOCAL_MAC
If no MAC address is set in the environment, then preserve the ethernet interface's current MAC address. Used if the MAC is configured before U-Boot is loaded.
Thanks, Michael
On Thursday, March 17, 2011 15:46:56 Michael Spang wrote:
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
this logic in the mvgbe is plain broken. it should not be touching the env at all. if there is no eeprom to read, then the mvgbe driver should leave dev-
enetaddr alone. let the boards take care of setting things up.
i.e. this patch: diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index c701f43..4c0d5bf 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -645,7 +645,6 @@ int mvgbe_initialize(bd_t *bis) struct mvgbe_device *dmvgbe; struct eth_device *dev; int devnum; - char *s; u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { @@ -700,16 +699,13 @@ error1: /* must be less than NAMESIZE (16) */ sprintf(dev->name, "egiga%d", devnum);
- /* Extract the MAC address from the environment */ switch (devnum) { case 0: dmvgbe->regs = (void *)MVGBE0_BASE; - s = "ethaddr"; break; #if defined(MVGBE1_BASE) case 1: dmvgbe->regs = (void *)MVGBE1_BASE; - s = "eth1addr"; break; #endif default: /* this should never happen */ @@ -718,30 +714,11 @@ error1: return -1; }
- while (!eth_getenv_enetaddr(s, dev->enetaddr)) { - /* Generate Private MAC addr if not set */ - dev->enetaddr[0] = 0x02; - dev->enetaddr[1] = 0x50; - dev->enetaddr[2] = 0x43; -#if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION) - /* Generate fixed lower MAC half using devnum */ - dev->enetaddr[3] = 0; - dev->enetaddr[4] = 0; - dev->enetaddr[5] = devnum; -#else - /* Generate random lower MAC half */ - dev->enetaddr[3] = get_random_hex(); - dev->enetaddr[4] = get_random_hex(); - dev->enetaddr[5] = get_random_hex(); -#endif - eth_setenv_enetaddr(s, dev->enetaddr); - } - - dev->init = (void *)mvgbe_init; - dev->halt = (void *)mvgbe_halt; - dev->send = (void *)mvgbe_send; - dev->recv = (void *)mvgbe_recv; - dev->write_hwaddr = (void *)mvgbe_write_hwaddr; + dev->init = mvgbe_init; + dev->halt = mvgbe_halt; + dev->send = mvgbe_send; + dev->recv = mvgbe_recv; + dev->write_hwaddr = mvgbe_write_hwaddr;
eth_register(dev);
-mike
The TS-7800 has one 128M RAM bank, so the maximum must be increased.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- arch/arm/include/asm/arch-orion5x/orion5x.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index e3d3f76..96c2c57 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -63,7 +63,7 @@ #define MAX_MVGBE_DEVS 1 #define MVGBE0_BASE ORION5X_EGIGA_BASE
-#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) +#define CONFIG_MAX_RAM_BANK_SIZE (128*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when adding support for them, and this comment should then be updated. */
This code intends to read the SDRAM controller base address registers but is instead reading the CPU window base address registers. Also, remove "ddr" from the name of struct orion5x_addr_decode_registers, since it also applies to other decode registers.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- arch/arm/cpu/arm926ejs/orion5x/dram.c | 6 +++--- arch/arm/include/asm/arch-orion5x/cpu.h | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 1 + 3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index b749282..b95d537 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -36,9 +36,9 @@ DECLARE_GLOBAL_DATA_PTR; */ u32 orion5x_sdram_bar(enum memory_bank bank) { - struct orion5x_ddr_addr_decode_registers *winregs = - (struct orion5x_ddr_addr_decode_registers *) - ORION5X_CPU_WIN_BASE; + struct orion5x_addr_decode_registers *winregs = + (struct orion5x_addr_decode_registers *) + ORION5X_SDRAM_CTRL_BASE;
u32 result = 0; u32 enable = 0x01 & winregs[bank].size; diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index c84efaf..d43abbf 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -243,7 +243,7 @@ struct orion5x_cpu_registers { * DDR SDRAM Controller Address Decode Registers * Source: 88F5182 User Manual, Appendix A, section A.5.1 */ -struct orion5x_ddr_addr_decode_registers { +struct orion5x_addr_decode_registers { u32 base; u32 size; }; diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index 96c2c57..95bb952 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -42,6 +42,7 @@ #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
/* Documented registers */ +#define ORION5X_SDRAM_CTRL_BASE (ORION5X_REGISTER(0x01500)) #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
For ARM, the CONFIG_SKIP_LOWLEVEL_INIT option implies that the cpu_init_crit and lowlevel_init assembly functions are skipped. We may want to skip only lowlevel_init, so rename the option that skips both to CONFIG_SKIP_CPU_INIT_CRIT. The MIPS option of the same name is not renamed.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- Makefile | 2 +- README | 8 +++++++- arch/arm/cpu/arm1136/start.S | 6 +++--- arch/arm/cpu/arm720t/start.S | 2 +- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 4 ++-- arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S | 4 ++-- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 4 ++-- arch/arm/cpu/arm920t/start.S | 6 +++--- arch/arm/cpu/arm925t/start.S | 2 +- arch/arm/cpu/arm926ejs/at91/Makefile | 2 +- arch/arm/cpu/arm926ejs/davinci/Makefile | 2 +- arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 +- arch/arm/cpu/arm926ejs/start.S | 6 +++--- arch/arm/cpu/arm946es/start.S | 4 ++-- arch/arm/cpu/arm_intcm/start.S | 4 ++-- arch/arm/cpu/armv7/start.S | 2 +- arch/arm/cpu/lh7a40x/start.S | 2 +- arch/arm/cpu/s3c44b0/start.S | 2 +- arch/arm/cpu/sa1100/start.S | 2 +- board/ns9750dev/lowlevel_init.S | 6 +++--- include/common.h | 2 +- include/configs/SMN42.h | 2 +- include/configs/a320evb.h | 2 +- include/configs/afeb9260.h | 2 +- include/configs/armadillo.h | 2 +- include/configs/aspenite.h | 2 +- include/configs/at91cap9adk.h | 2 +- include/configs/at91rm9200dk.h | 12 ++++++------ include/configs/at91rm9200ek.h | 6 +++--- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9261ek.h | 2 +- include/configs/at91sam9263ek.h | 4 ++-- include/configs/at91sam9m10g45ek.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/cmc_pu2.h | 4 ++-- include/configs/colibri_pxa270.h | 2 +- include/configs/cpuat91.h | 6 +++--- include/configs/csb637.h | 4 ++-- include/configs/da830evm.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/davinci_dm355evm.h | 2 +- include/configs/davinci_dm355leopard.h | 2 +- include/configs/davinci_dm365evm.h | 2 +- include/configs/davinci_dm6467evm.h | 2 +- include/configs/davinci_dvevm.h | 6 +++--- include/configs/davinci_schmoogie.h | 2 +- include/configs/davinci_sffsdr.h | 2 +- include/configs/davinci_sonata.h | 6 +++--- include/configs/dkb.h | 2 +- include/configs/dnp1110.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/ea20.h | 2 +- include/configs/evb4510.h | 2 +- include/configs/gcplus.h | 4 ++-- include/configs/guruplug.h | 2 +- include/configs/hawkboard.h | 2 +- include/configs/integratorap.h | 2 +- include/configs/integratorcp.h | 6 +++--- include/configs/kb9202.h | 2 +- include/configs/km_arm.h | 2 +- include/configs/lpc2292sodimm.h | 2 +- include/configs/meesc.h | 2 +- include/configs/mp2usb.h | 4 ++-- include/configs/mv88f6281gtw_ge.h | 2 +- include/configs/mx31pdk.h | 2 +- include/configs/nhk8815.h | 2 +- include/configs/openrd_base.h | 2 +- include/configs/otc570.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pm9g45.h | 2 +- include/configs/pxa255_idp.h | 2 +- include/configs/rd6281a.h | 2 +- include/configs/sbc2410x.h | 2 +- include/configs/sbc35_a9g20.h | 2 +- include/configs/shannon.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/tegra2-common.h | 2 +- include/configs/tny_a9260.h | 2 +- include/configs/top9000.h | 2 +- include/configs/tx25.h | 2 +- include/configs/zipitz2.h | 2 +- 82 files changed, 121 insertions(+), 115 deletions(-)
diff --git a/Makefile b/Makefile index dc2e3d8..d805750 100644 --- a/Makefile +++ b/Makefile @@ -1071,7 +1071,7 @@ mx31pdk_nand_config : unconfig @if [ -n "$(findstring _nand_,$@)" ]; then \ echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \ else \ - echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \ + echo "#define CONFIG_SKIP_CPU_INIT_CRIT" >> $(obj)include/config.h; \ fi @$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31
diff --git a/README b/README index 21cd71b..f9b0c91 100644 --- a/README +++ b/README @@ -2892,7 +2892,7 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEM).
- CONFIG_SKIP_LOWLEVEL_INIT - [ARM only] If this variable is defined, then certain + If this variable is defined, then certain low level initializations (like setting up the memory controller) are omitted and/or U-Boot does not relocate itself into RAM. @@ -2902,6 +2902,12 @@ Low Level (hardware related) configuration options: other boot loader or by a debugger which performs these initializations itself.
+- CONFIG_SKIP_CPU_INIT_CRIT + [ARM only] If this variable is defined, then the CPU + is assumed to be initialized when U-Boot starts. For + most CPUs this also implies low level initialization + is skipped (see CONFIG_SKIP_LOWLEVEL_INIT). + - CONFIG_PRELOADER Modifies the behaviour of start.S when compiling a loader that is executed before the actual U-Boot. E.g. when diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 3c5f3ef..5563f14 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -157,7 +157,7 @@ next: bl cpy_clk_code /* put dpll adjust code behind vectors */ #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -300,7 +300,7 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches @@ -327,7 +327,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
#ifndef CONFIG_PRELOADER /* diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index e774c3f..36e2b40 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -131,7 +131,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S index eaea9d2..4ea2649 100644 --- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/at91/lowlevel_init.S @@ -27,7 +27,7 @@
#include <config.h>
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT
#include <asm/arch/hardware.h> #include <asm/arch/at91_mc.h> @@ -161,4 +161,4 @@ SMRDATA1: .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S index 2e7160f..a7b8c32 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -30,7 +30,7 @@ #include <config.h> #include <version.h>
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT /* * some parameters for the board * @@ -166,4 +166,4 @@ SMRDATA1: .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S index e9f1227..f736ca5 100644 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S @@ -26,7 +26,7 @@ #include <version.h> #include <asm/arch/platform.h>
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT
/* ************************************************************************* @@ -202,4 +202,4 @@ nobutton: add ip, ip, #0x02000000 /* this is a hack */ mov pc, lr /* all done, return */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index a7476b0..d945ff5 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -178,7 +178,7 @@ copyex: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -324,7 +324,7 @@ _dynsym_start_ofs: */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches @@ -354,7 +354,7 @@ cpu_init_crit:
mov lr, ip mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
/* ************************************************************************* diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 39f2e99..ad2def2 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -172,7 +172,7 @@ poll1: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index be9f6dd..7fb1a0a 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -41,7 +41,7 @@ COBJS-y += cpu.o COBJS-y += reset.o COBJS-y += timer.o
-ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_CPU_INIT_CRIT SOBJS-y := lowlevel_init.o endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 3183e6a..3442f6e 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -36,7 +36,7 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o
SOBJS = reset.o
-ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_CPU_INIT_CRIT SOBJS += lowlevel_init.o endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile index e5a9994..780fe18 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Makefile +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -33,7 +33,7 @@ COBJS-y = cpu.o COBJS-y += dram.o COBJS-y += timer.o
-ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_CPU_INIT_CRIT SOBJS := lowlevel_init.o endif
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index fefcfa2..c0a2532 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -171,7 +171,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -315,7 +315,7 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches @@ -341,7 +341,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
#ifndef CONFIG_PRELOADER /* diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 00914f4..9ab4122 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -143,7 +143,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -284,7 +284,7 @@ _dynsym_start_ofs: */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 2fd3b9a..36073b2 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -139,7 +139,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -284,7 +284,7 @@ _dynsym_start_ofs: ************************************************************************* */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* arm_int_generic assumes the ARM boot monitor, or user software, * has initialized the platform diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index d83d501..342f08e 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -139,7 +139,7 @@ next: #endif /* NAND Boot */ #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 81242b1..63bee1a 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -152,7 +152,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 10f5284..2ec1ae8 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -118,7 +118,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit /* * before relocating, we have to setup RAM timing diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index b27e970..be103d1 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -128,7 +128,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S index ba5ff81..407e413 100644 --- a/board/ns9750dev/lowlevel_init.S +++ b/board/ns9750dev/lowlevel_init.S @@ -34,7 +34,7 @@ #include <version.h>
#if defined(CONFIG_NS9750DEV) -# ifndef CONFIG_SKIP_LOWLEVEL_INIT +# ifndef CONFIG_SKIP_CPU_INIT_CRIT # include <./ns9750_sys.h> # include <./ns9750_mem.h> # endif @@ -74,7 +74,7 @@ _PHYS_FLASH: _CAS_LATENCY: .word 0x00022000 @ for CAS2 latency
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT .globl lowlevel_init lowlevel_init:
@@ -295,4 +295,4 @@ _AHB_MONITOR_START: NS9750_SYS_AHB_MON_BATC_GEN_IRQ) _AHB_MONITOR_END:
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ diff --git a/include/common.h b/include/common.h index d8c912d..4d1f783 100644 --- a/include/common.h +++ b/include/common.h @@ -737,7 +737,7 @@ int cpu_release(int nr, int argc, char * const argv[]);
#ifdef CONFIG_INIT_CRITICAL #error CONFIG_INIT_CRITICAL is deprecated! -#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. +#error Read section CONFIG_SKIP_CPU_INIT_CRIT in README. #endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index 4a8acab..30cfef3 100644 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -30,7 +30,7 @@ * If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * High Level Configuration Options diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index 27f137f..a0bfdb4 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -29,7 +29,7 @@ */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/*----------------------------------------------------------------------- * Timer diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 36a2a46..e2151b9 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -41,7 +41,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index d0d0998..a20928e 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -34,7 +34,7 @@ * If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * High Level Configuration Options diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h index fd35f3e..9c1f484 100644 --- a/include/configs/aspenite.h +++ b/include/configs/aspenite.h @@ -38,7 +38,7 @@ #define CONFIG_ARMADA100 1 /* SOC Family Name */ #define CONFIG_ARMADA168 1 /* SOC Used on this Board */ #define CONFIG_MACH_ASPENITE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * There is no internal RAM in ARMADA100, using DRAM diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 49c923f..19867ad 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -43,7 +43,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 15de310..163019e 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -44,7 +44,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 @@ -69,7 +69,7 @@ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Size of malloc() pool */ @@ -160,19 +160,19 @@ #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ #else #define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ #else #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ #define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ #endif /* CONFIG_ENV_IS_IN_DATAFLASH */
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ #define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) #define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ @@ -180,7 +180,7 @@ #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 810023a..48ed135 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -40,7 +40,7 @@ * initialisation was done by some preloader */ #ifdef CONFIG_RAMBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0x20100000 #else #define CONFIG_SYS_TEXT_BASE 0x10000000 @@ -87,7 +87,7 @@ /* * LowLevel Init */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 @@ -113,7 +113,7 @@ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
/* * Hardware drivers diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 5e7dee5..fdf758f 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -48,7 +48,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 401478b..99ff86e 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -46,7 +46,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f6cb406..ff3914f 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -42,7 +42,7 @@ #define CONFIG_INITRD_TAG 1
#ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #endif
/* @@ -144,7 +144,7 @@ "cp.b ${load_addr} ${monitor_base} ${filesize};" \ "protect on ${monitor_base} +${filesize}\0"
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define MASTER_PLL_MUL 171 #define MASTER_PLL_DIV 14 #define MASTER_PLL_OUT 3 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index de74dcf..7082cff 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -46,7 +46,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 8dbd082..725843b 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -43,7 +43,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index a197635..a5d5487 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -43,7 +43,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 @@ -68,7 +68,7 @@ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
/* * Size of malloc() pool diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 23bfbeb..1bea34b 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -30,7 +30,7 @@
#undef BOARD_LATE_INIT #undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * Environment settings diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index f31081d..cfc66e9 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -27,7 +27,7 @@ #define _CONFIG_CPUAT91_H
#ifdef CONFIG_CPUAT91_RAM -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_CPU_INIT_CRIT 1 #else #define CONFIG_BOOTDELAY 1 #endif @@ -48,7 +48,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ #define CONFIG_SYS_MC_PUIA_VAL 0x00000000 @@ -78,7 +78,7 @@ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
/* define one of these to choose the DBGU, USART0 or USART1 as console */ #define CONFIG_AT91RM9200_USART 1 diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 7a85d65..057d1d8 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -44,7 +44,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 @@ -69,7 +69,7 @@ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Size of malloc() pool */ diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index bcf8ee0..b23a534 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -40,7 +40,7 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0xc1080000
/* diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index bbb5a9b..65b6e28 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -40,7 +40,7 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0xc1080000
/* diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index 56d0ac9..a00385d 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -23,7 +23,7 @@ /* Spectrum Digital TMS320DM355 EVM board */ #define DAVINCI_DM355EVM
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index b44b2ea..e00723f 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -22,7 +22,7 @@
#define DAVINCI_DM355LEOPARD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 2825050..c810c9e 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -23,7 +23,7 @@ /* Spectrum Digital TMS320DM365 EVM board */ #define DAVINCI_DM365EVM
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index a0a30f5..ab3f883 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 45214fa..7e75320 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -133,7 +133,7 @@ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_HW_ECC @@ -141,9 +141,9 @@ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #else -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT #endif #define CONFIG_ENV_IS_IN_FLASH #undef CONFIG_SYS_NO_FLASH diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 5cc8bc0..7fc4453 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -87,7 +87,7 @@ #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 307b9f2..e82cddf 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -82,7 +82,7 @@ #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 2336129..2195d88 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -121,16 +121,16 @@ #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #else -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT #endif #define CONFIG_ENV_IS_IN_FLASH #undef CONFIG_SYS_NO_FLASH diff --git a/include/configs/dkb.h b/include/configs/dkb.h index 638af5e..82b81be 100644 --- a/include/configs/dkb.h +++ b/include/configs/dkb.h @@ -36,7 +36,7 @@ #define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ #define CONFIG_PANTHEON 1 /* SOC Family Name */ #define CONFIG_MACH_TTC_DKB 1 /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) #define CONFIG_NR_DRAM_BANKS_MAX 2 diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index 69c6420..a657d4a 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -31,7 +31,7 @@ * If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_CPU_INIT_CRIT 1
/* * High Level Configuration Options diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 249f93b..54b00d2 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -40,7 +40,7 @@ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_DOCKSTAR /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * Commands configuration diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 48ce945..d9cdf55 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0xc1080000
/* diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index fb05727..9d0f27e 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -32,7 +32,7 @@ * * Also swap the flash1 and flash2 addresses during debug. * - * #define CONFIG_SKIP_LOWLEVEL_INIT + * #define CONFIG_SKIP_CPU_INIT_CRIT */
/* diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index fd39ab4..66be194 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -36,9 +36,9 @@ * e.g. bootp/tftp download of the kernel is a far more convenient * when testing new kernels on this target. However the ADS GCPlus Linux * boot ROM leaves the MMU enabled when it passes control to U-Boot. So - * we use lowlevel_init (!CONFIG_SKIP_LOWLEVEL_INIT) to remedy that problem. + * we use lowlevel_init (!CONFIG_SKIP_CPU_INIT_CRIT) to remedy that problem. */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * High Level Configuration Options diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index f449da9..4c81907 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -37,7 +37,7 @@ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_GURUPLUG /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * Commands configuration diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 23a88d0..12c6e4d 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -39,7 +39,7 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_BOARD_EARLY_INIT_F
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_UART_U_BOOT) diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 32ff193..d06ef7c 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -44,7 +44,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_CM_INIT 1 #define CONFIG_CM_REMAP 1 #undef CONFIG_CM_SPD_DETECT diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 2c8ca2d..10c48e1 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -206,12 +206,12 @@ SIB at Block62 End Block62 address 0x24f80000 /* * The ARM boot monitor initializes the board. * However, the default U-Boot code also performs the initialization. - * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT + * If desired, this can be prevented by defining SKIP_CPU_INIT_CRIT * - see documentation supplied with board for details of how to choose the * image to run at reset/power up * e.g. whether the ARM Boot Monitor runs before U-Boot
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
*/
@@ -235,7 +235,7 @@ SIB at Block62 End Block62 address 0x24f80000 #include "armcoremodule.h"
/* - * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & + * If CONFIG_SKIP_CPU_INIT_CRIT is not defined & * the core module has a CM_INIT register * then the U-Boot initialisation code will * e.g. ARM Boot Monitor or pre-loader is repeated once diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index cfb7cea..5cd71f7 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -52,7 +52,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
#define CONFIG_SYS_LONGHELP
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index bf77cc0..5606a1e 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -46,7 +46,7 @@ #undef CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 17972d7..1fa890c 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -30,7 +30,7 @@ * If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * High Level Configuration Options diff --git a/include/configs/meesc.h b/include/configs/meesc.h index a27b36b..742eb04 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -47,7 +47,7 @@ #define CONFIG_REVISION_TAG 1 #undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_MISC_INIT_R /* Call misc_init_r */
#define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 8e398d7..f411278 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -48,7 +48,7 @@ #define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_ATMEL_PLL_INIT_BUG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 @@ -73,7 +73,7 @@ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
/* * Size of malloc() pool diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h index d323829..07a4f78 100644 --- a/include/configs/mv88f6281gtw_ge.h +++ b/include/configs/mv88f6281gtw_ge.h @@ -37,7 +37,7 @@ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * Commands configuration diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 86c758f..f58f79e 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -46,7 +46,7 @@ #define CONFIG_INITRD_TAG 1
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #endif
/* diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 49a16ab..34eb189 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -33,7 +33,7 @@ #define CONFIG_NOMADIK_8815 /* cpu variant */ #define CONFIG_NOMADIK_NHK8815 /* board variant */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* we have already been loaded to RAM */
/* commands */ #include <config_cmd_default.h> diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index cfdd09c..aa9d742 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -42,7 +42,7 @@ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_OPENRD_BASE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * Commands configuration diff --git a/include/configs/otc570.h b/include/configs/otc570.h index ca3bf26..157d5e7 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -47,7 +47,7 @@ #define CONFIG_REVISION_TAG 1 #undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 26e5049..bcadb84 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -153,7 +153,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 96e12f2..7b48316 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -162,7 +162,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_USER_LOWLEVEL_INIT 1
/* diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index ec51ccf..52d4914 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -48,7 +48,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index c1c7f80..d5183a5 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -41,7 +41,7 @@ * If we are developing, we might want to start U-Boot from RAM * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ +#undef CONFIG_SKIP_CPU_INIT_CRIT /* define for developing */ #define CONFIG_SYS_TEXT_BASE 0x0
/* diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h index 60f9579..b4a6b03 100644 --- a/include/configs/rd6281a.h +++ b/include/configs/rd6281a.h @@ -37,7 +37,7 @@ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_RD6281A /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * Commands configuration diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index f0f19b2..110f4ac 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -37,7 +37,7 @@ * If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ +#undef CONFIG_SKIP_CPU_INIT_CRIT /* undef for developing */
/* * High Level Configuration Options diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index 00f4dc9..85c9551 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -53,7 +53,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/shannon.h b/include/configs/shannon.h index c0e6643..4a937df 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -33,7 +33,7 @@ * But U-Boot still relocates itself into RAM */ #define CONFIG_INFERNO /* we are using the inferno bootldr */ -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_CPU_INIT_CRIT 1
/* * High Level Configuration Options diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 83dd8ff..19ff9bd 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -37,7 +37,7 @@ #define CONFIG_KIRKWOOD 1 /* SOC Family Name */ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */
/* * Commands configuration diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 4f4374a..203330d 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -42,7 +42,7 @@ #define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 7b18022..c7abe0b 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -62,7 +62,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
-#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT
/* * Hardware drivers diff --git a/include/configs/top9000.h b/include/configs/top9000.h index 5f0160d..4ed30f3 100644 --- a/include/configs/top9000.h +++ b/include/configs/top9000.h @@ -77,7 +77,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO #define CONFIG_AT91RESET_EXTRST /* assert external reset */ diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 8f8a1a3..fa3cd22 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -51,7 +51,7 @@ #define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #else -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #endif
#define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index ade40b5..af9d74a 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -31,7 +31,7 @@
#undef BOARD_LATE_INIT #undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT
/* * Environment settings
Dear Michael Spang,
In message 1300391223-11879-6-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
For ARM, the CONFIG_SKIP_LOWLEVEL_INIT option implies that the cpu_init_crit and lowlevel_init assembly functions are skipped. We may want to skip only lowlevel_init, so rename the option that skips both to CONFIG_SKIP_CPU_INIT_CRIT. The MIPS option of the same name is not renamed.
This is an inconsistency between architectures which I dislike.
Also, what in case we should want to skip only cpu_init_crit and not lowlevel_init? If we need to handle these separately, then we need 2 CONFIG options.
Best regards,
Wolfgang Denk
On Sun, Apr 24, 2011 at 7:53 PM, Wolfgang Denk wd@denx.de wrote:
Dear Michael Spang,
In message 1300391223-11879-6-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
For ARM, the CONFIG_SKIP_LOWLEVEL_INIT option implies that the cpu_init_crit and lowlevel_init assembly functions are skipped. We may want to skip only lowlevel_init, so rename the option that skips both to CONFIG_SKIP_CPU_INIT_CRIT. The MIPS option of the same name is not renamed.
This is an inconsistency between architectures which I dislike.
Also, what in case we should want to skip only cpu_init_crit and not lowlevel_init? If we need to handle these separately, then we need 2 CONFIG options.
The CPU initialization is idempotent, so I can't think of a reason why it would be required to skip it. So, we might be able to change CONFIG_SKIP_CPU_INIT_CRIT to CONFIG_SKIP_LOWLEVEL_INIT in most cases. I'm just hesitant to do so because I don't have a variety of boards to test on.
Michael
The TS-7800 needs to skip SDRAM initialization since it loads from RAM, but the CPU should still be initialized to the correct state. Thus we add an #ifdef around the call to the lowlevel_init function.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- arch/arm/cpu/arm926ejs/at91/Makefile | 2 ++ arch/arm/cpu/arm926ejs/davinci/Makefile | 2 ++ arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 ++ arch/arm/cpu/arm926ejs/start.S | 3 +++ 4 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index 7fb1a0a..efe9e9bd 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -42,8 +42,10 @@ COBJS-y += reset.o COBJS-y += timer.o
ifndef CONFIG_SKIP_CPU_INIT_CRIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS-y := lowlevel_init.o endif +endif
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 3442f6e..d283d61 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -37,8 +37,10 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o SOBJS = reset.o
ifndef CONFIG_SKIP_CPU_INIT_CRIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS += lowlevel_init.o endif +endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile index 780fe18..8045e53 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Makefile +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -34,8 +34,10 @@ COBJS-y += dram.o COBJS-y += timer.o
ifndef CONFIG_SKIP_CPU_INIT_CRIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS := lowlevel_init.o endif +endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index c0a2532..2e1d5ec 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -334,12 +334,15 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_CPU_INIT_CRIT */
Dear Michael Spang,
In message 1300391223-11879-7-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The TS-7800 needs to skip SDRAM initialization since it loads from RAM, but the CPU should still be initialized to the correct state. Thus we add an #ifdef around the call to the lowlevel_init function.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
How can the SDRAM be initialized when the CPU is not?
Best regards,
Wolfgang Denk
Hi Wolfgang et al.,
(replying both to 5/9 and 6/9 here)
Le 25/04/2011 01:55, Wolfgang Denk a écrit :
This is an inconsistency between architectures which I dislike.
Then these two config options could be defined for other architectures as well.
Also, what in case we should want to skip only cpu_init_crit and not lowlevel_init? If we need to handle these separately, then we need 2 CONFIG options.
Agreed this complete separation could be useful in case U-Boot is not the code executed on startup, and this startup code does the CPU initialization but leaves the rest to U-Boot for commodity.
How can the SDRAM be initialized when the CPU is not?
Debugging sessions come to mind, where the debugger resets the target and initializes SDRAM to load the target code. I've also seen cases on multiple-core ICs where an ARM core starts with SDRAM access already working, but U-Boot was not involved.
The idea is that during board bring-up, rather than have people try and neutralize some code in assembly language startup files, they just temporarily define the configuration options CONFIG_SKIP_* in their board's config header file (and, for those boards that have an IPL of some sort before U-Boot, they keep the relevant CONFIG_SKIP_* there once debugged).
Best regards,
Wolfgang Denk
Amicalement,
On Sun, Apr 24, 2011 at 7:55 PM, Wolfgang Denk wd@denx.de wrote:
Dear Michael Spang,
In message 1300391223-11879-7-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The TS-7800 needs to skip SDRAM initialization since it loads from RAM, but the CPU should still be initialized to the correct state. Thus we add an #ifdef around the call to the lowlevel_init function.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
How can the SDRAM be initialized when the CPU is not?
It is already initialized, but even if the state matches what U-Boot expects now, I'm not confident the desired settings will never change. So I think it is best to just run U-Boot's initialization anyway.
Michael
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- MAKEALL | 1 + board/technologic/ts7800/Makefile | 46 +++++++++++ board/technologic/ts7800/ts7800.c | 36 +++++++++ boards.cfg | 1 + include/configs/ts7800.h | 152 +++++++++++++++++++++++++++++++++++++ 5 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 include/configs/ts7800.h
diff --git a/MAKEALL b/MAKEALL index a732e6a..5cd4155 100755 --- a/MAKEALL +++ b/MAKEALL @@ -344,6 +344,7 @@ LIST_ARM9=" \ edb9315 \ edb9315a \ edminiv2 \ + ts7800 \ guruplug \ imx27lite \ jadecpu \ diff --git a/board/technologic/ts7800/Makefile b/board/technologic/ts7800/Makefile new file mode 100644 index 0000000..3a02b04 --- /dev/null +++ b/board/technologic/ts7800/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2010-2011 Michael Spang mspang@csclub.uwaterloo.ca +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +LIB = $(obj)lib$(BOARD).o + +COBJS := ts7800.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/technologic/ts7800/ts7800.c b/board/technologic/ts7800/ts7800.c new file mode 100644 index 0000000..4937436 --- /dev/null +++ b/board/technologic/ts7800/ts7800.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2010-2011 Michael Spang mspang@csclub.uwaterloo.ca + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* Technologic's MBR uses machine type 526, however the mainline + machine type is 1652. Set the machtype environment variable + to 526 to boot Technologic kernels. */ + gd->bd->bi_arch_number = MACH_TYPE_TS78XX; + gd->bd->bi_boot_params = 0x100; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 45c3102..b9d7939 100644 --- a/boards.cfg +++ b/boards.cfg @@ -106,6 +106,7 @@ magnesium arm arm926ejs imx27lite logicpd omap5912osk arm arm926ejs - ti omap edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon +ts7800 arm arm926ejs - technologic orion5x ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 mx51evk arm armv7 mx51evk freescale mx5 diff --git a/include/configs/ts7800.h b/include/configs/ts7800.h new file mode 100644 index 0000000..c07d132 --- /dev/null +++ b/include/configs/ts7800.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2010-2011 Michael Spang mspang@csclub.uwaterloo.ca + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_TS7800_H +#define _CONFIG_TS7800_H + +/* + * User Interface Configuration + */ + +#define CONFIG_IDENT_STRING " TS-7800" +#define CONFIG_SYS_PROMPT "TS-7800> " +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOOTDELAY 3 + +/* + * Flash Driver + */ + +#define CONFIG_SYS_NO_FLASH + +/* + * Commands Configuration + */ + +#include <config_cmd_default.h> +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII + +/* + * Serial Port Configuration + */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x2000 + +/* + * Limits + */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE /* Print Buffer Size */ \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* Max args to U-Boot commands */ + +/* + * System Components + */ + +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_TS78XX 1 /* Machine type */ +#define CONFIG_SYS_HZ 1000 + +/* + * Board Initialization + */ + +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot starts with RAM initialized */ + +/* MPP configuration need not be changed from power-on */ +#define ORION5X_MPP0_7 0x00000000 +#define ORION5X_MPP8_15 0x00000000 +#define ORION5X_MPP16_23 0x00000000 +#define ORION5X_GPIO_OUT_ENABLE 0xffffffff + +/* + * Memory Layout + */ + +#define CONFIG_SYS_TEXT_BASE 0x00008000 /* Boards loads U-Boot at 32 kB */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 /* Initial stack at 1 MB */ +#define CONFIG_SYS_MALLOC_LEN 0x00020000 /* Reserve 128 kB for malloc() */ + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* RAM starts at address 0 */ +#define CONFIG_NR_DRAM_BANKS 1 /* Board has one 128 MB RAM bank */ + +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* Load kernels at 8 MB */ + +/* Memtest skips the first 4k (vectors) and the last 2MB (U-Boot) */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07e00000 + +/* + * UART Driver + */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 ORION5X_UART1_BASE +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +/* + * Network Driver + */ + +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE +#define CONFIG_MVGBE_PORTS {1} +#define CONFIG_PRESERVE_LOCAL_MAC +#define CONFIG_PHY_BASE_ADR 0 +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_ENV_OVERWRITE +#endif + +/* + * Linux + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#endif /* _CONFIG_TS7800_H */
Dear Michael Spang,
In message 1300391223-11879-8-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
MAKEALL | 1 + board/technologic/ts7800/Makefile | 46 +++++++++++ board/technologic/ts7800/ts7800.c | 36 +++++++++ boards.cfg | 1 + include/configs/ts7800.h | 152 +++++++++++++++++++++++++++++++++++++ 5 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 include/configs/ts7800.h
diff --git a/MAKEALL b/MAKEALL index a732e6a..5cd4155 100755 --- a/MAKEALL +++ b/MAKEALL @@ -344,6 +344,7 @@ LIST_ARM9=" \ edb9315 \ edb9315a \ edminiv2 \
- ts7800 \ guruplug \ imx27lite \ jadecpu \
Boards don;t get added to MAKEALL any more; they will get picked automatically from boards.cfg.
...
+#define CONFIG_ENV_IS_NOWHERE 1
Please remove the '1' from all defines that select a feature only, i. e. that don;t actually care abut a specific numeric value.
Best regards,
Wolfgang Denk
On Sun, Apr 24, 2011 at 7:57 PM, Wolfgang Denk wd@denx.de wrote:
Dear Michael Spang,
In message 1300391223-11879-8-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
MAKEALL | 1 + board/technologic/ts7800/Makefile | 46 +++++++++++ board/technologic/ts7800/ts7800.c | 36 +++++++++ boards.cfg | 1 + include/configs/ts7800.h | 152 +++++++++++++++++++++++++++++++++++++ 5 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 include/configs/ts7800.h
diff --git a/MAKEALL b/MAKEALL index a732e6a..5cd4155 100755 --- a/MAKEALL +++ b/MAKEALL @@ -344,6 +344,7 @@ LIST_ARM9=" \ edb9315 \ edb9315a \ edminiv2 \
- ts7800 \
guruplug \ imx27lite \ jadecpu \
Boards don;t get added to MAKEALL any more; they will get picked automatically from boards.cfg.
...
+#define CONFIG_ENV_IS_NOWHERE 1
Please remove the '1' from all defines that select a feature only, i. e. that don;t actually care abut a specific numeric value.
Ok I'll drop the change to MAKEALL and update the #defines.
Michael
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++++++++++++++++++++++++++++++++++ include/configs/ts7800.h | 47 ++++++++++++++++++++++++++-- 3 files changed, 113 insertions(+), 3 deletions(-) create mode 100644 drivers/mtd/nand/ts7800_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 8b598f6..897e6c2 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif
diff --git a/drivers/mtd/nand/ts7800_nand.c b/drivers/mtd/nand/ts7800_nand.c new file mode 100644 index 0000000..8b9fe0c --- /dev/null +++ b/drivers/mtd/nand/ts7800_nand.c @@ -0,0 +1,68 @@ +/* + * Based on arch/arm/mach-orion5x/ts78xx-setup.c from Linux + * by Alexander Clouter alex@digriz.org.uk. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <nand.h> + +/* + * hardware specific access to control-lines + * + * ctrl: + * NAND_NCE: bit 0 -> bit 2 + * NAND_CLE: bit 1 -> bit 1 + * NAND_ALE: bit 2 -> bit 0 + */ +static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + unsigned char bits; + + bits = (ctrl & NAND_NCE) << 2; + bits |= ctrl & NAND_CLE; + bits |= (ctrl & NAND_ALE) >> 2; + + writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd) +{ + return readb(TS_NAND_CTRL) & 0x20; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->options = NAND_USE_FLASH_BBT; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = ts78xx_ts_nand_cmd_ctrl; + nand->dev_ready = ts78xx_ts_nand_dev_ready; + nand->chip_delay = 15; + return 0; +} diff --git a/include/configs/ts7800.h b/include/configs/ts7800.h index c07d132..0d8cc10 100644 --- a/include/configs/ts7800.h +++ b/include/configs/ts7800.h @@ -33,10 +33,11 @@ #define CONFIG_BOOTDELAY 3
/* - * Flash Driver + * Flash Configuration */
-#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NO_FLASH /* TS-7800 has only NAND flash */ +#define CONFIG_USE_NAND 0 /* Disable NAND by default */
/* * Commands Configuration @@ -46,6 +47,11 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_MII
+#if CONFIG_USE_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#endif + /* * Serial Port Configuration */ @@ -57,9 +63,21 @@ * Environment Configuration */
-#define CONFIG_ENV_IS_NOWHERE 1 +#if CONFIG_USE_NAND + +#define CONFIG_ENV_IS_IN_NAND + +#define CONFIG_ENV_OFFSET 0x00320000 /* 128k(mbr) + 3m(kernel) */ +#define CONFIG_ENV_SIZE 0x00020000 /* 128k */ +#define CONFIG_ENV_RANGE 0x00100000 /* 1m(env) */ + +#else + +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x2000
+#endif + /* * Limits */ @@ -112,6 +130,29 @@ #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07e00000
+#define ORION5X_ADR_PCI_MEM 0xe8000000 /* Match Linux (FPGA) */ +#define ORION5X_SZ_PCI_MEM 0x08000000 + +/* + * Flash Driver + */ + +#ifdef CONFIG_CMD_NAND + +#define TS_NAND_CTRL 0xe8000800 +#define TS_NAND_DATA 0xe8000804 + +#define CONFIG_NAND_TS7800 +#define CONFIG_SYS_NAND_BASE TS_NAND_DATA +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=gen_nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=gen_nand:128k(mbr),3m(uboot),1m(env),4m(linux),-(rootfs)" + +#endif + /* * UART Driver */
On Thu, 17 Mar 2011 15:47:02 -0400 Michael Spang mspang@csclub.uwaterloo.ca wrote:
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++++++++++++++++++++++++++++++++++ include/configs/ts7800.h | 47 ++++++++++++++++++++++++++-- 3 files changed, 113 insertions(+), 3 deletions(-) create mode 100644 drivers/mtd/nand/ts7800_nand.c
Acked-by: Scott Wood scottwood@freescale.com
-Scott
Dear Michael Spang,
In message 1300391223-11879-9-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Please provide exact reference, see bullet # 4 at http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 8b598f6..897e6c2 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif
Please keep the list sorted.
Best regards,
Wolfgang Denk
On Sun, Apr 24, 2011 at 7:59 PM, Wolfgang Denk wd@denx.de wrote:
Dear Michael Spang,
In message 1300391223-11879-9-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Please provide exact reference, see bullet # 4 at http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign
Will add the following:
[upstream commit 75bb6b9aab3255f440ef4e72a31978d1681105d6]
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 8b598f6..897e6c2 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif
Please keep the list sorted.
Ok. The surrounding two are not correct either, not sure if I should fix them.
Michael
Dear Michael Spang,
In message BANLkTinwTNqubP4pZdJePb_5doEzSvwnWA@mail.gmail.com you wrote:
Please provide exact reference, see bullet # 4 at http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign
Will add the following:
[upstream commit 75bb6b9aab3255f440ef4e72a31978d1681105d6]
Please follow the example given.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 8b598f6..897e6c2 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif
Please keep the list sorted.
Ok. The surrounding two are not correct either, not sure if I should fix them.
Please do. Thanks.
Best regards,
Wolfgang Denk
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca --- doc/README.ts7800 | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 doc/README.ts7800
diff --git a/doc/README.ts7800 b/doc/README.ts7800 new file mode 100644 index 0000000..6a6ab94 --- /dev/null +++ b/doc/README.ts7800 @@ -0,0 +1,84 @@ +Booting +------- + +The TS-7800 boots initially from a proprietary bootloader on the FPGA +called TS-BOOTROM. TS-BOOTROM loads a small image from the MBR of the +onboard NAND or SD card into RAM, and executes it. The default MBR is +intended to boot a Linux kernel. + +The TS-7800 port of U-Boot takes the place of the Linux kernel in this +configuration, and is therefore loaded and executed by the MBR. The +MBR also creates an ATAG structure intended for Linux, but U-Boot +ignores it. + +NAND layout +----------- + +NAND support is not enabled by default because U-Boot will overwrite +part of it with its environment. To enable NAND support, enable +CONFIG_USE_NAND in include/configs/ts7800.h. + +The default NAND partition layout used by Technologic and Linux is: + + 128k(mbr),4m(linux),4m(initrd),-(rootfs) + +For U-Boot, we split the linux partition into a partition for the +U-Boot code and a partition for the U-Boot environment. The initrd +partition is not used, and is renamed to "linux". The new layout is: + + 128k(mbr),3m(uboot),1m(env),4m(linux),-(rootfs) + +When NAND support is enabled, this string is available in the U-Boot +default environment as the "mtdparts" variable. You may wish to use +this layout for Linux as well by adding it to the Linux command line. +For example: + + setenv bootargs console=ttyS0,115200n8 ${mtdparts} + +Installing U-Boot +----------------- + +To install U-Boot to the onboard flash, write u-boot.bin to the kernel +partition on the flash. From Linux this might be done as follows: + + flash_eraseall /dev/mtd1 + nandwrite --pad /dev/mtd1 u-boot.bin + +When running from onboard flash, you may wish to enable NAND support +as described in the previous section. The environment is not preserved +unless you enable NAND support. + +To install U-Boot to an SD card, write u-boot.bin to the kernel +partition on the card. + +Booting Technologic Kernels +--------------------------- + +Technologic's kernels use a different machine type ID than upstream +kernels. U-Boot uses the upstream ID, so Technologic kernels will +not boot from U-Boot without the following workaround: + + setenv machid 0x20e + +The following commands will convert a Technologic kernel image +into U-Boot format: + + mkimage -A arm -O linux -T kernel -C none -a 0x8000 \ + -d kernel-image-latest.dd uImage + + mkimage -A arm -O linux -T ramdisk -C none -a 0x1000000 \ + -d initrd-busybox-rootfs-latest.dd initrd + +Then pass both images to the bootm command to boot. Note that with +U-Boot installed there is only one partition available for the kernel +and initrd. To use both changing the NAND partitioning may be +required. To do so you can use the mtdparts command in U-Boot and pass +${mtdparts} to linux. + +TS-7800 Wiki +------------ + +A useful resource about the TS-7800 is the TS-7800 wiki [1], +maintained by Alexander Clouter. + +[1] http://www.digriz.org.uk/ts78xx
Dear Michael Spang,
In message 1300391223-11879-10-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
doc/README.ts7800 | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 doc/README.ts7800
This should be added together with the original board support in a single patch.
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de You've no idea of what a poor opinion I have of myself, and how little I deserve it. - W. S. Gilbert
On Sun, Apr 24, 2011 at 8:01 PM, Wolfgang Denk wd@denx.de wrote:
Dear Michael Spang,
In message 1300391223-11879-10-git-send-email-mspang@csclub.uwaterloo.ca you wrote:
Signed-off-by: Michael Spang mspang@csclub.uwaterloo.ca
doc/README.ts7800 | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 doc/README.ts7800
This should be added together with the original board support in a single patch.
Ok will squash them.
Michael
On Thu, Mar 17, 2011 at 3:46 PM, Michael Spang mspang@csclub.uwaterloo.ca wrote:
The TS-7800 is an Orion5x implementation by Technologic Systems.
Albert, Wolfgang -
Thanks for reviewing my patch series and sorry for the delay in updating it.
Changelog: - Fixed all checkpatch errors. - Updated copyright year. - Renamed CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT and introduced new CONFIG_SKIP_LOWLEVEL_INIT that skips only lowlevel_init. - Documented machine type ID workaround in the README. - Removed "ddr" from name of orion5x_ddr_addr_decode_registers. - Allow the environment to override the MAC even if CONFIG_PRESERVE_LOCAL_MAC is set.
This is version 2 of this series. I forgot to update the subject line.
Michael
Le 17/03/2011 20:46, Michael Spang a écrit :
The TS-7800 is an Orion5x implementation by Technologic Systems.
Albert, Wolfgang -
Thanks for reviewing my patch series and sorry for the delay in updating it.
Hi Michael,
In return, sorry in advance for the delay in reviewing this new patch set -- I will do during the week-end, especially as I want to test on ED Mini V2 for regression.
Amicalement,
participants (9)
-
Albert ARIBAUD -
Albert ARIBAUD -
Aneesh V -
arden jay -
Michael Spang -
Mike Frysinger -
Scott Wood -
Tabi Timur-B04825 -
Wolfgang Denk