Hi Lukasz,

On 12/08/2011 10:24, Lukasz Majewski wrote:

This commit adds support for reading the D cache line size for armv7 architecture.

The get_dcache_line_size() function is supposed to work in conjunction with memalign call to provide D cache aligned DMA buffers.

Signed-off-by: Lukasz Majewskil.majewski@samsung.com Signed-off-by: Kyungmin Parkkyungmin.park@samsung.com CC: Aneesh Vaneesh@ti.com CC: Albert ARIBAUDalbert.u.boot@aribaud.net

---

arch/arm/cpu/armv7/cache_v7.c | 25 +++++++++++++++++++++++++ include/common.h | 1 + 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..bd0b1a8 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -246,6 +246,21 @@ static void v7_inval_tlb(void) CP15ISB; }

+/* Read the cache line size (bytes) */ +static int v7_dcache_line_size(void) +{

• u32 ccsidr, log2_line_len;
• ccsidr = get_ccsidr();
• log2_line_len = ((ccsidr& CCSIDR_LINE_SIZE_MASK)>>

• 		CCSIDR_LINE_SIZE_OFFSET) + 2;
  

• /* Converting from words to bytes */
• log2_line_len += 2;
• return 1<< log2_line_len;

+}

• void invalidate_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);

@@ -303,6 +318,11 @@ void flush_cache(unsigned long start, unsigned long size) { flush_dcache_range(start, start + size); }

+int get_dcache_line_size(void) +{

• return v7_dcache_line_size();

+} #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) { @@ -327,6 +347,11 @@ void arm_init_before_mmu(void) void flush_cache(unsigned long start, unsigned long size) { }

+int get_dcache_line_size(void) +{

• return 0;

+} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */

#ifndef CONFIG_SYS_ICACHE_OFF diff --git a/include/common.h b/include/common.h index 12a1074..b535300 100644 --- a/include/common.h +++ b/include/common.h @@ -622,6 +622,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); +int get_dcache_line_size(void);

/* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void);

I like the idea of a global cache line accessor, but:

1) Does it have to be a function? I don't know cache implementations where line size is not a constant, and a function might be overkill.

2) If it has to be a function, then I'd rather have the function introduced in arch/arm/lib/cache.c as a weak function returning 32, with armv7 providing a replacement.

Aneesh, that patch could affect your patch series as the magic 32 could then come from this weak function rather than be hard-coded.

Amicalement,

On Friday 12 August 2011 01:54 PM, Lukasz Majewski wrote:

This commit adds support for reading the D cache line size for armv7 architecture.

The get_dcache_line_size() function is supposed to work in conjunction with memalign call to provide D cache aligned DMA buffers.

Signed-off-by: Lukasz Majewskil.majewski@samsung.com Signed-off-by: Kyungmin Parkkyungmin.park@samsung.com CC: Aneesh Vaneesh@ti.com CC: Albert ARIBAUDalbert.u.boot@aribaud.net

---

arch/arm/cpu/armv7/cache_v7.c | 25 +++++++++++++++++++++++++ include/common.h | 1 + 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..bd0b1a8 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -246,6 +246,21 @@ static void v7_inval_tlb(void) CP15ISB; }

+/* Read the cache line size (bytes) */ +static int v7_dcache_line_size(void) +{

• u32 ccsidr, log2_line_len;
• ccsidr = get_ccsidr();
• log2_line_len = ((ccsidr& CCSIDR_LINE_SIZE_MASK)>>

• 		CCSIDR_LINE_SIZE_OFFSET) + 2;
  

• /* Converting from words to bytes */
• log2_line_len += 2;
• return 1<< log2_line_len;

+}

• void invalidate_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);

@@ -303,6 +318,11 @@ void flush_cache(unsigned long start, unsigned long size) { flush_dcache_range(start, start + size); }

+int get_dcache_line_size(void) +{

• return v7_dcache_line_size();

+} #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) { @@ -327,6 +347,11 @@ void arm_init_before_mmu(void) void flush_cache(unsigned long start, unsigned long size) { }

+int get_dcache_line_size(void) +{

• return 0;

+}

Does memalign() take 0 as input and if so what is the output. The GNU C library seems to mandate only that it's a power of 2. But the following man page seems to says that "The value of alignment must be a power of two and must be greater than or equal to the size of a word."

http://www.s-gms.ms.edus.si/cgi-bin/man-cgi?memalign+3C

Also, you seem to be using get_dcache_line_size() in MMC driver. Is this function defined for all platforms. Maybe, you must implement a weakly linked default function for all platforms?

best regards, Aneesh

This commit adds support for reading the D cache line size for armv7 architecture.

The get_dcache_line_size() function is supposed to work in conjunction with memalign call to provide D cache aligned DMA buffers.

Signed-off-by: Lukasz Majewski l.majewski@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Aneesh V aneesh@ti.com CC: Albert ARIBAUD albert.u.boot@aribaud.net --- Changes for v2: - Weak function get_dcache_line_size added to lib/cache.c for non armv7 architectures --- arch/arm/cpu/armv7/cache_v7.c | 15 +++++++++++++++ arch/arm/lib/cache.c | 11 +++++++++++ include/common.h | 1 + 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..0ff9a97 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -246,6 +246,21 @@ static void v7_inval_tlb(void) CP15ISB; }

+/* Read the cache line size (in bytes) */ +int get_dcache_line_size(void) +{ + u32 ccsidr, log2_line_len; + puts("222\n"); + ccsidr = get_ccsidr(); + + log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> + CCSIDR_LINE_SIZE_OFFSET) + 2; + /* Converting from words to bytes */ + log2_line_len += 2; + + return 1 << log2_line_len; +} + void invalidate_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..5ebf551 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,14 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + +/* Default implementation: */ +/* Read the default D CACHE LINE size */ +int __attribute__((weak)) get_dcache_line_size(void) +{ +#if defined(CONFIG_SYS_CACHE_LINE_SIZE) && !defined(CONFIG_SYS_DCACHE_OFF) + return CONFIG_SYS_CACHE_LINE_SIZE; +#else + return 8; /* Default alignment for memalign() */ +#endif +} diff --git a/include/common.h b/include/common.h index 12a1074..b535300 100644 --- a/include/common.h +++ b/include/common.h @@ -622,6 +622,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); +int get_dcache_line_size(void);

/* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void);

This commit adds support for reading the D cache line size for armv7 architecture.

The get_dcache_line_size() function is supposed to work in conjunction with memalign call to provide D cache aligned DMA buffers.

Signed-off-by: Lukasz Majewski l.majewski@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Aneesh V aneesh@ti.com CC: Albert ARIBAUD albert.u.boot@aribaud.net --- Changes for v2: - Weak function get_dcache_line_size added to lib/cache.c for non armv7 architectures --- arch/arm/cpu/armv7/cache_v7.c | 14 ++++++++++++++ arch/arm/lib/cache.c | 11 +++++++++++ include/common.h | 1 + 3 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..ea5a3e4 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -246,6 +246,20 @@ static void v7_inval_tlb(void) CP15ISB; }

+/* Read the cache line size (in bytes) */ +int get_dcache_line_size(void) +{ + u32 ccsidr, log2_line_len; + + ccsidr = get_ccsidr(); + log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> + CCSIDR_LINE_SIZE_OFFSET) + 2; + /* Converting from words to bytes */ + log2_line_len += 2; + + return 1 << log2_line_len; +} + void invalidate_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..5ebf551 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,14 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + +/* Default implementation: */ +/* Read the default D CACHE LINE size */ +int __attribute__((weak)) get_dcache_line_size(void) +{ +#if defined(CONFIG_SYS_CACHE_LINE_SIZE) && !defined(CONFIG_SYS_DCACHE_OFF) + return CONFIG_SYS_CACHE_LINE_SIZE; +#else + return 8; /* Default alignment for memalign() */ +#endif +} diff --git a/include/common.h b/include/common.h index 12a1074..b535300 100644 --- a/include/common.h +++ b/include/common.h @@ -622,6 +622,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); +int get_dcache_line_size(void);

/* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void);

The get_dcache_line_size() function is supposed to work in conjunction with memalign call to provide D cache aligned DMA buffers.

This commit adds support for reading the D cache line size for armv7 architecture. Moreover a default implementation of get_dcache_line_size() is provided.

Signed-off-by: Lukasz Majewski l.majewski@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com CC: Aneesh V aneesh@ti.com CC: Albert ARIBAUD albert.u.boot@aribaud.net --- Changes for v2: - Weak function get_dcache_line_size added to arch/arm/lib/cache.c Changes for v3: - __BIGGEST_ALIGNMENT__ GCC constant added Changes for v4: - Weak function get_dcache_line_size added to arch/arm/lib/cache.c for non armv7 architectures --- arch/arm/cpu/armv7/cache_v7.c | 14 ++++++++++++++ include/common.h | 1 + lib/Makefile | 1 + lib/cache.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 50 insertions(+), 0 deletions(-) create mode 100644 lib/cache.c

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..ea5a3e4 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -246,6 +246,20 @@ static void v7_inval_tlb(void) CP15ISB; }

+/* Read the cache line size (in bytes) */ +int get_dcache_line_size(void) +{ + u32 ccsidr, log2_line_len; + + ccsidr = get_ccsidr(); + log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> + CCSIDR_LINE_SIZE_OFFSET) + 2; + /* Converting from words to bytes */ + log2_line_len += 2; + + return 1 << log2_line_len; +} + void invalidate_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); diff --git a/include/common.h b/include/common.h index 12a1074..b535300 100644 --- a/include/common.h +++ b/include/common.h @@ -622,6 +622,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); +int get_dcache_line_size(void);

/* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void); diff --git a/lib/Makefile b/lib/Makefile index 884f64c..c0070c2 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_SHA1) += sha1.o COBJS-$(CONFIG_SHA256) += sha256.o COBJS-y += strmhz.o COBJS-$(CONFIG_RBTREE) += rbtree.o +COBJS-y += cache.o endif

COBJS-y += ctype.o diff --git a/lib/cache.c b/lib/cache.c new file mode 100644 index 0000000..b8f49ce --- /dev/null +++ b/lib/cache.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2011 SAMSUNG Electronics + * Łukasz Majewski l.majewski@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* Read the default Data CACHE LINE size */ +int __attribute__((weak)) get_dcache_line_size(void) +{ +#if defined(CONFIG_SYS_CACHE_LINE_SIZE) && !defined(CONFIG_SYS_DCACHE_OFF) + return CONFIG_SYS_CACHE_LINE_SIZE; +#else + return __BIGGEST_ALIGNMENT__; /* Constant defined by GCC compiler */ +#endif +}